1 /* $NetBSD: ti_div_clock.c,v 1.3 2025/12/16 12:20:22 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2019 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: ti_div_clock.c,v 1.3 2025/12/16 12:20:22 skrll Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/device.h> 35 #include <sys/kmem.h> 36 #include <sys/bus.h> 37 38 #include <dev/clk/clk_backend.h> 39 40 #include <dev/fdt/fdtvar.h> 41 42 static const struct device_compatible_entry compat_data[] = { 43 { .compat = "ti,composite-divider-clock" }, 44 { .compat = "ti,divider-clock" }, 45 DEVICE_COMPAT_EOL 46 }; 47 48 static int ti_div_clock_match(device_t, cfdata_t, void *); 49 static void ti_div_clock_attach(device_t, device_t, void *); 50 51 static struct clk *ti_div_clock_decode(device_t, int, const void *, size_t); 52 53 static const struct fdtbus_clock_controller_func ti_div_clock_fdt_funcs = { 54 .decode = ti_div_clock_decode 55 }; 56 57 static struct clk *ti_div_clock_get(void *, const char *); 58 static void ti_div_clock_put(void *, struct clk *); 59 static int ti_div_clock_enable(void *, struct clk *); 60 static u_int ti_div_clock_get_rate(void *, struct clk *); 61 static struct clk *ti_div_clock_get_parent(void *, struct clk *); 62 63 static const struct clk_funcs ti_div_clock_clk_funcs = { 64 .get = ti_div_clock_get, 65 .put = ti_div_clock_put, 66 .enable = ti_div_clock_enable, 67 .get_rate = ti_div_clock_get_rate, 68 .get_parent = ti_div_clock_get_parent, 69 }; 70 71 struct ti_div_clock_softc { 72 device_t sc_dev; 73 int sc_phandle; 74 bus_space_tag_t sc_bst; 75 bus_space_handle_t sc_bsh; 76 77 struct clk_domain sc_clkdom; 78 struct clk sc_clk; 79 }; 80 81 #define RD4(sc) \ 82 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, 0) 83 #define WR4(sc, val) \ 84 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, 0, (val)) 85 86 CFATTACH_DECL_NEW(ti_div_clock, sizeof(struct ti_div_clock_softc), 87 ti_div_clock_match, ti_div_clock_attach, NULL, NULL); 88 89 static int 90 ti_div_clock_match(device_t parent, cfdata_t cf, void *aux) 91 { 92 const struct fdt_attach_args *faa = aux; 93 94 return of_compatible_match(faa->faa_phandle, compat_data); 95 } 96 97 static void 98 ti_div_clock_attach(device_t parent, device_t self, void *aux) 99 { 100 struct ti_div_clock_softc * const sc = device_private(self); 101 const struct fdt_attach_args *faa = aux; 102 const int phandle = faa->faa_phandle; 103 bus_addr_t addr, base_addr; 104 105 const int prcm_phandle = OF_parent(OF_parent(phandle)); 106 if (fdtbus_get_reg(phandle, 0, &addr, NULL) != 0 || 107 fdtbus_get_reg(prcm_phandle, 0, &base_addr, NULL) != 0) { 108 aprint_error(": couldn't get registers\n"); 109 return; 110 } 111 112 sc->sc_dev = self; 113 sc->sc_phandle = phandle; 114 sc->sc_bst = faa->faa_bst; 115 if (bus_space_map(sc->sc_bst, base_addr + addr, 4, 0, &sc->sc_bsh) != 0) { 116 aprint_error(": couldn't map registers\n"); 117 return; 118 } 119 120 sc->sc_clkdom.name = device_xname(self); 121 sc->sc_clkdom.funcs = &ti_div_clock_clk_funcs; 122 sc->sc_clkdom.priv = sc; 123 124 sc->sc_clk.domain = &sc->sc_clkdom; 125 sc->sc_clk.name = kmem_asprintf("%s", faa->faa_name); 126 clk_attach(&sc->sc_clk); 127 128 aprint_naive("\n"); 129 aprint_normal(": TI divider clock (%s)\n", sc->sc_clk.name); 130 131 fdtbus_register_clock_controller(self, phandle, &ti_div_clock_fdt_funcs); 132 } 133 134 static struct clk * 135 ti_div_clock_decode(device_t dev, int cc_phandle, const void *data, 136 size_t len) 137 { 138 struct ti_div_clock_softc * const sc = device_private(dev); 139 140 return &sc->sc_clk; 141 } 142 143 static struct clk * 144 ti_div_clock_get(void *priv, const char *name) 145 { 146 struct ti_div_clock_softc * const sc = priv; 147 148 return &sc->sc_clk; 149 } 150 151 static void 152 ti_div_clock_put(void *priv, struct clk *clk) 153 { 154 } 155 156 static int 157 ti_div_clock_enable(void *priv, struct clk *clk) 158 { 159 struct clk *clk_parent = clk_get_parent(clk); 160 161 return clk_enable(clk_parent); 162 } 163 164 static u_int 165 ti_div_clock_get_rate(void *priv, struct clk *clk) 166 { 167 struct ti_div_clock_softc * const sc = priv; 168 struct clk *clk_parent = clk_get_parent(clk); 169 uint64_t parent_rate; 170 uint32_t val, max_val, mask; 171 u_int div, max_div, bit_shift; 172 173 if (clk_parent == NULL) 174 return 0; 175 176 if (of_hasprop(sc->sc_phandle, "ti,index-power-of-two")) 177 return EINVAL; /* not supported yet */ 178 179 const int start_index = of_hasprop(sc->sc_phandle, "ti,index-starts-at-one") ? 1 : 0; 180 181 if (of_getprop_uint32(sc->sc_phandle, "ti,bit-shift", &bit_shift) != 0) 182 bit_shift = 0; 183 184 if (of_getprop_uint32(sc->sc_phandle, "ti,max-div", &max_div) == 0) { 185 max_val = start_index + max_div; 186 while (!powerof2(max_val)) 187 max_val++; 188 mask = (max_val - 1) << bit_shift; 189 } else { 190 /* 191 * The bindings allow for this, but it is not yet supported 192 * by this driver. 193 */ 194 return EINVAL; 195 } 196 197 val = RD4(sc); 198 div = __SHIFTOUT(val, mask) + (start_index ? 0 : 1); 199 if (div == 0) 200 return EINVAL; 201 202 parent_rate = clk_get_rate(clk_parent); 203 204 return (u_int)(parent_rate / div); 205 } 206 207 static struct clk * 208 ti_div_clock_get_parent(void *priv, struct clk *clk) 209 { 210 struct ti_div_clock_softc * const sc = priv; 211 212 return fdtbus_clock_get_index(sc->sc_phandle, 0); 213 } 214
Indexes created Sun Oct 25 00:26:45 UTC 2026