1 /* $NetBSD: ti_div_clock.c,v 1.2 2021/01/27 03:10:20 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2019 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: ti_div_clock.c,v 1.2 2021/01/27 03:10:20 thorpej Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/device.h> 35 #include <sys/kmem.h> 36 #include <sys/bus.h> 37 38 #include <dev/clk/clk_backend.h> 39 40 #include <dev/fdt/fdtvar.h> 41 42 static const struct device_compatible_entry compat_data[] = { 43 { .compat = "ti,divider-clock" }, 44 DEVICE_COMPAT_EOL 45 }; 46 47 static int ti_div_clock_match(device_t, cfdata_t, void *); 48 static void ti_div_clock_attach(device_t, device_t, void *); 49 50 static struct clk *ti_div_clock_decode(device_t, int, const void *, size_t); 51 52 static const struct fdtbus_clock_controller_func ti_div_clock_fdt_funcs = { 53 .decode = ti_div_clock_decode 54 }; 55 56 static struct clk *ti_div_clock_get(void *, const char *); 57 static void ti_div_clock_put(void *, struct clk *); 58 static u_int ti_div_clock_get_rate(void *, struct clk *); 59 static struct clk *ti_div_clock_get_parent(void *, struct clk *); 60 61 static const struct clk_funcs ti_div_clock_clk_funcs = { 62 .get = ti_div_clock_get, 63 .put = ti_div_clock_put, 64 .get_rate = ti_div_clock_get_rate, 65 .get_parent = ti_div_clock_get_parent, 66 }; 67 68 struct ti_div_clock_softc { 69 device_t sc_dev; 70 int sc_phandle; 71 bus_space_tag_t sc_bst; 72 bus_space_handle_t sc_bsh; 73 74 struct clk_domain sc_clkdom; 75 struct clk sc_clk; 76 }; 77 78 #define RD4(sc) \ 79 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, 0) 80 #define WR4(sc, val) \ 81 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, 0, (val)) 82 83 CFATTACH_DECL_NEW(ti_div_clock, sizeof(struct ti_div_clock_softc), 84 ti_div_clock_match, ti_div_clock_attach, NULL, NULL); 85 86 static int 87 ti_div_clock_match(device_t parent, cfdata_t cf, void *aux) 88 { 89 const struct fdt_attach_args *faa = aux; 90 91 return of_compatible_match(faa->faa_phandle, compat_data); 92 } 93 94 static void 95 ti_div_clock_attach(device_t parent, device_t self, void *aux) 96 { 97 struct ti_div_clock_softc * const sc = device_private(self); 98 const struct fdt_attach_args *faa = aux; 99 const int phandle = faa->faa_phandle; 100 bus_addr_t addr, base_addr; 101 102 const int prcm_phandle = OF_parent(OF_parent(phandle)); 103 if (fdtbus_get_reg(phandle, 0, &addr, NULL) != 0 || 104 fdtbus_get_reg(prcm_phandle, 0, &base_addr, NULL) != 0) { 105 aprint_error(": couldn't get registers\n"); 106 return; 107 } 108 109 sc->sc_dev = self; 110 sc->sc_phandle = phandle; 111 sc->sc_bst = faa->faa_bst; 112 if (bus_space_map(sc->sc_bst, base_addr + addr, 4, 0, &sc->sc_bsh) != 0) { 113 aprint_error(": couldn't map registers\n"); 114 return; 115 } 116 117 sc->sc_clkdom.name = device_xname(self); 118 sc->sc_clkdom.funcs = &ti_div_clock_clk_funcs; 119 sc->sc_clkdom.priv = sc; 120 121 sc->sc_clk.domain = &sc->sc_clkdom; 122 sc->sc_clk.name = kmem_asprintf("%s", faa->faa_name); 123 clk_attach(&sc->sc_clk); 124 125 aprint_naive("\n"); 126 aprint_normal(": TI divider clock (%s)\n", sc->sc_clk.name); 127 128 fdtbus_register_clock_controller(self, phandle, &ti_div_clock_fdt_funcs); 129 } 130 131 static struct clk * 132 ti_div_clock_decode(device_t dev, int cc_phandle, const void *data, 133 size_t len) 134 { 135 struct ti_div_clock_softc * const sc = device_private(dev); 136 137 return &sc->sc_clk; 138 } 139 140 static struct clk * 141 ti_div_clock_get(void *priv, const char *name) 142 { 143 struct ti_div_clock_softc * const sc = priv; 144 145 return &sc->sc_clk; 146 } 147 148 static void 149 ti_div_clock_put(void *priv, struct clk *clk) 150 { 151 } 152 153 static u_int 154 ti_div_clock_get_rate(void *priv, struct clk *clk) 155 { 156 struct ti_div_clock_softc * const sc = priv; 157 struct clk *clk_parent = clk_get_parent(clk); 158 uint64_t parent_rate; 159 uint32_t val, max_val, mask; 160 u_int div, max_div, bit_shift; 161 162 if (clk_parent == NULL) 163 return 0; 164 165 if (of_hasprop(sc->sc_phandle, "ti,index-power-of-two")) 166 return EINVAL; /* not supported yet */ 167 168 const int start_index = of_hasprop(sc->sc_phandle, "ti,index-starts-at-one") ? 1 : 0; 169 170 if (of_getprop_uint32(sc->sc_phandle, "ti,bit-shift", &bit_shift) != 0) 171 bit_shift = 0; 172 173 if (of_getprop_uint32(sc->sc_phandle, "ti,max-div", &max_div) == 0) { 174 max_val = start_index + max_div; 175 while (!powerof2(max_val)) 176 max_val++; 177 mask = (max_val - 1) << bit_shift; 178 } else { 179 /* 180 * The bindings allow for this, but it is not yet supported 181 * by this driver. 182 */ 183 return EINVAL; 184 } 185 186 val = RD4(sc); 187 div = __SHIFTOUT(val, mask) + (start_index ? 0 : 1); 188 if (div == 0) 189 return EINVAL; 190 191 parent_rate = clk_get_rate(clk_parent); 192 193 return (u_int)(parent_rate / div); 194 } 195 196 static struct clk * 197 ti_div_clock_get_parent(void *priv, struct clk *clk) 198 { 199 struct ti_div_clock_softc * const sc = priv; 200 201 return fdtbus_clock_get_index(sc->sc_phandle, 0); 202 } 203
Indexes created Sat Sep 20 22:09:52 GMT 2025