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  /src/sys/compat/linux/common/
linux_blkio.h 46 #define LINUX_BLKROSET _LINUX_IO(0x12, 93)
47 #define LINUX_BLKROGET _LINUX_IO(0x12, 94)
48 #define LINUX_BLKRRPART _LINUX_IO(0x12, 95)
49 #define LINUX_BLKGETSIZE _LINUX_IO(0x12, 96)
50 #define LINUX_BLKFLSBUF _LINUX_IO(0x12, 97)
51 #define LINUX_BLKRASET _LINUX_IO(0x12, 98)
52 #define LINUX_BLKRAGET _LINUX_IO(0x12, 99)
53 #define LINUX_BLKFRASET _LINUX_IO(0x12, 100)
54 #define LINUX_BLKFRAGET _LINUX_IO(0x12, 101)
55 #define LINUX_BLKSECTSET _LINUX_IO(0x12, 102
    [all...]
  /src/crypto/external/apache2/openssl/lib/libcrypto/arch/riscv64/
aes-riscv64-zkn.S 16 ld x13,0(x12)
17 ld x14,8(x12)
20 lwu x30,240(x12)
35 add x12,x12,16
38 ld x13,0(x12)
39 ld x14,8(x12)
51 ld x13,16(x12)
52 ld x14,24(x12)
78 lwu x30,240(x12)
    [all...]
  /src/external/gpl3/gcc.old/dist/libphobos/libdruntime/core/sys/linux/
fs.d 159 enum BLKROSET = _IO(0x12, 93); /// set device read-only
160 enum BLKROGET = _IO(0x12, 94); /// get read-only status
161 enum BLKRRPART = _IO(0x12, 95); /// re-read partition table
162 enum BLKGETSIZE = _IO(0x12, 96); /// return device size
163 enum BLKFLSBUF = _IO(0x12, 97); /// flush buffer cache
164 enum BLKRASET = _IO(0x12, 98); /// set read ahead for block device
165 enum BLKRAGET = _IO(0x12, 99); /// get current read ahead setting
166 enum BLKFRASET = _IO(0x12, 100); /// set filesystem
167 enum BLKFRAGET = _IO(0x12, 101); /// get filesystem
168 enum BLKSECTSET = _IO(0x12, 102); /// set max sectors per reques
    [all...]
  /src/external/gpl3/gdb/dist/gdb/testsuite/gdb.disasm/
t13_otr.s 6 .org 0x12
11 bra 0x12+.+2 ;4012
12 brn 0x12+.+2 ;4112
13 bhi 0x12+.+2 ;4212
14 bls 0x12+.+2 ;4312
15 bcc 0x12+.+2 ;4412
16 bcs 0x12+.+2 ;4512
17 bne 0x12+.+2 ;4612
18 beq 0x12+.+2 ;4712
19 bvc 0x12+.+2 ;4812
    [all...]
  /src/external/gpl3/gdb.old/dist/gdb/testsuite/gdb.disasm/
t13_otr.s 6 .org 0x12
11 bra 0x12+.+2 ;4012
12 brn 0x12+.+2 ;4112
13 bhi 0x12+.+2 ;4212
14 bls 0x12+.+2 ;4312
15 bcc 0x12+.+2 ;4412
16 bcs 0x12+.+2 ;4512
17 bne 0x12+.+2 ;4612
18 beq 0x12+.+2 ;4712
19 bvc 0x12+.+2 ;4812
    [all...]
  /src/crypto/external/apache2/openssl/lib/libcrypto/arch/riscv32/
aes-riscv32-zkn.S 17 lw x13,0(x12)
18 lw x14,4(x12)
19 lw x15,8(x12)
20 lw x16,12(x12)
23 lw x30,240(x12)
36 add x12,x12,16
37 lw x13,0(x12)
38 lw x14,4(x12)
39 lw x15,8(x12)
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
smu7_powertune.h 29 #define DIDT_SQ_CTRL0__UNUSED_0__SHIFT 0x12
31 #define DIDT_TD_CTRL0__UNUSED_0__SHIFT 0x12
33 #define DIDT_TCP_CTRL0__UNUSED_0__SHIFT 0x12
  /src/sys/dev/pci/bktr/
bktr_audio.c 234 msp_dpl_write(bktr, bktr->msp_addr, 0x12, 0x0000, 0x0000); /* volume to MUTE */
237 msp_dpl_write(bktr, bktr->msp_addr, 0x12, 0x0000, 0x7300); /* 0 db volume */
242 msp_dpl_write(bktr, bktr->msp_addr, 0x12, 0x0000, 0x7300); /* 0 db volume */
243 msp_dpl_write(bktr, bktr->msp_addr, 0x12, 0x000d, 0x1900); /* scart prescale */
244 msp_dpl_write(bktr, bktr->msp_addr, 0x12, 0x0008, 0x0220); /* SCART | STEREO */
245 msp_dpl_write(bktr, bktr->msp_addr, 0x12, 0x0013, 0x0000); /* DSP In = SC1_IN_L/R */
250 msp_dpl_write(bktr, bktr->msp_addr, 0x12, 0x0000, 0x7300); /* 0 db volume */
251 msp_dpl_write(bktr, bktr->msp_addr, 0x12, 0x000d, 0x1900); /* scart prescale */
252 msp_dpl_write(bktr, bktr->msp_addr, 0x12, 0x0008, 0x0220); /* SCART | STEREO */
253 msp_dpl_write(bktr, bktr->msp_addr, 0x12, 0x0013, 0x0200); /* DSP In = SC2_IN_L/R *
    [all...]
  /src/crypto/external/apache2/openssl/lib/libcrypto/arch/aarch64/
ecp_sm2p256-armv8.S 53 ldp x11,x12,[x2]
58 sbcs x8,x8,x12
91 ldp x11,x12,[x2]
97 csel x12,xzr,x12,eq
103 adcs x8,x8,x12
135 ldp x11,x12,[x2]
141 csel x12,xzr,x12,eq
147 adcs x8,x8,x12
    [all...]
poly1305-armv8.S 43 adrp x12,poly1305_blocks
44 add x12,x12,#:lo12:.Lpoly1305_blocks
52 csel x12,x12,x7,eq
58 stp x12,x13,[x2]
93 mul x12,x4,x7 // h0*r0
100 adds x12,x12,x10
121 adds x4,x12,x1
    [all...]
  /src/crypto/external/apache2/openssl/lib/libcrypto/arch/arm/
ecp_sm2p256-armv8.S 54 ldp x11,x12,[x2]
59 sbcs x8,x8,x12
92 ldp x11,x12,[x2]
98 csel x12,xzr,x12,eq
104 adcs x8,x8,x12
136 ldp x11,x12,[x2]
142 csel x12,xzr,x12,eq
148 adcs x8,x8,x12
    [all...]
poly1305-armv8.S 44 adrp x12,poly1305_blocks
45 add x12,x12,#:lo12:.Lpoly1305_blocks
53 csel x12,x12,x7,eq
59 stp x12,x13,[x2]
94 mul x12,x4,x7 // h0*r0
101 adds x12,x12,x10
122 adds x4,x12,x1
    [all...]
  /src/sys/dev/i2c/
mpl115areg.h 49 #define MPL115A_CONVERT 0x12
  /src/sys/dev/ic/
apple_smcreg.h 49 #define APPLE_SMC_CMD_NTH_KEY 0x12
  /src/sys/dev/isa/
if_levar.h 36 #define NE2100_RAP 0x12
  /src/sys/dev/mii/
tlphyreg.h 46 #define MII_TLPHY_ST 0x12 /* Status register */
  /src/sys/dev/pci/
if_pcnreg.h 63 #define PCN16_RAP 0x12
  /src/sys/external/gpl2/dts/dist/include/dt-bindings/pmu/
exynos_ppmu.h 21 #define PPMU_RO_LATENCY 0x12
  /src/sys/dev/microcode/ral/
microcode.h 27 0x02, 0x1c, 0x12, 0x02, 0x13, 0xcb, 0xc2, 0x8c, 0x22, 0x22, 0x00,
29 0x8a, 0x93, 0xd2, 0xaf, 0x22, 0x02, 0x18, 0xda, 0x12, 0x1b, 0xe8,
31 0x90, 0x00, 0x03, 0xe0, 0x12, 0x08, 0x25, 0x00, 0xb0, 0x00, 0x00,
36 0xe5, 0x03, 0x30, 0x07, 0x03, 0xd2, 0x08, 0x22, 0x12, 0x17, 0xa5,
43 0x12, 0x11, 0x31, 0x90, 0x21, 0x00, 0xe0, 0xf5, 0x31, 0x60, 0x05,
44 0x12, 0x1b, 0x8a, 0x80, 0x03, 0x12, 0x1b, 0x3d, 0xe4, 0x90, 0x21,
45 0x03, 0xf0, 0xaf, 0x2d, 0x12, 0x1c, 0x62, 0x22, 0x75, 0x31, 0xff,
48 0xf0, 0x90, 0x21, 0x03, 0xf0, 0xaf, 0x2d, 0x12, 0x1c, 0x62, 0x22,
49 0x7e, 0x2b, 0x7f, 0x80, 0x7d, 0x03, 0x12, 0x04, 0x0e, 0x90, 0x34
    [all...]
  /src/sys/external/isc/libsodium/dist/src/libsodium/crypto_core/hsalsa20/ref2/
core_hsalsa20_ref2.c 23 x9, x10, x11, x12, x13, x14, x15; local
42 x12 = LOAD32_LE(k + 20);
51 x4 ^= ROTL32(x0 + x12, 7);
53 x12 ^= ROTL32(x8 + x4, 13);
54 x0 ^= ROTL32(x12 + x8, 18);
79 x12 ^= ROTL32(x15 + x14, 7);
80 x13 ^= ROTL32(x12 + x15, 9);
81 x14 ^= ROTL32(x13 + x12, 13);
  /src/sys/arch/arm/amlogic/
meson_canvasreg.h 34 #define DC_CAV_LUT_DATAL_REG CANVAS_REG(0x12)
  /src/sys/arch/hpcmips/vr/
vrkiureg.h 47 #define KIUSCANS 0x12
  /src/sys/netinet/
igmp.h 99 #define IGMP_v1_HOST_MEMBERSHIP_REPORT 0x12 /* v1 membership report */
  /src/external/gpl3/gdb.old/dist/sim/lm32/
lm32-sim.h 40 #define LM32_CSR_BP2 0x12
  /src/external/gpl3/gdb/dist/sim/lm32/
lm32-sim.h 40 #define LM32_CSR_BP2 0x12

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