1 /* $NetBSD: exynos5422_clock.c,v 1.18 2025/12/14 19:57:58 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "locators.h" 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: exynos5422_clock.c,v 1.18 2025/12/14 19:57:58 skrll Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/intr.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/atomic.h> 41 42 #include <dev/clk/clk_backend.h> 43 44 #include <arm/samsung/exynos_reg.h> 45 #include <arm/samsung/exynos_var.h> 46 #include <arm/samsung/exynos_clock.h> 47 48 #include <dev/fdt/fdtvar.h> 49 50 static struct clk *exynos5422_clock_decode(device_t, int, const void *, size_t); 51 52 static const struct fdtbus_clock_controller_func exynos5422_car_fdtclock_funcs = { 53 .decode = exynos5422_clock_decode 54 }; 55 56 /* DT clock ID to clock name mappings */ 57 static struct exynos5422_clock_id { 58 u_int id; 59 const char *name; 60 } exynos5422_clock_ids[] = { 61 { 1, "fin_pll" }, 62 { 2, "fout_apll" }, 63 { 3, "fout_cpll" }, 64 { 4, "fout_dpll" }, 65 { 5, "fout_epll" }, 66 { 6, "fout_rpll" }, 67 { 7, "fout_ipll" }, 68 { 8, "fout_spll" }, 69 { 9, "fout_vpll" }, 70 { 10, "fout_mpll" }, 71 { 11, "fout_bpll" }, 72 { 12, "fout_kpll" }, 73 { 128, "sclk_uart0" }, 74 { 129, "sclk_uart1" }, 75 { 130, "sclk_uart2" }, 76 { 131, "sclk_uart3" }, 77 { 132, "sclk_mmc0" }, 78 { 133, "sclk_mmc1" }, 79 { 134, "sclk_mmc2" }, 80 { 135, "sclk_spi0" }, 81 { 136, "sclk_spi1" }, 82 { 137, "sclk_spi2" }, 83 { 138, "sclk_i2s1" }, 84 { 139, "sclk_i2s2" }, 85 { 140, "sclk_pcm1" }, 86 { 141, "sclk_pcm2" }, 87 { 142, "sclk_spdif" }, 88 { 143, "sclk_hdmi" }, 89 { 144, "sclk_pixel" }, 90 { 145, "sclk_dp1" }, 91 { 146, "sclk_mipi1" }, 92 { 147, "sclk_fimd1" }, 93 { 148, "sclk_maudio0" }, 94 { 149, "sclk_maupcm0" }, 95 { 150, "sclk_usbd300" }, 96 { 151, "sclk_usbd301" }, 97 { 152, "sclk_usbphy300" }, 98 { 153, "sclk_usbphy301" }, 99 { 154, "sclk_unipro" }, 100 { 155, "sclk_pwm" }, 101 { 156, "sclk_gscl_wa" }, 102 { 157, "sclk_gscl_wb" }, 103 { 158, "sclk_hdmiphy" }, 104 { 159, "mau_epll" }, 105 { 160, "sclk_hsic_12m" }, 106 { 161, "sclk_mphy_ixtal24" }, 107 { 257, "uart0" }, 108 { 258, "uart1" }, 109 { 259, "uart2" }, 110 { 260, "uart3" }, 111 { 261, "i2c0" }, 112 { 262, "i2c1" }, 113 { 263, "i2c2" }, 114 { 264, "i2c3" }, 115 { 265, "usi0" }, 116 { 266, "usi1" }, 117 { 267, "usi2" }, 118 { 268, "usi3" }, 119 { 269, "i2c_hdmi" }, 120 { 270, "tsadc" }, 121 { 271, "spi0" }, 122 { 272, "spi1" }, 123 { 273, "spi2" }, 124 { 274, "keyif" }, 125 { 275, "i2s1" }, 126 { 276, "i2s2" }, 127 { 277, "pcm1" }, 128 { 278, "pcm2" }, 129 { 279, "pwm" }, 130 { 280, "spdif" }, 131 { 281, "usi4" }, 132 { 282, "usi5" }, 133 { 283, "usi6" }, 134 { 300, "aclk66_psgen" }, 135 { 301, "chipid" }, 136 { 302, "sysreg" }, 137 { 303, "tzpc0" }, 138 { 304, "tzpc1" }, 139 { 305, "tzpc2" }, 140 { 306, "tzpc3" }, 141 { 307, "tzpc4" }, 142 { 308, "tzpc5" }, 143 { 309, "tzpc6" }, 144 { 310, "tzpc7" }, 145 { 311, "tzpc8" }, 146 { 312, "tzpc9" }, 147 { 313, "hdmi_cec" }, 148 { 314, "seckey" }, 149 { 315, "mct" }, 150 { 316, "wdt" }, 151 { 317, "rtc" }, 152 { 318, "tmu" }, 153 { 319, "tmu_gpu" }, 154 { 330, "pclk66_gpio" }, 155 { 350, "aclk200_fsys2" }, 156 { 351, "mout_mmc0" }, 157 { 352, "mout_mmc1" }, 158 { 353, "mout_mmc2" }, 159 { 354, "sromc" }, 160 { 355, "ufs" }, 161 { 360, "aclk200_fsys" }, 162 { 361, "tsi" }, 163 { 362, "pdma0" }, 164 { 363, "pdma1" }, 165 { 364, "rtic" }, 166 { 365, "usbh20" }, 167 { 366, "usbd300" }, 168 { 367, "usbd301" }, 169 { 380, "aclk400_mscl" }, 170 { 381, "mscl0" }, 171 { 382, "mscl1" }, 172 { 383, "mscl2" }, 173 { 384, "smmu_mscl0" }, 174 { 385, "smmu_mscl1" }, 175 { 386, "smmu_mscl2" }, 176 { 400, "aclk333" }, 177 { 401, "mfc" }, 178 { 402, "smmu_mfcl" }, 179 { 403, "smmu_mfcr" }, 180 { 410, "aclk200_disp1" }, 181 { 411, "dsim1" }, 182 { 412, "dp1" }, 183 { 413, "hdmi" }, 184 { 420, "aclk300_disp1" }, 185 { 421, "fimd1" }, 186 { 422, "smmu_fimd1m0" }, 187 { 423, "smmu_fimd1m1" }, 188 { 430, "aclk166" }, 189 { 431, "mixer" }, 190 { 440, "aclk266" }, 191 { 441, "rotator" }, 192 { 442, "mdma1" }, 193 { 443, "smmu_rotator" }, 194 { 444, "smmu_mdma1" }, 195 { 450, "aclk300_jpeg" }, 196 { 451, "jpeg" }, 197 { 452, "jpeg2" }, 198 { 453, "smmu_jpeg" }, 199 { 454, "smmu_jpeg2" }, 200 { 460, "aclk300_gscl" }, 201 { 461, "smmu_gscl0" }, 202 { 462, "smmu_gscl1" }, 203 { 463, "gscl_wa" }, 204 { 464, "gscl_wb" }, 205 { 465, "gscl0" }, 206 { 466, "gscl1" }, 207 { 467, "fimc_3aa" }, 208 { 470, "aclk266_g2d" }, 209 { 471, "sss" }, 210 { 472, "slim_sss" }, 211 { 473, "mdma0" }, 212 { 480, "aclk333_g2d" }, 213 { 481, "g2d" }, 214 { 490, "aclk333_432_gscl" }, 215 { 491, "smmu_3aa" }, 216 { 492, "smmu_fimcl0" }, 217 { 493, "smmu_fimcl1" }, 218 { 494, "smmu_fimcl3" }, 219 { 495, "fimc_lite3" }, 220 { 496, "fimc_lite0" }, 221 { 497, "fimc_lite1" }, 222 { 500, "aclk_g3d" }, 223 { 501, "g3d" }, 224 { 502, "smmu_mixer" }, 225 { 503, "smmu_g2d" }, 226 { 504, "smmu_mdma0" }, 227 { 505, "mc" }, 228 { 506, "top_rtc" }, 229 { 510, "sclk_uart_isp" }, 230 { 511, "sclk_spi0_isp" }, 231 { 512, "sclk_spi1_isp" }, 232 { 513, "sclk_pwm_isp" }, 233 { 514, "sclk_isp_sensor0" }, 234 { 515, "sclk_isp_sensor1" }, 235 { 516, "sclk_isp_sensor2" }, 236 { 517, "aclk432_scaler" }, 237 { 518, "aclk432_cam" }, 238 { 519, "aclk_fl1550_cam" }, 239 { 520, "aclk550_cam" }, 240 { 640, "mout_hdmi" }, 241 { 641, "mout_g3d" }, 242 { 642, "mout_vpll" }, 243 { 643, "mout_maudio0" }, 244 { 644, "mout_user_aclk333" }, 245 { 645, "mout_sw_aclk333" }, 246 { 646, "mout_user_aclk200_disp1" }, 247 { 647, "mout_sw_aclk200" }, 248 { 648, "mout_user_aclk300_disp1" }, 249 { 649, "mout_sw_aclk300" }, 250 { 650, "mout_user_aclk400_disp1" }, 251 { 651, "mout_sw_aclk400" }, 252 { 768, "dout_pixel" }, 253 }; 254 255 static struct clk *exynos5422_clock_get(void *, const char *); 256 static void exynos5422_clock_put(void *, struct clk *); 257 static u_int exynos5422_clock_get_rate(void *, struct clk *); 258 static int exynos5422_clock_set_rate(void *, struct clk *, u_int); 259 static int exynos5422_clock_enable(void *, struct clk *); 260 static int exynos5422_clock_disable(void *, struct clk *); 261 static int exynos5422_clock_set_parent(void *, struct clk *, struct clk *); 262 static struct clk *exynos5422_clock_get_parent(void *, struct clk *); 263 264 static const struct clk_funcs exynos5422_clock_funcs = { 265 .get = exynos5422_clock_get, 266 .put = exynos5422_clock_put, 267 .get_rate = exynos5422_clock_get_rate, 268 .set_rate = exynos5422_clock_set_rate, 269 .enable = exynos5422_clock_enable, 270 .disable = exynos5422_clock_disable, 271 .set_parent = exynos5422_clock_set_parent, 272 .get_parent = exynos5422_clock_get_parent, 273 }; 274 275 #define CLK_FIXED(_name, _rate) { \ 276 .base = { .name = (_name) }, .type = EXYNOS_CLK_FIXED, \ 277 .u = { .fixed = { .rate = (_rate) } } \ 278 } 279 280 #define CLK_PLL35XX(_name, _parent, _lock, _con0) { \ 281 .base = { .name = (_name) }, \ 282 .type = EXYNOS_CLK_PLL35XX, \ 283 .parent = (_parent), \ 284 .u = { \ 285 .pll = { \ 286 .lock_reg = (_lock), \ 287 .con0_reg = (_con0), \ 288 } \ 289 } \ 290 } 291 292 #define CLK_MUXF(_name, _alias, _reg, _bits, _f, _p) { \ 293 .base = { .name = (_name), .flags = (_f) }, \ 294 .type = EXYNOS_CLK_MUX, \ 295 .alias = (_alias), \ 296 .u = { \ 297 .mux = { \ 298 .nparents = __arraycount(_p), \ 299 .parents = (_p), \ 300 .reg = (_reg), \ 301 .bits = (_bits) \ 302 } \ 303 } \ 304 } 305 306 #define CLK_MUXA(_name, _alias, _reg, _bits, _p) \ 307 CLK_MUXF(_name, _alias, _reg, _bits, 0, _p) 308 309 #define CLK_MUX(_name, _reg, _bits, _p) \ 310 CLK_MUXF(_name, NULL, _reg, _bits, 0, _p) 311 312 #define CLK_DIV(_name, _parent, _reg, _bits) { \ 313 .base = { .name = (_name) }, .type = EXYNOS_CLK_DIV, \ 314 .parent = (_parent), \ 315 .u = { \ 316 .div = { \ 317 .reg = (_reg), \ 318 .bits = (_bits) \ 319 } \ 320 } \ 321 } 322 323 #define CLK_GATE(_name, _parent, _reg, _bits, _f) { \ 324 .base = { .name = (_name), .flags = (_f) }, \ 325 .type = EXYNOS_CLK_GATE, \ 326 .parent = (_parent), \ 327 .u = { \ 328 .gate = { \ 329 .reg = (_reg), \ 330 .bits = (_bits) \ 331 } \ 332 } \ 333 } 334 335 #define EXYNOS5422_APLL_LOCK 0x00000 336 #define EXYNOS5422_APLL_CON0 0x00100 337 #define EXYNOS5422_CPLL_LOCK 0x10020 338 #define EXYNOS5422_DPLL_LOCK 0x10030 339 #define EXYNOS5422_EPLL_LOCK 0x10040 340 #define EXYNOS5422_RPLL_LOCK 0x10050 341 #define EXYNOS5422_IPLL_LOCK 0x10060 342 #define EXYNOS5422_SPLL_LOCK 0x10070 343 #define EXYNOS5422_VPLL_LOCK 0x10080 344 #define EXYNOS5422_MPLL_LOCK 0x10090 345 #define EXYNOS5422_CPLL_CON0 0x10120 346 #define EXYNOS5422_DPLL_CON0 0x10128 347 #define EXYNOS5422_EPLL_CON0 0x10130 348 #define EXYNOS5422_EPLL_CON1 0x10134 349 #define EXYNOS5422_EPLL_CON2 0x10138 350 #define EXYNOS5422_RPLL_CON0 0x10140 351 #define EXYNOS5422_RPLL_CON1 0x10144 352 #define EXYNOS5422_RPLL_CON2 0x10148 353 #define EXYNOS5422_IPLL_CON0 0x10150 354 #define EXYNOS5422_SPLL_CON0 0x10160 355 #define EXYNOS5422_VPLL_CON0 0x10170 356 #define EXYNOS5422_MPLL_CON0 0x10180 357 #define EXYNOS5422_BPLL_LOCK 0x20010 358 #define EXYNOS5422_BPLL_CON0 0x20110 359 #define EXYNOS5422_KPLL_LOCK 0x28000 360 #define EXYNOS5422_KPLL_CON0 0x28100 361 362 #define EXYNOS5422_SRC_CPU 0x00200 363 #define EXYNOS5422_SRC_TOP0 0x10200 364 #define EXYNOS5422_SRC_TOP1 0x10204 365 #define EXYNOS5422_SRC_TOP2 0x10208 366 #define EXYNOS5422_SRC_TOP3 0x1020c 367 #define EXYNOS5422_SRC_TOP4 0x10210 368 #define EXYNOS5422_SRC_TOP5 0x10214 369 #define EXYNOS5422_SRC_TOP6 0x10218 370 #define EXYNOS5422_SRC_TOP7 0x1021c 371 #define EXYNOS5422_SRC_DISP10 0x1022c 372 #define EXYNOS5422_SRC_MAU 0x10240 373 #define EXYNOS5422_SRC_FSYS 0x10244 374 #define EXYNOS5422_SRC_PERIC0 0x10250 375 #define EXYNOS5422_SRC_PERIC1 0x10254 376 #define EXYNOS5422_SRC_ISP 0x10270 377 #define EXYNOS5422_SRC_TOP10 0x10280 378 #define EXYNOS5422_SRC_TOP11 0x10284 379 #define EXYNOS5422_SRC_TOP12 0x10288 380 381 #define EXYNOS5422_DIV_TOP0 0x10500 382 #define EXYNOS5422_DIV_TOP1 0x10504 383 #define EXYNOS5422_DIV_FSYS0 0x10548 384 #define EXYNOS5422_DIV_FSYS1 0x1054c 385 #define EXYNOS5422_DIV_PERIC0 0x10558 386 387 #define EXYNOS5422_GATE_BUS_FSYS0 0x10740 388 #define EXYNOS5422_GATE_TOP_SCLK_FSYS 0x10840 389 #define EXYNOS5422_GATE_TOP_SCLK_PERIC 0x10850 390 #define EXYNOS5422_GATE_IP_FSYS 0x10944 391 #define EXYNOS5422_GATE_IP_PERIC 0x10950 392 393 static const char *mout_cpll_p[] = { "fin_pll", "fout_cpll" }; 394 static const char *mout_dpll_p[] = { "fin_pll", "fout_dpll" }; 395 static const char *mout_mpll_p[] = { "fin_pll", "fout_mpll" }; 396 static const char *mout_spll_p[] = { "fin_pll", "fout_spll" }; 397 static const char *mout_ipll_p[] = { "fin_pll", "fout_ipll" }; 398 static const char *mout_epll_p[] = { "fin_pll", "fout_epll" }; 399 static const char *mout_rpll_p[] = { "fin_pll", "fout_rpll" }; 400 static const char *mout_group1_p[] = 401 { "sclk_cpll", "sclk_dpll", "sclk_mpp" }; 402 static const char *mout_group2_p[] = 403 { "fin_pll", "sclk_cpll", "sclk_dpll", "sclk_mpll", 404 "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" }; 405 static const char *mout_user_aclk200_fsys_p[] = 406 { "fin_pll", "mout_sw_aclk200_fsys" }; 407 static const char *mout_user_aclk200_fsys2_p[] = 408 { "fin_pll", "mout_sw_aclk200_fsys2" }; 409 static const char *mout_user_aclk66_peric_p[] = 410 { "fin_pll", "mout_sw_aclk66" }; 411 static const char *mout_sw_aclk66_p[] = 412 { "dout_aclk66", "sclk_spll" }; 413 static const char *mout_sw_aclk200_fsys_p[] = 414 { "dout_aclk200_fsys", "sclk_spll" }; 415 static const char *mout_sw_aclk200_fsys2_p[] = 416 { "dout_aclk200_fsys2", "sclk_spll" }; 417 418 static struct exynos_clk exynos5422_clocks[] = { 419 CLK_FIXED("fin_pll", EXYNOS_F_IN_FREQ), 420 421 CLK_PLL35XX("fout_apll", "fin_pll", EXYNOS5422_APLL_LOCK, 422 EXYNOS5422_APLL_CON0), 423 CLK_PLL35XX("fout_cpll", "fin_pll", EXYNOS5422_CPLL_LOCK, 424 EXYNOS5422_CPLL_CON0), 425 CLK_PLL35XX("fout_dpll", "fin_pll", EXYNOS5422_DPLL_LOCK, 426 EXYNOS5422_DPLL_CON0), 427 CLK_PLL35XX("fout_epll", "fin_pll", EXYNOS5422_EPLL_LOCK, 428 EXYNOS5422_EPLL_CON0), 429 CLK_PLL35XX("fout_rpll", "fin_pll", EXYNOS5422_RPLL_LOCK, 430 EXYNOS5422_RPLL_CON0), 431 CLK_PLL35XX("fout_ipll", "fin_pll", EXYNOS5422_IPLL_LOCK, 432 EXYNOS5422_IPLL_CON0), 433 CLK_PLL35XX("fout_spll", "fin_pll", EXYNOS5422_SPLL_LOCK, 434 EXYNOS5422_SPLL_CON0), 435 CLK_PLL35XX("fout_vpll", "fin_pll", EXYNOS5422_VPLL_LOCK, 436 EXYNOS5422_VPLL_CON0), 437 CLK_PLL35XX("fout_mpll", "fin_pll", EXYNOS5422_MPLL_LOCK, 438 EXYNOS5422_MPLL_CON0), 439 CLK_PLL35XX("fout_bpll", "fin_pll", EXYNOS5422_BPLL_LOCK, 440 EXYNOS5422_BPLL_CON0), 441 CLK_PLL35XX("fout_kpll", "fin_pll", EXYNOS5422_KPLL_LOCK, 442 EXYNOS5422_KPLL_CON0), 443 444 CLK_MUXA("sclk_cpll", "mout_cpll", EXYNOS5422_SRC_TOP6, __BIT(28), 445 mout_cpll_p), 446 CLK_MUXA("sclk_dpll", "mout_dpll", EXYNOS5422_SRC_TOP6, __BIT(24), 447 mout_dpll_p), 448 CLK_MUXA("sclk_mpll", "mout_mpll", EXYNOS5422_SRC_TOP6, __BIT(0), 449 mout_mpll_p), 450 CLK_MUXA("sclk_spll", "mout_spll", EXYNOS5422_SRC_TOP6, __BIT(8), 451 mout_spll_p), 452 CLK_MUXA("sclk_ipll", "mout_ipll", EXYNOS5422_SRC_TOP6, __BIT(12), 453 mout_ipll_p), 454 CLK_MUXF("sclk_epll", "mout_epll", EXYNOS5422_SRC_TOP6, __BIT(20), 455 CLK_SET_RATE_PARENT, mout_epll_p), 456 CLK_MUXF("sclk_rpll", "mout_rpll", EXYNOS5422_SRC_TOP6, __BIT(16), 457 CLK_SET_RATE_PARENT, mout_rpll_p), 458 459 CLK_MUX("mout_sw_aclk200_fsys", EXYNOS5422_SRC_TOP10, __BIT(24), 460 mout_sw_aclk200_fsys_p), 461 CLK_MUX("mout_sw_aclk200_fsys2", EXYNOS5422_SRC_TOP10, __BIT(12), 462 mout_sw_aclk200_fsys2_p), 463 CLK_MUX("mout_user_aclk200_fsys", EXYNOS5422_SRC_TOP3, __BIT(28), 464 mout_user_aclk200_fsys_p), 465 CLK_MUX("mout_user_aclk200_fsys2", EXYNOS5422_SRC_TOP3, __BIT(12), 466 mout_user_aclk200_fsys2_p), 467 CLK_MUX("mout_aclk66", EXYNOS5422_SRC_TOP1, __BITS(9,8), 468 mout_group1_p), 469 CLK_MUX("mout_aclk200_fsys", EXYNOS5422_SRC_TOP0, __BITS(25,24), 470 mout_group1_p), 471 CLK_MUX("mout_aclk200_fsys2", EXYNOS5422_SRC_TOP0, __BITS(13,12), 472 mout_group1_p), 473 474 CLK_MUX("mout_sw_aclk66", EXYNOS5422_SRC_TOP11, __BIT(8), 475 mout_sw_aclk66_p), 476 CLK_MUX("mout_user_aclk66_peric", EXYNOS5422_SRC_TOP4, __BIT(8), 477 mout_user_aclk66_peric_p), 478 479 CLK_MUX("mout_usbd301", EXYNOS5422_SRC_FSYS, __BITS(6,4), 480 mout_group2_p), 481 CLK_MUX("mout_usbd300", EXYNOS5422_SRC_FSYS, __BITS(22,20), 482 mout_group2_p), 483 CLK_MUX("mout_mmc0", EXYNOS5422_SRC_FSYS, __BITS(10,8), 484 mout_group2_p), 485 CLK_MUX("mout_mmc1", EXYNOS5422_SRC_FSYS, __BITS(14,12), 486 mout_group2_p), 487 CLK_MUX("mout_mmc2", EXYNOS5422_SRC_FSYS, __BITS(18,16), 488 mout_group2_p), 489 CLK_MUX("mout_uart0", EXYNOS5422_SRC_PERIC0, __BITS(6,4), 490 mout_group2_p), 491 CLK_MUX("mout_uart1", EXYNOS5422_SRC_PERIC0, __BITS(10,8), 492 mout_group2_p), 493 CLK_MUX("mout_uart2", EXYNOS5422_SRC_PERIC0, __BITS(14,12), 494 mout_group2_p), 495 CLK_MUX("mout_uart3", EXYNOS5422_SRC_PERIC0, __BITS(18,16), 496 mout_group2_p), 497 498 CLK_DIV("dout_aclk66", "mout_aclk66", EXYNOS5422_DIV_TOP1, __BITS(13,8)), 499 CLK_DIV("dout_aclk200_fsys", "mout_aclk200_fsys", EXYNOS5422_DIV_TOP0, __BITS(30,28)), 500 CLK_DIV("dout_aclk200_fsys2", "mout_aclk200_fsys2", EXYNOS5422_DIV_TOP0, __BITS(14,12)), 501 502 CLK_DIV("dout_usbphy301", "mout_usbd301", EXYNOS5422_DIV_FSYS0, __BITS(15,12)), 503 CLK_DIV("dout_usbphy300", "mout_usbd300", EXYNOS5422_DIV_FSYS0, __BITS(19,16)), 504 CLK_DIV("dout_usbd301", "mout_usbd301", EXYNOS5422_DIV_FSYS0, __BITS(23,20)), 505 CLK_DIV("dout_usbd300", "mout_usbd300", EXYNOS5422_DIV_FSYS0, __BITS(27,24)), 506 CLK_DIV("dout_mmc0", "mout_mmc0", EXYNOS5422_DIV_FSYS1, __BITS(9,0)), 507 CLK_DIV("dout_mmc1", "mout_mmc1", EXYNOS5422_DIV_FSYS1, __BITS(19,10)), 508 CLK_DIV("dout_mmc2", "mout_mmc2", EXYNOS5422_DIV_FSYS1, __BITS(29,20)), 509 CLK_DIV("dout_uart0", "mout_uart0", EXYNOS5422_DIV_PERIC0, 510 __BITS(11,8)), 511 CLK_DIV("dout_uart1", "mout_uart1", EXYNOS5422_DIV_PERIC0, 512 __BITS(15,12)), 513 CLK_DIV("dout_uart2", "mout_uart2", EXYNOS5422_DIV_PERIC0, 514 __BITS(19,16)), 515 CLK_DIV("dout_uart3", "mout_uart3", EXYNOS5422_DIV_PERIC0, 516 __BITS(23,20)), 517 518 CLK_GATE("aclk200_fsys", "mout_user_aclk200_fsys", EXYNOS5422_GATE_BUS_FSYS0, 519 __BIT(9), CLK_SET_RATE_PARENT), 520 CLK_GATE("aclk200_fsys2", "mout_user_aclk200_fsys2", EXYNOS5422_GATE_BUS_FSYS0, 521 __BIT(10), CLK_SET_RATE_PARENT), 522 523 CLK_GATE("sclk_mmc0", "dout_mmc0", EXYNOS5422_GATE_TOP_SCLK_FSYS, 524 __BIT(0), CLK_SET_RATE_PARENT), 525 CLK_GATE("sclk_mmc1", "dout_mmc1", EXYNOS5422_GATE_TOP_SCLK_FSYS, 526 __BIT(1), CLK_SET_RATE_PARENT), 527 CLK_GATE("sclk_mmc2", "dout_mmc2", EXYNOS5422_GATE_TOP_SCLK_FSYS, 528 __BIT(2), CLK_SET_RATE_PARENT), 529 CLK_GATE("sclk_usbphy301", "dout_usbphy301", EXYNOS5422_GATE_TOP_SCLK_FSYS, 530 __BIT(7), CLK_SET_RATE_PARENT), 531 CLK_GATE("sclk_usbphy300", "dout_usbphy300", EXYNOS5422_GATE_TOP_SCLK_FSYS, 532 __BIT(8), CLK_SET_RATE_PARENT), 533 CLK_GATE("sclk_usbd300", "dout_usbd300", EXYNOS5422_GATE_TOP_SCLK_FSYS, 534 __BIT(9), CLK_SET_RATE_PARENT), 535 CLK_GATE("sclk_usbd301", "dout_usbd301", EXYNOS5422_GATE_TOP_SCLK_FSYS, 536 __BIT(10), CLK_SET_RATE_PARENT), 537 CLK_GATE("sclk_uart0", "dout_uart0", EXYNOS5422_GATE_TOP_SCLK_PERIC, 538 __BIT(0), CLK_SET_RATE_PARENT), 539 CLK_GATE("sclk_uart1", "dout_uart1", EXYNOS5422_GATE_TOP_SCLK_PERIC, 540 __BIT(1), CLK_SET_RATE_PARENT), 541 CLK_GATE("sclk_uart2", "dout_uart2", EXYNOS5422_GATE_TOP_SCLK_PERIC, 542 __BIT(2), CLK_SET_RATE_PARENT), 543 CLK_GATE("sclk_uart3", "dout_uart3", EXYNOS5422_GATE_TOP_SCLK_PERIC, 544 __BIT(3), CLK_SET_RATE_PARENT), 545 546 CLK_GATE("mmc0", "aclk200_fsys2", EXYNOS5422_GATE_IP_FSYS, 547 __BIT(12), CLK_SET_RATE_PARENT), 548 CLK_GATE("mmc1", "aclk200_fsys2", EXYNOS5422_GATE_IP_FSYS, 549 __BIT(13), CLK_SET_RATE_PARENT), 550 CLK_GATE("mmc2", "aclk200_fsys2", EXYNOS5422_GATE_IP_FSYS, 551 __BIT(14), CLK_SET_RATE_PARENT), 552 CLK_GATE("usbh20", "aclk200_fsys", EXYNOS5422_GATE_IP_FSYS, 553 __BIT(18), CLK_SET_RATE_PARENT), 554 CLK_GATE("usbd300", "aclk200_fsys", EXYNOS5422_GATE_IP_FSYS, 555 __BIT(19), CLK_SET_RATE_PARENT), 556 CLK_GATE("usbd301", "aclk200_fsys", EXYNOS5422_GATE_IP_FSYS, 557 __BIT(20), CLK_SET_RATE_PARENT), 558 559 CLK_GATE("uart0", "mout_user_aclk66_peric", EXYNOS5422_GATE_IP_PERIC, 560 __BIT(0), CLK_SET_RATE_PARENT), 561 CLK_GATE("uart1", "mout_user_aclk66_peric", EXYNOS5422_GATE_IP_PERIC, 562 __BIT(1), CLK_SET_RATE_PARENT), 563 CLK_GATE("uart2", "mout_user_aclk66_peric", EXYNOS5422_GATE_IP_PERIC, 564 __BIT(2), CLK_SET_RATE_PARENT), 565 CLK_GATE("uart3", "mout_user_aclk66_peric", EXYNOS5422_GATE_IP_PERIC, 566 __BIT(3), CLK_SET_RATE_PARENT), 567 CLK_GATE("i2c0", "mout_user_aclk66_peric", EXYNOS5422_GATE_IP_PERIC, 568 __BIT(6), CLK_SET_RATE_PARENT), 569 CLK_GATE("i2c1", "mout_user_aclk66_peric", EXYNOS5422_GATE_IP_PERIC, 570 __BIT(7), CLK_SET_RATE_PARENT), 571 CLK_GATE("i2c2", "mout_user_aclk66_peric", EXYNOS5422_GATE_IP_PERIC, 572 __BIT(8), CLK_SET_RATE_PARENT), 573 CLK_GATE("i2c3", "mout_user_aclk66_peric", EXYNOS5422_GATE_IP_PERIC, 574 __BIT(9), CLK_SET_RATE_PARENT), 575 CLK_GATE("i2c_hdmi", "mout_user_aclk66_peric", EXYNOS5422_GATE_IP_PERIC, 576 __BIT(14), CLK_SET_RATE_PARENT), 577 CLK_GATE("pwm", "mout_user_aclk66_peric", EXYNOS5422_GATE_IP_PERIC, 578 __BIT(24), CLK_SET_RATE_PARENT), 579 }; 580 581 static int exynos5422_clock_match(device_t, cfdata_t, void *); 582 static void exynos5422_clock_attach(device_t, device_t, void *); 583 584 struct exynos5422_clock_softc { 585 device_t sc_dev; 586 bus_space_tag_t sc_bst; 587 bus_space_handle_t sc_bsh; 588 589 struct clk_domain sc_clkdom; 590 }; 591 592 static void exynos5422_clock_print_header(void); 593 static void exynos5422_clock_print(struct exynos5422_clock_softc *, 594 struct exynos_clk *); 595 596 CFATTACH_DECL_NEW(exynos5422_clock, sizeof(struct exynos5422_clock_softc), 597 exynos5422_clock_match, exynos5422_clock_attach, NULL, NULL); 598 599 #define CLOCK_READ(sc, reg) \ 600 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 601 #define CLOCK_WRITE(sc, reg, val) \ 602 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 603 604 static const struct device_compatible_entry compat_data[] = { 605 { .compat = "samsung,exynos5800-clock" }, 606 DEVICE_COMPAT_EOL 607 }; 608 609 static int 610 exynos5422_clock_match(device_t parent, cfdata_t cf, void *aux) 611 { 612 struct fdt_attach_args * const faa = aux; 613 614 return of_compatible_match(faa->faa_phandle, compat_data); 615 } 616 617 static void 618 exynos5422_clock_attach(device_t parent, device_t self, void *aux) 619 { 620 struct exynos5422_clock_softc * const sc = device_private(self); 621 struct fdt_attach_args * const faa = aux; 622 bus_addr_t addr; 623 bus_size_t size; 624 int error; 625 626 if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) { 627 aprint_error(": couldn't get registers\n"); 628 return; 629 } 630 631 sc->sc_dev = self; 632 sc->sc_bst = faa->faa_bst; 633 634 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 635 if (error) { 636 aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", 637 addr, error); 638 return; 639 } 640 641 aprint_naive("\n"); 642 aprint_normal(": Exynos5422 Clock Controller\n"); 643 644 sc->sc_clkdom.funcs = &exynos5422_clock_funcs; 645 sc->sc_clkdom.priv = sc; 646 for (u_int n = 0; n < __arraycount(exynos5422_clocks); n++) { 647 exynos5422_clocks[n].base.domain = &sc->sc_clkdom; 648 } 649 650 fdtbus_register_clock_controller(self, faa->faa_phandle, 651 &exynos5422_car_fdtclock_funcs); 652 653 exynos5422_clock_print_header(); 654 for (u_int n = 0; n < __arraycount(exynos5422_clocks); n++) { 655 exynos5422_clock_print(sc, &exynos5422_clocks[n]); 656 } 657 } 658 659 static struct exynos_clk * 660 exynos5422_clock_find(const char *name) 661 { 662 u_int n; 663 664 for (n = 0; n < __arraycount(exynos5422_clocks); n++) { 665 if (strcmp(exynos5422_clocks[n].base.name, name) == 0) { 666 return &exynos5422_clocks[n]; 667 } 668 } 669 670 return NULL; 671 } 672 673 static struct exynos_clk * 674 exynos5422_clock_find_by_id(u_int clock_id) 675 { 676 u_int n; 677 678 for (n = 0; n < __arraycount(exynos5422_clock_ids); n++) { 679 if (exynos5422_clock_ids[n].id == clock_id) { 680 const char *name = exynos5422_clock_ids[n].name; 681 return exynos5422_clock_find(name); 682 } 683 } 684 685 return NULL; 686 } 687 688 static void 689 exynos5422_clock_print_header(void) 690 { 691 aprint_debug(" %-10s %2s %-10s %-5s %10s\n", 692 "clock", "", "parent", "type", "rate"); 693 aprint_debug(" %-10s %2s %-10s %-5s %10s\n", 694 "=====", "", "======", "====", "===="); 695 } 696 697 static void 698 exynos5422_clock_print(struct exynos5422_clock_softc *sc, 699 struct exynos_clk *eclk) 700 { 701 struct exynos_clk *eclk_parent; 702 struct clk *clk_parent; 703 const char *type = "?"; 704 705 switch (eclk->type) { 706 case EXYNOS_CLK_FIXED: 707 type = "fixed"; 708 break; 709 case EXYNOS_CLK_PLL35XX: 710 case EXYNOS_CLK_PLL2650X: 711 type = "pll"; 712 break; 713 case EXYNOS_CLK_MUX: 714 type = "mux"; 715 break; 716 case EXYNOS_CLK_DIV: 717 type = "div"; 718 break; 719 case EXYNOS_CLK_GATE: 720 type = "gate"; 721 break; 722 } 723 724 clk_parent = exynos5422_clock_get_parent(sc, &eclk->base); 725 eclk_parent = (struct exynos_clk *)clk_parent; 726 727 aprint_debug(" %-10s %2s %-10s %-5s %10d Hz\n", 728 eclk->base.name, 729 eclk_parent ? "<-" : "", 730 eclk_parent ? eclk_parent->base.name : "", 731 type, clk_get_rate(&eclk->base)); 732 } 733 734 static struct clk * 735 exynos5422_clock_decode(device_t dev, int cc_phandle, const void *data, 736 size_t len) 737 { 738 struct exynos_clk *eclk; 739 740 /* #clock-cells should be 1 */ 741 if (len != 4) { 742 return NULL; 743 } 744 745 const u_int clock_id = be32dec(data); 746 747 eclk = exynos5422_clock_find_by_id(clock_id); 748 if (eclk) 749 return &eclk->base; 750 751 return NULL; 752 } 753 754 static u_int 755 exynos5422_clock_get_rate_pll(struct exynos5422_clock_softc *sc, 756 struct exynos_clk *eclk) 757 { 758 struct exynos_pll_clk *epll = &eclk->u.pll; 759 struct exynos_clk *clk_parent; 760 761 KASSERT(eclk->type == EXYNOS_CLK_PLL35XX); 762 763 clk_parent = exynos5422_clock_find(eclk->parent); 764 KASSERT(clk_parent != NULL); 765 const u_int rate_parent = exynos5422_clock_get_rate(sc, 766 &clk_parent->base); 767 768 const uint32_t v = CLOCK_READ(sc, epll->con0_reg); 769 770 return PLL35XX_FREQ(rate_parent, v); 771 } 772 773 static int 774 exynos5422_clock_set_rate_pll(struct exynos5422_clock_softc *sc, 775 struct exynos_clk *eclk, u_int rate) 776 { 777 /* TODO */ 778 return EOPNOTSUPP; 779 } 780 781 static int 782 exynos5422_clock_set_parent_mux(struct exynos5422_clock_softc *sc, 783 struct exynos_clk *eclk, struct exynos_clk *eclk_parent) 784 { 785 struct exynos_mux_clk *emux = &eclk->u.mux; 786 const char *pname = eclk_parent->base.name; 787 u_int sel; 788 789 KASSERT(eclk->type == EXYNOS_CLK_MUX); 790 791 for (sel = 0; sel < emux->nparents; sel++) { 792 if (strcmp(pname, emux->parents[sel]) == 0) { 793 break; 794 } 795 } 796 if (sel == emux->nparents) { 797 return EINVAL; 798 } 799 800 uint32_t v = CLOCK_READ(sc, emux->reg); 801 v &= ~emux->bits; 802 v |= __SHIFTIN(sel, emux->bits); 803 CLOCK_WRITE(sc, emux->reg, v); 804 805 return 0; 806 } 807 808 static struct exynos_clk * 809 exynos5422_clock_get_parent_mux(struct exynos5422_clock_softc *sc, 810 struct exynos_clk *eclk) 811 { 812 struct exynos_mux_clk *emux = &eclk->u.mux; 813 814 KASSERT(eclk->type == EXYNOS_CLK_MUX); 815 816 const uint32_t v = CLOCK_READ(sc, emux->reg); 817 const u_int sel = __SHIFTOUT(v, emux->bits); 818 819 KASSERT(sel < emux->nparents); 820 821 return exynos5422_clock_find(emux->parents[sel]); 822 } 823 824 static u_int 825 exynos5422_clock_get_rate_div(struct exynos5422_clock_softc *sc, 826 struct exynos_clk *eclk) 827 { 828 struct exynos_div_clk *ediv = &eclk->u.div; 829 struct clk *clk_parent; 830 831 KASSERT(eclk->type == EXYNOS_CLK_DIV); 832 833 clk_parent = exynos5422_clock_get_parent(sc, &eclk->base); 834 const u_int parent_rate = exynos5422_clock_get_rate(sc, clk_parent); 835 836 const uint32_t v = CLOCK_READ(sc, ediv->reg); 837 const u_int div = __SHIFTOUT(v, ediv->bits); 838 839 return parent_rate / (div + 1); 840 } 841 842 static int 843 exynos5422_clock_set_rate_div(struct exynos5422_clock_softc *sc, 844 struct exynos_clk *eclk, u_int rate) 845 { 846 struct exynos_div_clk *ediv = &eclk->u.div; 847 struct clk *clk_parent; 848 int tmp_div, new_div = -1; 849 u_int tmp_rate; 850 851 KASSERT(eclk->type == EXYNOS_CLK_DIV); 852 853 clk_parent = exynos5422_clock_get_parent(sc, &eclk->base); 854 const u_int parent_rate = exynos5422_clock_get_rate(sc, clk_parent); 855 856 for (tmp_div = 0; tmp_div < __SHIFTOUT_MASK(ediv->bits); tmp_div++) { 857 tmp_rate = parent_rate / (tmp_div + 1); 858 if (tmp_rate <= rate) { 859 new_div = tmp_div; 860 break; 861 } 862 } 863 if (new_div == -1) 864 return EINVAL; 865 866 uint32_t v = CLOCK_READ(sc, ediv->reg); 867 v &= ~ediv->bits; 868 v |= __SHIFTIN(new_div, ediv->bits); 869 CLOCK_WRITE(sc, ediv->reg, v); 870 871 return 0; 872 } 873 874 static int 875 exynos5422_clock_enable_gate(struct exynos5422_clock_softc *sc, 876 struct exynos_clk *eclk, bool enable) 877 { 878 struct exynos_gate_clk *egate = &eclk->u.gate; 879 880 KASSERT(eclk->type == EXYNOS_CLK_GATE); 881 882 uint32_t v = CLOCK_READ(sc, egate->reg); 883 if (enable) { 884 v |= egate->bits; 885 } else { 886 v &= ~egate->bits; 887 } 888 CLOCK_WRITE(sc, egate->reg, v); 889 890 return 0; 891 } 892 893 /* 894 * clk api 895 */ 896 897 static struct clk * 898 exynos5422_clock_get(void *priv, const char *name) 899 { 900 struct exynos_clk *eclk; 901 902 eclk = exynos5422_clock_find(name); 903 if (eclk == NULL) 904 return NULL; 905 906 atomic_inc_uint(&eclk->refcnt); 907 908 return &eclk->base; 909 } 910 911 static void 912 exynos5422_clock_put(void *priv, struct clk *clk) 913 { 914 struct exynos_clk *eclk = (struct exynos_clk *)clk; 915 916 KASSERT(eclk->refcnt > 0); 917 918 atomic_dec_uint(&eclk->refcnt); 919 } 920 921 static u_int 922 exynos5422_clock_get_rate(void *priv, struct clk *clk) 923 { 924 struct exynos_clk *eclk = (struct exynos_clk *)clk; 925 struct clk *clk_parent; 926 927 switch (eclk->type) { 928 case EXYNOS_CLK_FIXED: 929 return eclk->u.fixed.rate; 930 case EXYNOS_CLK_PLL35XX: 931 return exynos5422_clock_get_rate_pll(priv, eclk); 932 case EXYNOS_CLK_MUX: 933 case EXYNOS_CLK_GATE: 934 clk_parent = exynos5422_clock_get_parent(priv, clk); 935 return exynos5422_clock_get_rate(priv, clk_parent); 936 case EXYNOS_CLK_DIV: 937 return exynos5422_clock_get_rate_div(priv, eclk); 938 default: 939 panic("exynos5422: unknown eclk type %d", eclk->type); 940 } 941 } 942 943 static int 944 exynos5422_clock_set_rate(void *priv, struct clk *clk, u_int rate) 945 { 946 struct exynos_clk *eclk = (struct exynos_clk *)clk; 947 948 KASSERT((clk->flags & CLK_SET_RATE_PARENT) == 0); 949 950 switch (eclk->type) { 951 case EXYNOS_CLK_FIXED: 952 return EIO; 953 case EXYNOS_CLK_PLL35XX: 954 return exynos5422_clock_set_rate_pll(priv, eclk, rate); 955 case EXYNOS_CLK_MUX: 956 return EIO; 957 case EXYNOS_CLK_DIV: 958 return exynos5422_clock_set_rate_div(priv, eclk, rate); 959 case EXYNOS_CLK_GATE: 960 return EINVAL; 961 default: 962 panic("exynos5422: unknown eclk type %d", eclk->type); 963 } 964 } 965 966 static int 967 exynos5422_clock_enable(void *priv, struct clk *clk) 968 { 969 struct exynos_clk *eclk = (struct exynos_clk *)clk; 970 971 switch (eclk->type) { 972 case EXYNOS_CLK_FIXED: 973 return 0; /* always on */ 974 case EXYNOS_CLK_PLL35XX: 975 return 0; /* XXX */ 976 case EXYNOS_CLK_MUX: 977 case EXYNOS_CLK_DIV: 978 return 0; 979 case EXYNOS_CLK_GATE: 980 return exynos5422_clock_enable_gate(priv, eclk, true); 981 default: 982 panic("exynos5422: unknown eclk type %d", eclk->type); 983 } 984 } 985 986 static int 987 exynos5422_clock_disable(void *priv, struct clk *clk) 988 { 989 struct exynos_clk *eclk = (struct exynos_clk *)clk; 990 991 switch (eclk->type) { 992 case EXYNOS_CLK_FIXED: 993 return EINVAL; /* always on */ 994 case EXYNOS_CLK_PLL35XX: 995 return EINVAL; /* XXX */ 996 case EXYNOS_CLK_MUX: 997 case EXYNOS_CLK_DIV: 998 return EINVAL; 999 case EXYNOS_CLK_GATE: 1000 return exynos5422_clock_enable_gate(priv, eclk, false); 1001 default: 1002 panic("exynos5422: unknown eclk type %d", eclk->type); 1003 } 1004 } 1005 1006 static int 1007 exynos5422_clock_set_parent(void *priv, struct clk *clk, struct clk *clk_parent) 1008 { 1009 struct exynos_clk *eclk = (struct exynos_clk *)clk; 1010 struct exynos_clk *eclk_parent = (struct exynos_clk *)clk_parent; 1011 1012 switch (eclk->type) { 1013 case EXYNOS_CLK_FIXED: 1014 case EXYNOS_CLK_PLL35XX: 1015 case EXYNOS_CLK_DIV: 1016 case EXYNOS_CLK_GATE: 1017 return EINVAL; 1018 case EXYNOS_CLK_MUX: 1019 return exynos5422_clock_set_parent_mux(priv, eclk, eclk_parent); 1020 default: 1021 panic("exynos5422: unknown eclk type %d", eclk->type); 1022 } 1023 } 1024 1025 static struct clk * 1026 exynos5422_clock_get_parent(void *priv, struct clk *clk) 1027 { 1028 struct exynos_clk *eclk = (struct exynos_clk *)clk; 1029 struct exynos_clk *eclk_parent = NULL; 1030 1031 switch (eclk->type) { 1032 case EXYNOS_CLK_FIXED: 1033 case EXYNOS_CLK_PLL35XX: 1034 case EXYNOS_CLK_DIV: 1035 case EXYNOS_CLK_GATE: 1036 if (eclk->parent != NULL) { 1037 eclk_parent = exynos5422_clock_find(eclk->parent); 1038 } 1039 break; 1040 case EXYNOS_CLK_MUX: 1041 eclk_parent = exynos5422_clock_get_parent_mux(priv, eclk); 1042 break; 1043 default: 1044 panic("exynos5422: unknown eclk type %d", eclk->type); 1045 } 1046 1047 return (struct clk *)eclk_parent; 1048 } 1049
Indexes created Sun Oct 25 00:26:45 UTC 2026