| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
| amdgpu_process_pptables_v1_0.c | 422 phm_ppt_v1_clock_voltage_dependency_table *sclk_table; local in function:get_sclk_voltage_dependency_table
436 sclk_table = kzalloc(table_size, GFP_KERNEL);
438 if (NULL == sclk_table)
441 sclk_table->count = (uint32_t)tonga_table->ucNumEntries;
449 entries, sclk_table, i);
468 sclk_table = kzalloc(table_size, GFP_KERNEL);
470 if (NULL == sclk_table)
473 sclk_table->count = (uint32_t)polaris_table->ucNumEntries;
481 entries, sclk_table, i);
491 *pp_tonga_sclk_dep_table = sclk_table;
[all...] |
| amdgpu_smu8_hwmgr.c | 1523 struct phm_clock_voltage_dependency_table *sclk_table = local in function:smu8_print_clock_levels
1535 for (i = 0; i < sclk_table->count; i++)
1537 i, sclk_table->entries[i].clk / 100,
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| amdgpu_vega20_hwmgr.c | 1452 struct vega20_single_dpm_table *sclk_table = local in function:vega20_get_sclk_od
1456 int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
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| smu7_hwmgr.h | 106 struct smu7_single_dpm_table sclk_table; member in struct:smu7_dpm_table
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| amdgpu_vega10_hwmgr.c | 3329 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); local in function:vega10_find_dpm_states_clocks_in_dpm_table
3337 for (i = 0; i < sclk_table->count; i++) {
3338 if (sclk == sclk_table->dpm_levels[i].value)
3342 if (i >= sclk_table->count) {
3343 if (sclk > sclk_table->dpm_levels[i-1].value) {
3345 sclk_table->dpm_levels[i-1].value = sclk;
4537 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); local in function:vega10_print_clock_levels
4558 count = sclk_table->count;
4561 i, sclk_table->dpm_levels[i].value / 100,
4825 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table) local in function:vega10_get_sclk_od
[all...] |
| amdgpu_smu7_hwmgr.c | 642 &data->dpm_table.sclk_table,
700 data->dpm_table.sclk_table.count = 0;
703 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count-1].value !=
705 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
707 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = (i == 0) ? 1 : 0;
708 data->dpm_table.sclk_table.count++;
794 data->dpm_table.sclk_table.count = 0
1712 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = NULL; local in function:smu7_get_evv_voltages
1860 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = local in function:smu7_patch_voltage_dependency_tables_with_lookup_table
1941 phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk; local in function:smu7_calc_voltage_dependency_tables
3606 struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); local in function:smu7_find_dpm_states_clocks_in_dpm_table
4454 struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); local in function:smu7_print_clock_levels
4578 struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); local in function:smu7_get_sclk_od
4665 struct phm_clock_voltage_dependency_table *sclk_table; local in function:smu7_get_sclks
4786 struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); local in function:smu7_get_max_high_clocks
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/ |
| amdgpu_vegam_smumgr.c | 890 for (i = 0; i < dpm_table->sclk_table.count; i++) {
893 dpm_table->sclk_table.dpm_levels[i].value,
911 (uint8_t)dpm_table->sclk_table.count;
913 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
915 for (i = 0; i < dpm_table->sclk_table.count; i++)
924 for (i = 0; i < dpm_table->sclk_table.count; i++)
949 for (i = 2; i < dpm_table->sclk_table.count; i++)
1289 for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) {
1292 hw_data->dpm_table.sclk_table.dpm_levels[i].value,
1376 result = phm_find_boot_level(&(data->dpm_table.sclk_table),
1497 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = local in function:vegam_populate_clock_stretcher_data_table
1578 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = local in function:vegam_populate_avfs_parameters
[all...] |
| amdgpu_fiji_smumgr.c | 1029 for (i = 0; i < dpm_table->sclk_table.count; i++) {
1031 dpm_table->sclk_table.dpm_levels[i].value,
1045 levels[dpm_table->sclk_table.count - 1].DisplayWatermark =
1049 (uint8_t)dpm_table->sclk_table.count;
1051 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
1058 for (i = 0; i < dpm_table->sclk_table.count; i++)
1083 for (i = 2; i < dpm_table->sclk_table.count; i++)
1323 data->dpm_table.sclk_table.dpm_levels[0].value;
1539 for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
1542 data->dpm_table.sclk_table.dpm_levels[i].value
1678 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = local in function:fiji_populate_clock_stretcher_data_table
[all...] |
| amdgpu_polaris10_smumgr.c | 1006 for (i = 0; i < dpm_table->sclk_table.count; i++) {
1009 dpm_table->sclk_table.dpm_levels[i].value,
1024 (uint8_t)dpm_table->sclk_table.count;
1026 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
1034 for (i = 0; i < dpm_table->sclk_table.count; i++)
1059 for (i = 2; i < dpm_table->sclk_table.count; i++)
1375 for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) {
1378 hw_data->dpm_table.sclk_table.dpm_levels[i].value,
1464 result = phm_find_boot_level(&(data->dpm_table.sclk_table),
1524 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table local in function:polaris10_populate_clock_stretcher_data_table
1660 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = local in function:polaris10_populate_avfs_parameters
[all...] |
| amdgpu_tonga_smumgr.c | 715 for (i = 0; i < dpm_table->sclk_table.count; i++) {
717 dpm_table->sclk_table.dpm_levels[i].value,
731 if (dpm_table->sclk_table.count > 1)
732 smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark =
736 (uint8_t)dpm_table->sclk_table.count;
738 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
745 for (i = 0; i < dpm_table->sclk_table.count; i++) {
775 for (i = 2; i < dpm_table->sclk_table.count; i++)
1502 for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
1505 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value
1589 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = local in function:tonga_populate_clock_stretcher_data_table
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| ci_dpm.h | 71 struct ci_single_dpm_table sclk_table; member in struct:ci_dpm_table
|
| radeon_ci_dpm.c | 2561 for (i = 0; i < pi->dpm_table.sclk_table.count; i++) {
2564 pi->dpm_table.sclk_table.dpm_levels[i].value,
3295 for (i = 0; i < dpm_table->sclk_table.count; i++) {
3297 dpm_table->sclk_table.dpm_levels[i].value,
3304 if (i == (dpm_table->sclk_table.count - 1))
3310 pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;
3312 ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
3470 &pi->dpm_table.sclk_table,
3485 pi->dpm_table.sclk_table.count = 0;
3488 (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value !
3866 struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table; local in function:ci_find_dpm_states_clocks_in_dpm_table
[all...] |
