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  /src/tests/lib/libc/locale/
t_mbrtoc8.c 62 static char8_t c8; variable in typeref:typename:char8_t
72 ATF_CHECK_EQ_MSG((n = mbrtoc8(&c8, "", 1, NULL)), 0, "n=%zu", n);
73 ATF_CHECK_EQ_MSG(c8, 0, "c8=0x%"PRIx8, (uint8_t)c8);
77 ATF_CHECK_EQ_MSG((n = mbrtoc8(&c8, "", 1, &s)), 0, "n=%zu", n);
78 ATF_CHECK_EQ_MSG(c8, 0, "c8=0x%"PRIx8, (uint8_t)c8);
82 ATF_CHECK_EQ_MSG((n = mbrtoc8(&c8, "A", 1, NULL)), 1, "n=%zu", n)
    [all...]
  /src/sys/arch/arm/arm/
cpufunc_asm_arm10.S 42 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
43 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
46 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
47 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
53 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
56 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
75 mcr p15, 0, r0, c8, c7, 0 /* and flush the I+D tlbs */
cpufunc_asm_armv4.S 47 mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */
53 mcr p15, 0, r0, c8, c5, 0 /* flush I tlb */
59 mcr p15, 0, r0, c8, c6, 0 /* flush D tlb */
64 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
67 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
cpufunc_asm_arm11.S 54 mcrne p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
77 mcr p15, 0, r0, c8, c7, 0 /* and flush the I+D tlbs */
93 mcr p15, 0, r0, c8, c5, 0 /* flush I tlb */
103 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
106 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
116 mcr p15, 0, r0, c8, c6, 0 /* flush D tlb */
126 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
129 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
138 mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */
148 mcr p15, 0, r0, c8, c7, 1 /* flush I+D tlb single entry *
    [all...]
cpufunc_asm_arm7tdmi.S 83 mcr p15, 0, r0, c8, c7, 0
88 mcr p15, 0, r0, c8, c7, 1
91 mcr p15, 0, r0, c8, c7, 1
cpufunc_asm_sa11x0.S 91 mcr p15, 0, r0, c15, c8, 2 /* wait for interrupt
116 mcr p15, 0, r0, c8, c7, 0 /* flush the I+D tlb */
cpufunc_asm_ixp12x0.S 57 mcr p15, 0, r0, c8, c7, 0 /* flush the I+D tlb */
cpufunc_asm_arm9.S 55 mcrne p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
63 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
64 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
67 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
68 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
246 mcr p15, 0, r0, c8, c7, 0 /* and flush the I+D tlbs */
cpufunc_asm_sa1.S 75 mcrne p15, 0, r0, c8, c7, 0 /* invalidate I+D TLB */
95 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
96 mcr p15, 0, r0, c8, c5, 0 /* flush I tlb */
99 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
100 mcr p15, 0, r0, c8, c5, 0 /* flush I tlb */
328 mcr p15, 0, r0, c8, c7, 0 /* flush the I+D tlb */
cpufunc_asm_xscale.S 164 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLB */
187 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
188 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
191 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
192 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
509 mcr p15, 0, r0, c8, c7, 0 /* flush the I+D tlb */
cpufunc_asm_arm8.S 86 mcrne p15, 0, r0, c8, c7, 0
103 mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */
108 mcr p15, 0, r0, c8, c7, 1 /* flush I+D tlb single entry */
111 mcr p15, 0, r0, c8, c7, 1 /* flush I+D tlb single entry */
288 mcr p15, 0, r0, c8, c7, 0 /* flush the I+D tlb */
cpufunc_asm_armv7.S 59 mcr p15, 0, r0, c8, c7, 0 @ flush the I+D
68 mcr p15, 0, r0, c8, c7, 2 @ flush I+D tlb all ASID
76 mcr p15, 0, r0, c8, c3, 2 @ flush I+D tlb all ASID
88 mcr p15, 0, r0, c8, c7, 1 @ flush I+D tlb single entry
91 mcr p15, 0, r0, c8, c7, 1 @ flush I+D tlb single entry
103 mcr p15, 0, r0, c8, c3, 1 @ flush I+D tlb single entry
106 mcr p15, 0, r0, c8, c3, 1 @ flush I+D tlb single entry
119 mcr p15, 0, r0, c8, c6, 0 @ flush entire D tlb
129 mcr p15, 0, r0, c8, c7, 0 @ flush entire I+D tlb
141 mcr p15, 0, r0, c8, c3, 0 @ flush entire I+D tlb, I
    [all...]
cpufunc_asm_armv6.S 59 mcrne p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
  /src/lib/libc/locale/
c8rtomb.c 30 * c8rtomb(s, c8, ps)
32 * Encode the Unicode UTF-8 code unit c8 into the multibyte buffer
35 * If c8 is not the last byte of a UTF-8 scalar value sequence, no
36 * output will be produced, but c8 will be remembered; this must
115 utf8_decode_step(utf8_state_t state, char8_t c8, char32_t *pc32)
117 const utf8_class_t class = utf8_classtab[c8];
120 ? (c8 & (0xff >> class))
121 : ((c8 & 0x3f) | (*pc32 << 6)));
131 c8rtomb(char *restrict s, char8_t c8, mbstate_t *restrict ps)
134 return c8rtomb_l(s, c8, ps, _current_locale())
    [all...]
  /src/sys/arch/evbarm/ixm1200/
ixm1200_start.S 91 mcr p15, 0, r0, c8, c7 ,0 /* flush D and I TLB */
107 mcr p15, 0, r0, c15, c8 ,0 /* IBCR = 0 (never watch) */
154 mcr p15, 0, r0, c8, c7 ,0 /* flush D and I TLB */
  /src/sys/external/isc/libsodium/dist/test/default/
pwhash_scrypt_ll.exp 4 fc d0 06 9d ed 09 48 f8 32 6a 75 3a 0f c8 1f 17
8 7c 6a d7 cb c8 23 78 30 e7 73 76 63 4b 37 31 62
  /src/sys/arch/evbarm/imx31/
imx31lk_start.S 100 mcr p15, 0, r0, c8, c7, 0
  /src/sys/arch/evbarm/iq80310/
iq80310_start.S 116 mcr p15, 0, r0, c8, c7, 0
  /src/sys/arch/netwinder/netwinder/
nwmmu.S 105 mcr p15, 0, r0, c8, c7, 0
  /src/sys/arch/zaurus/zaurus/
zaurus_start.S 81 mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */
  /src/sys/arch/evbarm/g42xxeb/
g42xxeb_start.S 124 mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */
  /src/sys/arch/evbarm/iq80321/
iq80321_start.S 125 mcr p15, 0, r0, c8, c7, 0
  /src/sys/arch/evbarm/lubbock/
lubbock_start.S 124 mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */
  /src/sys/arch/evbarm/marvell/
marvell_start.S 222 mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */
228 mcreq p15, 0, r0, c8, c7, 0 /* Flush TLB */
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
keystone-k2e-clocks.dtsi 65 clkxge: clkxge@23500c8 {

Completed in 42 milliseconds

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