1 /* $NetBSD: g42xxeb_start.S,v 1.3 2011/01/31 06:28:02 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2002, 2003 Genetec Corporation. All rights reserved. 5 * Written by Hiroyuki Bessho for Genetec Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of Genetec Corporation may not be used to endorse or 16 * promote products derived from this software without specific prior 17 * written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <machine/asm.h> 33 #include <arm/armreg.h> 34 #include "assym.h" 35 36 RCSID("$NetBSD: g42xxeb_start.S,v 1.3 2011/01/31 06:28:02 matt Exp $") 37 38 #ifndef SDRAM_START 39 #define SDRAM_START 0xa0000000 40 #endif 41 42 /* 43 * CPWAIT -- Canonical method to wait for CP15 update. 44 * NOTE: Clobbers the specified temp reg. 45 * copied from arm/arm/cpufunc_asm_xscale.S 46 * XXX: better be in a common header file. 47 */ 48 #define CPWAIT_BRANCH \ 49 sub pc, pc, #4 50 51 #define CPWAIT(tmp) \ 52 mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\ 53 mov tmp, tmp /* wait for it to complete */ ;\ 54 CPWAIT_BRANCH /* branch to next insn */ 55 56 /* 57 * Kernel start routine for G4255EB (TWINTAIL) 58 * this code is excuted at the very first after the kernel is loaded 59 * by RedBoot. 60 */ 61 .text 62 63 .global _C_LABEL(g42xxeb_start) 64 _C_LABEL(g42xxeb_start): 65 /* Are we running on ROM ? */ 66 cmp pc, #0x06000000 67 bhi g42xxeb_start_ram 68 69 /* move me to RAM 70 * XXX: we can use memcpy if it is PIC 71 */ 72 ldr r1, Lcopy_size 73 adr r0, _C_LABEL(g42xxeb_start) 74 add r1, r1, #3 75 mov r1, r1, LSR #2 76 mov r2, #SDRAM_START 77 add r2, r2, #0x00200000 78 mov r4, r2 79 80 5: ldr r3,[r0],#4 81 str r3,[r2],#4 82 subs r1,r1,#1 83 bhi 5b 84 85 /* Jump to RAM */ 86 ldr r0, Lstart_off 87 add pc, r4, r0 88 89 Lcopy_size: .word _edata-_C_LABEL(g42xxeb_start) 90 Lstart_off: .word g42xxeb_start_ram-_C_LABEL(g42xxeb_start) 91 92 g42xxeb_start_ram: 93 /* 94 * Kernel is loaded in SDRAM (0xa0200000..), and is expected to run 95 * in VA 0xc0200000.. 96 */ 97 98 mrc p15, 0, r0, c2, c0, 0 /* get ttb prepared by redboot */ 99 adr r4, mmu_init_table2 100 101 #ifdef BUILD_STARTUP_PAGETABLE 102 mrc p15, 0, r2, c1, c0, 0 103 tst r2, #CPU_CONTROL_MMU_ENABLE /* we already have a page table? */ 104 bne 3f 105 106 /* build page table from scratch */ 107 ldr r0, Lstartup_pagetable 108 adr r4, mmu_init_table 109 #endif 110 b 3f 111 112 2: 113 str r3, [r0, r2] 114 add r2, r2, #4 115 add r3, r3, #(L1_S_SIZE) 116 adds r1, r1, #-1 117 bhi 2b 118 3: 119 ldmia r4!, {r1,r2,r3} /* # of sections, PA|attr, VA */ 120 cmp r1, #0 121 bne 2b 122 123 mcr p15, 0, r0, c2, c0, 0 /* Set TTB */ 124 mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */ 125 126 /* Set the Domain Access register. Very important! */ 127 mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT) 128 mcr p15, 0, r0, c3, c0, 0 129 130 /* Enable MMU */ 131 mrc p15, 0, r0, c1, c0, 0 132 orr r0, r0, #CPU_CONTROL_MMU_ENABLE 133 mcr p15, 0, r0, c1, c0, 0 134 CPWAIT(r0) 135 136 /* Jump to kernel code in TRUE VA */ 137 adr r0, Lstart 138 ldr pc, [r0] 139 140 Lstart: 141 .word start 142 143 #define MMU_INIT(va,pa,n_sec,attr) \ 144 .word n_sec ; \ 145 .word 4*((va)>>L1_S_SHIFT) ; \ 146 .word (pa)|(attr) ; 147 148 #ifdef BUILD_STARTUP_PAGETABLE 149 #ifndef STARTUP_PAGETABLE_ADDR 150 #define STARTUP_PAGETABLE_ADDR 0xa0004000 151 #endif 152 Lstartup_pagetable .word STARTUP_PAGETABLE_ADDR 153 mmu_init_table: 154 /* fill all table VA==PA */ 155 MMU_INIT(0x00000000, 0x00000000, 1<<(32-L1_S_SHIFT), L1_TYPE_S|L1_S_AP_KRW) 156 /* map SDRAM VA==PA, WT cacheable */ 157 MMU_INIT(SDRAM_START, SDRAM_START, 64, L1_TYPE_S|L1_S_C|L1_S_AP_KRW) 158 #endif 159 mmu_init_table2: 160 /* map VA 0xc0000000..0xc3ffffff to PA 0xa0000000..0xa3ffffff */ 161 MMU_INIT(0xc0000000, SDRAM_START, 64, L1_TYPE_S|L1_S_C|L1_S_AP_KRW) 162 163 .word 0 /* end of table */ 164
Indexes created Sat Sep 20 22:09:52 GMT 2025