| /src/share/man/man4/man4.sgimips/ |
| Makefile | 4 imc.4 intro.4 light.4 mace.4 mavb.4 mec.4 newport.4 pic.4 sq.4 wdsc.4
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| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_gfx.c | 43 int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec,
48 bit += mec * adev->gfx.mec.num_pipe_per_mec
49 * adev->gfx.mec.num_queue_per_pipe;
50 bit += pipe * adev->gfx.mec.num_queue_per_pipe;
57 int *mec, int *pipe, int *queue)
59 *queue = bit % adev->gfx.mec.num_queue_per_pipe;
60 *pipe = (bit / adev->gfx.mec.num_queue_per_pipe)
61 % adev->gfx.mec.num_pipe_per_mec;
62 *mec = (bit / adev->gfx.mec.num_queue_per_pipe
202 int i, queue, pipe, mec; local in function:amdgpu_gfx_compute_queue_acquire
264 int mec, pipe, queue; local in function:amdgpu_gfx_kiq_acquire
[all...] |
| amdgpu_amdkfd_gfx_v10.c | 87 static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe,
93 nv_grbm_select(adev, mec, pipe, queue, vmid);
109 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; local in function:acquire_queue
110 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
112 lock_srbm(kgd, mec, pipe, queue_id, 0);
118 unsigned int bit = pipe_id * adev->gfx.mec.num_queue_per_pipe +
196 uint32_t mec; local in function:kgd_init_interrupts
199 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1
351 uint32_t mec, pipe; local in function:kgd_hiq_mqd_load
[all...] |
| amdgpu_amdkfd_gfx_v9.c | 83 static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe,
89 soc15_grbm_select(adev, mec, pipe, queue, vmid);
105 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; local in function:acquire_queue
106 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
108 lock_srbm(kgd, mec, pipe, queue_id, 0);
114 unsigned int bit = pipe_id * adev->gfx.mec.num_queue_per_pipe +
206 uint32_t mec; local in function:kgd_gfx_v9_init_interrupts
209 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1
339 uint32_t mec, pipe; local in function:kgd_gfx_v9_hiq_mqd_load
[all...] |
| amdgpu_amdkfd_gfx_v8.c | 79 static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe,
83 uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue);
102 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; local in function:acquire_queue
103 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
105 lock_srbm(kgd, mec, pipe, queue_id, 0);
161 uint32_t mec; local in function:kgd_init_interrupts
164 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
165 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec)
217 uint32_t value, mec, pipe; local in function:kgd_hqd_load
[all...] |
| amdgpu_amdkfd_gfx_v7.c | 122 static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe,
126 uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue);
145 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; local in function:acquire_queue
146 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
148 lock_srbm(kgd, mec, pipe, queue_id, 0);
203 uint32_t mec; local in function:kgd_init_interrupts
206 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
207 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec)
[all...] |
| amdgpu_gfx.h | 248 struct amdgpu_mec mec; member in struct:amdgpu_gfx
259 const struct firmware *mec_fw; /* MEC firmware */
360 int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec,
363 int *mec, int *pipe, int *queue);
364 bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec,
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| amdgpu_amdkfd.c | 121 .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec,
122 .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe,
135 adev->gfx.mec.queue_bitmap,
141 last_valid_bit = 1 /* only first MEC can have compute queues */
142 * adev->gfx.mec.num_pipe_per_mec
143 * adev->gfx.mec.num_queue_per_pipe;
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| amdgpu_gfx_v10_0.c | 1031 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
1032 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
1061 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
1069 &adev->gfx.mec.hpd_eop_obj,
1070 &adev->gfx.mec.hpd_eop_gpu_addr,
1078 memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
1080 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
1081 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
1092 &adev->gfx.mec.mec_fw_obj,
1093 &adev->gfx.mec.mec_fw_gpu_addr
[all...] |
| amdgpu_gfx_v7_0.c | 2428 * Each MEC supports 4 compute pipes and each pipe supports 8 queues.
2805 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
2814 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
2820 mec_hpd_size = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec
2825 &adev->gfx.mec.hpd_eop_obj,
2826 &adev->gfx.mec.hpd_eop_gpu_addr,
2837 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
2838 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
2883 int mec, int pipe
[all...] |
| amdgpu_gfx_v9_0.c | 1861 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
1862 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
1876 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
1884 &adev->gfx.mec.hpd_eop_obj,
1885 &adev->gfx.mec.hpd_eop_gpu_addr,
1893 memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
1895 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
1896 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
1907 &adev->gfx.mec.mec_fw_obj,
1908 &adev->gfx.mec.mec_fw_gpu_addr
[all...] |
| amdgpu_gfx_v8_0.c | 1334 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
1343 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
1352 &adev->gfx.mec.hpd_eop_obj,
1353 &adev->gfx.mec.hpd_eop_gpu_addr,
1362 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
1363 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
1889 int mec, int pipe, int queue)
1898 ring->me = mec + 1;
1905 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
1910 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/amdkfd/ |
| kfd_device_queue_manager.c | 77 static bool is_pipe_enabled(struct device_queue_manager *dqm, int mec, int pipe)
80 int pipe_offset = mec * dqm->dev->shared_resources.num_pipe_per_mec
1027 int i, mec; local in function:set_sched_resources
1034 mec = (i / dqm->dev->shared_resources.num_queue_per_pipe)
1040 /* only acquire queues from the first MEC */
1041 if (mec > 0)
1973 seq_printf(m, " HIQ on MEC %d Pipe %d Queue %d\n",
|
| kfd_priv.h | 171 * Whether MEC FW support GWS barriers
470 * @mec: Used only in no cp scheduling mode and identifies to micro engine id
497 uint32_t mec; member in struct:queue
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| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_cik.c | 3878 * Each MEC supports 4 compute pipes and each pipe supports 8 queues.
4389 if (rdev->mec.hpd_eop_obj) {
4390 r = radeon_bo_reserve(rdev->mec.hpd_eop_obj, false);
4393 radeon_bo_unpin(rdev->mec.hpd_eop_obj);
4394 radeon_bo_unreserve(rdev->mec.hpd_eop_obj);
4396 radeon_bo_unref(&rdev->mec.hpd_eop_obj);
4397 rdev->mec.hpd_eop_obj = NULL;
4409 * KV: 2 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 64 Queues total
4410 * CI/KB: 1 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 32 Queues tota
[all...] |
| radeon.h | 2463 const struct firmware *mec_fw; /* CIK MEC firmware */
2474 struct radeon_mec mec; member in struct:radeon_device
|
| /src/sys/dev/pci/ |
| mfii.c | 1312 union mfi_evt_class_locale mec; local in function:mfii_aen_start
1322 mec.mec_members.class = MFI_EVT_CLASS_DEBUG;
1323 mec.mec_members.reserved = 0;
1324 mec.mec_members.locale = htole16(MFI_EVT_LOCALE_ALL);
1332 dcmd->mdf_mbox.w[1] = htole32(mec.mec_word);
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| /src/sys/arch/sgimips/mace/ |
| if_mec.c | 409 CFATTACH_DECL_NEW(mec, sizeof(struct mec_softc),
607 /* mec has dumb RX cksum support */
936 DPRINTF(MEC_DEBUG_RESET, ("mec: control now %llx\n",
1005 * I don't know if MEC chip does auto padding,
1691 * The MEC includes the CRC with every packet. Trim
1718 * Note MEC chip seems to insert 2 byte padding at the top of
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