1 /* $NetBSD: if_emac.c,v 1.61 2026/06/14 00:02:35 rkujawa Exp $ */ 2 3 /* 4 * Copyright 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Simon Burge and Jason Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * emac(4) supports following ibm4xx's EMACs. 40 * XXXX: ZMII not supported yet... 41 * The 'TCP Acceleration Hardware' (TAH) checksum offload engine is 42 * supported on the 460EX/GT with options EMAC_TAH. 43 * 44 * tested 45 * ------ 46 * 405EP - 10/100 x2 47 * 405EX/EXr o 10/100/1000 x2 (EXr x1), STA v2, 256bit hash-Table, RGMII 48 * 405GP/GPr o 10/100 49 * 440EP - 10/100 x2, ZMII 50 * 440GP - 10/100 x2, ZMII 51 * 440GX - 10/100/1000 x4, ZMII/RGMII(ch 2, 3), TAH(ch 2, 3) 52 * 440SP - 10/100/1000 53 * 440SPe - 10/100/1000, STA v2 54 * 460EX - 10/100/1000, STA v2, 256bit hash-Table, RGMII, TAH 55 */ 56 57 #include <sys/cdefs.h> 58 __KERNEL_RCSID(0, "$NetBSD: if_emac.c,v 1.61 2026/06/14 00:02:35 rkujawa Exp $"); 59 60 #ifdef _KERNEL_OPT 61 #include "opt_emac.h" 62 #ifdef EMAC_TAH 63 #include "opt_inet.h" 64 #endif 65 #endif 66 67 #include <sys/param.h> 68 #include <sys/systm.h> 69 #include <sys/mbuf.h> 70 #include <sys/kernel.h> 71 #include <sys/timevar.h> 72 #include <sys/socket.h> 73 #include <sys/ioctl.h> 74 #include <sys/cpu.h> 75 #include <sys/device.h> 76 77 #include <sys/rndsource.h> 78 79 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 80 81 #include <net/if.h> 82 #include <net/if_dl.h> 83 #include <net/if_media.h> 84 #include <net/if_ether.h> 85 86 #include <net/bpf.h> 87 88 #ifdef EMAC_TAH 89 #include <netinet/in.h> 90 #include <netinet/in_systm.h> 91 #include <netinet/ip.h> 92 #include <netinet/tcp.h> 93 #include <netinet/udp.h> 94 #include <netinet/in_offload.h> 95 #ifdef INET6 96 #include <netinet/ip6.h> 97 #include <netinet6/in6_offload.h> 98 #endif 99 #endif 100 101 #include <powerpc/ibm4xx/cpu.h> 102 #include <powerpc/ibm4xx/dcr4xx.h> 103 #include <powerpc/ibm4xx/mal405gp.h> 104 #ifdef EMAC_TAH 105 #include <powerpc/ibm4xx/amcc460ex.h> 106 #endif 107 #include <powerpc/ibm4xx/dev/emacreg.h> 108 #include <powerpc/ibm4xx/dev/if_emacreg.h> 109 #include <powerpc/ibm4xx/dev/if_emacvar.h> 110 #include <powerpc/ibm4xx/dev/malvar.h> 111 #include <powerpc/ibm4xx/dev/opbreg.h> 112 #include <powerpc/ibm4xx/dev/opbvar.h> 113 #include <powerpc/ibm4xx/dev/plbvar.h> 114 #if defined(EMAC_ZMII_PHY) || defined(EMAC_RGMII_PHY) 115 #include <powerpc/ibm4xx/dev/rmiivar.h> 116 #endif 117 118 #include <dev/mii/miivar.h> 119 120 #include "locators.h" 121 122 123 /* 124 * Transmit descriptor list size. There are two Tx channels, each with 125 * up to 256 hardware descriptors available. We currently use one Tx 126 * channel. We tell the upper layers that they can queue a lot of 127 * packets, and we go ahead and manage up to 64 of them at a time. We 128 * allow up to 16 DMA segments per packet. 129 */ 130 #define EMAC_NTXSEGS 16 131 #define EMAC_TXQUEUELEN 64 132 #define EMAC_TXQUEUELEN_MASK (EMAC_TXQUEUELEN - 1) 133 #define EMAC_TXQUEUE_GC (EMAC_TXQUEUELEN / 4) 134 #define EMAC_NTXDESC 256 135 #define EMAC_NTXDESC_MASK (EMAC_NTXDESC - 1) 136 #define EMAC_NEXTTX(x) (((x) + 1) & EMAC_NTXDESC_MASK) 137 #define EMAC_NEXTTXS(x) (((x) + 1) & EMAC_TXQUEUELEN_MASK) 138 139 /* 140 * Receive descriptor list size. There is one Rx channel with up to 256 141 * hardware descriptors available. We allocate 64 receive descriptors, 142 * each with a 2k buffer (MCLBYTES). 143 */ 144 #define EMAC_NRXDESC 64 145 #define EMAC_NRXDESC_MASK (EMAC_NRXDESC - 1) 146 #define EMAC_NEXTRX(x) (((x) + 1) & EMAC_NRXDESC_MASK) 147 #define EMAC_PREVRX(x) (((x) - 1) & EMAC_NRXDESC_MASK) 148 149 #ifdef EMAC_TAH 150 /* 151 * TSO via the TAH. Tx DMA maps must take a full combined packet 152 * (the MAL buffer length field is 12 bits, so segments stay below 4KB) 153 */ 154 #define EMAC_TSO_NSSR 6 /* TAH_SSR0..5 */ 155 #define EMAC_TSO_NTXSEGS 40 /* 64KB of 2KB clusters + slack */ 156 #define EMAC_TSO_MAXLEN (IP_MAXPACKET + ETHER_HDR_LEN) 157 #define EMAC_TSO_MAXSEGSZ MCLBYTES 158 #define EMAC_TSO_SEG_MIN 168 159 #define EMAC_TSO_SEG_MAX 9700 160 #endif 161 162 /* 163 * Transmit/receive descriptors that are DMA'd to the EMAC. 164 */ 165 struct emac_control_data { 166 struct mal_descriptor ecd_txdesc[EMAC_NTXDESC]; 167 struct mal_descriptor ecd_rxdesc[EMAC_NRXDESC]; 168 }; 169 170 #define EMAC_CDOFF(x) offsetof(struct emac_control_data, x) 171 #define EMAC_CDTXOFF(x) EMAC_CDOFF(ecd_txdesc[(x)]) 172 #define EMAC_CDRXOFF(x) EMAC_CDOFF(ecd_rxdesc[(x)]) 173 174 /* 175 * Software state for transmit jobs. 176 */ 177 struct emac_txsoft { 178 struct mbuf *txs_mbuf; /* head of mbuf chain */ 179 bus_dmamap_t txs_dmamap; /* our DMA map */ 180 int txs_firstdesc; /* first descriptor in packet */ 181 int txs_lastdesc; /* last descriptor in packet */ 182 int txs_ndesc; /* # of descriptors used */ 183 #ifdef EMAC_TAH 184 int8_t txs_ssr; /* TAH_SSR slot held, -1 = none */ 185 uint16_t txs_opackets; /* wire packets this job produces */ 186 #endif 187 }; 188 189 /* 190 * Software state for receive descriptors. 191 */ 192 struct emac_rxsoft { 193 struct mbuf *rxs_mbuf; /* head of mbuf chain */ 194 bus_dmamap_t rxs_dmamap; /* our DMA map */ 195 }; 196 197 /* 198 * Software state per device. 199 */ 200 struct emac_softc { 201 device_t sc_dev; /* generic device information */ 202 int sc_instance; /* instance no. */ 203 bus_space_tag_t sc_st; /* bus space tag */ 204 bus_space_handle_t sc_sh; /* bus space handle */ 205 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 206 struct ethercom sc_ethercom; /* ethernet common data */ 207 void *sc_sdhook; /* shutdown hook */ 208 void *sc_powerhook; /* power management hook */ 209 210 struct mii_data sc_mii; /* MII/media information */ 211 struct callout sc_callout; /* tick callout */ 212 213 uint32_t sc_mr1; /* copy of Mode Register 1 */ 214 uint32_t sc_stacr_read; /* Read opcode of STAOPC of STACR */ 215 uint32_t sc_stacr_write; /* Write opcode of STAOPC of STACR */ 216 uint32_t sc_stacr_bits; /* misc bits of STACR */ 217 bool sc_stacr_completed; /* Operation completed of STACR */ 218 int sc_htsize; /* Hash Table size */ 219 bool sc_ethcfg_ecs; /* clock select via SDR0_ETH_CFG */ 220 #ifdef EMAC_TAH 221 bus_space_handle_t sc_tahh; /* TAH bus space handle */ 222 bool sc_tah; /* TAH present, mapped and in path */ 223 bool sc_tah_cvr; /* RX checksum verification enabled */ 224 225 /* IFF_DEBUG diagnostics for the per-packet status interrupt */ 226 uint32_t sc_isr_seen; /* accumulated ISR bits */ 227 uint32_t sc_isr_zero; /* interrupts with empty ISR */ 228 struct timeval sc_isr_last; /* report rate limit */ 229 230 /* 231 * TSO segment-size register cache: a TAH_SSR slot may only be 232 * rewritten while no unreaped transmit job references it. 233 */ 234 uint16_t sc_ssr_bytes[EMAC_TSO_NSSR]; /* programmed size, 0 = none */ 235 uint16_t sc_ssr_refs[EMAC_TSO_NSSR]; /* in-flight references */ 236 struct mbuf *sc_txpending; /* sw-segmented chain (m_nextpkt) */ 237 #endif 238 239 bus_dmamap_t sc_cddmamap; /* control data dma map */ 240 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 241 242 /* Software state for transmit/receive descriptors. */ 243 struct emac_txsoft sc_txsoft[EMAC_TXQUEUELEN]; 244 struct emac_rxsoft sc_rxsoft[EMAC_NRXDESC]; 245 246 /* Control data structures. */ 247 struct emac_control_data *sc_control_data; 248 #define sc_txdescs sc_control_data->ecd_txdesc 249 #define sc_rxdescs sc_control_data->ecd_rxdesc 250 251 #ifdef EMAC_EVENT_COUNTERS 252 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 253 struct evcnt sc_ev_txintr; /* Tx interrupts */ 254 struct evcnt sc_ev_rxde; /* Rx descriptor interrupts */ 255 struct evcnt sc_ev_txde; /* Tx descriptor interrupts */ 256 struct evcnt sc_ev_intr; /* General EMAC interrupts */ 257 258 struct evcnt sc_ev_txreap; /* Calls to Tx descriptor reaper */ 259 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 260 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 261 struct evcnt sc_ev_txdrop; /* Tx packets dropped (too many segs) */ 262 struct evcnt sc_ev_tu; /* Tx underrun */ 263 #ifdef EMAC_TAH 264 struct evcnt sc_ev_txcsum; /* Tx packets checksummed by the TAH */ 265 struct evcnt sc_ev_tahted; /* TAH transmit errors (TSR) */ 266 struct evcnt sc_ev_rxcsum; /* Rx packets verified by the TAH */ 267 struct evcnt sc_ev_rxcsumbad; /* Rx checksum errors from the TAH */ 268 struct evcnt sc_ev_txtso; /* Tx bursts segmented by the TAH */ 269 struct evcnt sc_ev_txtsofb; /* Tx TSO software fallbacks */ 270 #endif 271 #endif /* EMAC_EVENT_COUNTERS */ 272 273 int sc_txfree; /* number of free Tx descriptors */ 274 int sc_txnext; /* next ready Tx descriptor */ 275 276 int sc_txsfree; /* number of free Tx jobs */ 277 int sc_txsnext; /* next ready Tx job */ 278 int sc_txsdirty; /* dirty Tx jobs */ 279 280 int sc_rxptr; /* next ready RX descriptor/descsoft */ 281 282 krndsource_t rnd_source; /* random source */ 283 284 void (*sc_rmii_enable)(device_t, int); /* reduced MII enable */ 285 void (*sc_rmii_disable)(device_t, int); /* reduced MII disable*/ 286 void (*sc_rmii_speed)(device_t, int, int); /* reduced MII speed */ 287 }; 288 289 #ifdef EMAC_EVENT_COUNTERS 290 #define EMAC_EVCNT_INCR(ev) (ev)->ev_count++ 291 #else 292 #define EMAC_EVCNT_INCR(ev) /* nothing */ 293 #endif 294 295 #define EMAC_CDTXADDR(sc, x) ((sc)->sc_cddma + EMAC_CDTXOFF((x))) 296 #define EMAC_CDRXADDR(sc, x) ((sc)->sc_cddma + EMAC_CDRXOFF((x))) 297 298 #define EMAC_CDTXSYNC(sc, x, n, ops) \ 299 do { \ 300 int __x, __n; \ 301 \ 302 __x = (x); \ 303 __n = (n); \ 304 \ 305 /* If it will wrap around, sync to the end of the ring. */ \ 306 if ((__x + __n) > EMAC_NTXDESC) { \ 307 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 308 EMAC_CDTXOFF(__x), sizeof(struct mal_descriptor) * \ 309 (EMAC_NTXDESC - __x), (ops)); \ 310 __n -= (EMAC_NTXDESC - __x); \ 311 __x = 0; \ 312 } \ 313 \ 314 /* Now sync whatever is left. */ \ 315 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 316 EMAC_CDTXOFF(__x), sizeof(struct mal_descriptor) * __n, (ops)); \ 317 } while (/*CONSTCOND*/0) 318 319 #define EMAC_CDRXSYNC(sc, x, ops) \ 320 do { \ 321 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 322 EMAC_CDRXOFF((x)), sizeof(struct mal_descriptor), (ops)); \ 323 } while (/*CONSTCOND*/0) 324 325 #define EMAC_INIT_RXDESC(sc, x) \ 326 do { \ 327 struct emac_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 328 struct mal_descriptor *__rxd = &(sc)->sc_rxdescs[(x)]; \ 329 struct mbuf *__m = __rxs->rxs_mbuf; \ 330 \ 331 /* \ 332 * Note: We scoot the packet forward 2 bytes in the buffer \ 333 * so that the payload after the Ethernet header is aligned \ 334 * to a 4-byte boundary. \ 335 */ \ 336 __m->m_data = __m->m_ext.ext_buf + 2; \ 337 \ 338 __rxd->md_data = __rxs->rxs_dmamap->dm_segs[0].ds_addr + 2; \ 339 __rxd->md_data_len = __m->m_ext.ext_size - 2; \ 340 __rxd->md_stat_ctrl = MAL_RX_EMPTY | MAL_RX_INTERRUPT | \ 341 /* Set wrap on last descriptor. */ \ 342 (((x) == EMAC_NRXDESC - 1) ? MAL_RX_WRAP : 0); \ 343 EMAC_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); \ 344 } while (/*CONSTCOND*/0) 345 346 #define EMAC_WRITE(sc, reg, val) \ 347 bus_space_write_stream_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 348 #define EMAC_READ(sc, reg) \ 349 bus_space_read_stream_4((sc)->sc_st, (sc)->sc_sh, (reg)) 350 351 #ifdef EMAC_TAH 352 #define TAH_WRITE(sc, reg, val) \ 353 bus_space_write_stream_4((sc)->sc_st, (sc)->sc_tahh, (reg), (val)) 354 #define TAH_READ(sc, reg) \ 355 bus_space_read_stream_4((sc)->sc_st, (sc)->sc_tahh, (reg)) 356 #endif 357 358 #define EMAC_SET_FILTER(aht, crc) \ 359 do { \ 360 (aht)[3 - (((crc) >> 26) >> 4)] |= 1 << (((crc) >> 26) & 0xf); \ 361 } while (/*CONSTCOND*/0) 362 #define EMAC_SET_FILTER256(aht, crc) \ 363 do { \ 364 (aht)[7 - (((crc) >> 24) >> 5)] |= 1 << (((crc) >> 24) & 0x1f); \ 365 } while (/*CONSTCOND*/0) 366 367 static int emac_match(device_t, cfdata_t, void *); 368 static void emac_attach(device_t, device_t, void *); 369 370 static int emac_intr(void *); 371 static void emac_shutdown(void *); 372 373 static void emac_start(struct ifnet *); 374 static int emac_ioctl(struct ifnet *, u_long, void *); 375 static int emac_init(struct ifnet *); 376 static void emac_stop(struct ifnet *, int); 377 static void emac_watchdog(struct ifnet *); 378 379 static int emac_add_rxbuf(struct emac_softc *, int); 380 static void emac_rxdrain(struct emac_softc *); 381 static int emac_set_filter(struct emac_softc *); 382 static int emac_txreap(struct emac_softc *); 383 384 static void emac_soft_reset(struct emac_softc *); 385 static void emac_smart_reset(struct emac_softc *); 386 #ifdef EMAC_TAH 387 static void emac_tah_reset(struct emac_softc *); 388 #endif 389 390 static int emac_mii_readreg(device_t, int, int, uint16_t *); 391 static int emac_mii_writereg(device_t, int, int, uint16_t); 392 static void emac_mii_statchg(struct ifnet *); 393 static uint32_t emac_mii_wait(struct emac_softc *); 394 static void emac_mii_tick(void *); 395 396 int emac_copy_small = 0; 397 398 CFATTACH_DECL_NEW(emac, sizeof(struct emac_softc), 399 emac_match, emac_attach, NULL, NULL); 400 401 402 static int 403 emac_match(device_t parent, cfdata_t cf, void *aux) 404 { 405 struct opb_attach_args *oaa = aux; 406 407 /* match only on-chip ethernet devices */ 408 if (strcmp(oaa->opb_name, cf->cf_name) == 0) 409 return 1; 410 411 return 0; 412 } 413 414 static void 415 emac_attach(device_t parent, device_t self, void *aux) 416 { 417 struct opb_attach_args *oaa = aux; 418 struct emac_softc *sc = device_private(self); 419 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 420 struct mii_data *mii = &sc->sc_mii; 421 const char * xname = device_xname(self); 422 bus_dma_segment_t seg; 423 int error, i, nseg, opb_freq, opbc, mii_phy = MII_PHY_ANY; 424 uint8_t enaddr[ETHER_ADDR_LEN]; 425 426 bus_space_map(oaa->opb_bt, oaa->opb_addr, EMAC_NREG, 0, &sc->sc_sh); 427 428 sc->sc_dev = self; 429 sc->sc_instance = oaa->opb_instance; 430 sc->sc_st = oaa->opb_bt; 431 sc->sc_dmat = oaa->opb_dmat; 432 433 callout_init(&sc->sc_callout, 0); 434 435 aprint_naive("\n"); 436 aprint_normal(": Ethernet Media Access Controller\n"); 437 438 /* Fetch the Ethernet address. */ 439 if (! ether_getaddr(self, enaddr)) { 440 aprint_error_dev(self, "unable to get mac-address\n"); 441 return; 442 } 443 aprint_normal_dev(self, "Ethernet address %s\n", ether_sprintf(enaddr)); 444 445 #if defined(EMAC_ZMII_PHY) || defined(EMAC_RGMII_PHY) 446 /* Fetch the MII offset. */ 447 prop_dictionary_get_uint32(device_properties(self), 448 "mii-phy", &mii_phy); 449 450 #ifdef EMAC_ZMII_PHY 451 if (oaa->opb_flags & OPB_FLAGS_EMAC_RMII_ZMII) 452 zmii_attach(parent, sc->sc_instance, &sc->sc_rmii_enable, 453 &sc->sc_rmii_disable, &sc->sc_rmii_speed); 454 #endif 455 #ifdef EMAC_RGMII_PHY 456 if (oaa->opb_flags & OPB_FLAGS_EMAC_RMII_RGMII) 457 rgmii_attach(parent, sc->sc_instance, &sc->sc_rmii_enable, 458 &sc->sc_rmii_disable, &sc->sc_rmii_speed); 459 #endif 460 #endif 461 462 /* 463 * Allocate the control data structures, and create and load the 464 * DMA map for it. 465 */ 466 if ((error = bus_dmamem_alloc(sc->sc_dmat, 467 sizeof(struct emac_control_data), 0, 0, &seg, 1, &nseg, 0)) != 0) { 468 aprint_error_dev(self, 469 "unable to allocate control data, error = %d\n", error); 470 goto fail_0; 471 } 472 473 /* 474 * Map the descriptor ring UNCACHED, no cache snooping of any kind. 475 */ 476 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, nseg, 477 sizeof(struct emac_control_data), (void **)&sc->sc_control_data, 478 BUS_DMA_DONTCACHE)) != 0) { 479 aprint_error_dev(self, 480 "unable to map control data, error = %d\n", error); 481 goto fail_1; 482 } 483 484 if ((error = bus_dmamap_create(sc->sc_dmat, 485 sizeof(struct emac_control_data), 1, 486 sizeof(struct emac_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 487 aprint_error_dev(self, 488 "unable to create control data DMA map, error = %d\n", 489 error); 490 goto fail_2; 491 } 492 493 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 494 sc->sc_control_data, sizeof(struct emac_control_data), NULL, 495 0)) != 0) { 496 aprint_error_dev(self, 497 "unable to load control data DMA map, error = %d\n", error); 498 goto fail_3; 499 } 500 501 #ifdef EMAC_TAH 502 /* 503 * Map and configure the TAH offload 504 */ 505 if (oaa->opb_flags & OPB_FLAGS_EMAC_TAH) { 506 if (bus_space_map(oaa->opb_bt, 507 AMCC460EX_TAH0_BASE + 0x100 * sc->sc_instance, 508 TAH_NREG, 0, &sc->sc_tahh) == 0) { 509 sc->sc_tah = true; 510 emac_tah_reset(sc); 511 aprint_normal_dev(self, 512 "TAH offload engine, rev. 0x%08x\n", 513 TAH_READ(sc, TAH_REVID)); 514 } else 515 aprint_error_dev(self, 516 "unable to map TAH registers, offload disabled\n"); 517 } 518 #endif 519 520 /* 521 * Create the transmit buffer DMA maps, dimensioned for a full 522 * TSO burst when the TAH will segment for us. 523 */ 524 for (i = 0; i < EMAC_TXQUEUELEN; i++) { 525 #ifdef EMAC_TAH 526 if (sc->sc_tah) 527 error = bus_dmamap_create(sc->sc_dmat, 528 EMAC_TSO_MAXLEN, EMAC_TSO_NTXSEGS, 529 EMAC_TSO_MAXSEGSZ, 0, 0, 530 &sc->sc_txsoft[i].txs_dmamap); 531 else 532 #endif 533 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 534 EMAC_NTXSEGS, MCLBYTES, 0, 0, 535 &sc->sc_txsoft[i].txs_dmamap); 536 if (error != 0) { 537 aprint_error_dev(self, 538 "unable to create tx DMA map %d, error = %d\n", 539 i, error); 540 goto fail_4; 541 } 542 #ifdef EMAC_TAH 543 sc->sc_txsoft[i].txs_ssr = -1; 544 #endif 545 } 546 547 /* 548 * Create the receive buffer DMA maps. 549 */ 550 for (i = 0; i < EMAC_NRXDESC; i++) { 551 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 552 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 553 aprint_error_dev(self, 554 "unable to create rx DMA map %d, error = %d\n", 555 i, error); 556 goto fail_5; 557 } 558 sc->sc_rxsoft[i].rxs_mbuf = NULL; 559 } 560 561 /* 562 * 460EX/GT moved the EMAC clock-select bits used during soft 563 * reset from SDR0_MFR to SDR0_ETH_CFG. 564 */ 565 sc->sc_ethcfg_ecs = (oaa->opb_flags & OPB_FLAGS_EMAC_ETHCFG_ECS) != 0; 566 567 if (sc->sc_ethcfg_ecs) { 568 uint32_t sdr; 569 570 /* 571 * Bypass the TAH offload engine 572 */ 573 sdr = mfsdr(DCR_SDR0_ETH_CFG); 574 #ifdef EMAC_TAH 575 if (sc->sc_tah) 576 sdr &= ~SDR0_ETH_CFG_TAH_BYPASS(sc->sc_instance); 577 else 578 #endif 579 sdr |= SDR0_ETH_CFG_TAH_BYPASS(sc->sc_instance); 580 mtsdr(DCR_SDR0_ETH_CFG, sdr); 581 } 582 583 /* Soft Reset the EMAC. The chip to a known state. */ 584 emac_soft_reset(sc); 585 586 opb_freq = opb_get_frequency(); 587 switch (opb_freq) { 588 case 33333333: opbc = STACR_OPBC_33MHZ; break; 589 case 50000000: opbc = STACR_OPBC_50MHZ; break; 590 case 66666666: opbc = STACR_OPBC_66MHZ; break; 591 case 83333333: opbc = STACR_OPBC_83MHZ; break; 592 case 100000000: opbc = STACR_OPBC_100MHZ; break; 593 594 default: 595 if (opb_freq > 100000000) { 596 opbc = STACR_OPBC_A100MHZ; 597 break; 598 } 599 aprint_error_dev(self, "unsupported OPB frequency %dMHz\n", 600 opb_freq / 1000 / 1000); 601 goto fail_5; 602 } 603 if (oaa->opb_flags & OPB_FLAGS_EMAC_GBE) { 604 sc->sc_mr1 = 605 MR1_RFS_GBE(MR1__FS_16KB) | 606 #ifdef EMAC_TAH 607 /* 608 * The 460EX EMAC0/1 transmit FIFO is 2KB! 609 */ 610 MR1_TFS_GBE(MR1__FS_2KB) | 611 #else 612 MR1_TFS_GBE(MR1__FS_16KB) | 613 #endif 614 MR1_TR0_MULTIPLE | 615 MR1_OBCI(opbc); 616 /* 617 * Do NOT set MR1_MWSW here 618 * EMAC holds the last packet's TX status to overlap 619 * it with the next packet 620 */ 621 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 622 623 if (oaa->opb_flags & OPB_FLAGS_EMAC_STACV2) { 624 sc->sc_stacr_read = STACR_STAOPC_READ; 625 sc->sc_stacr_write = STACR_STAOPC_WRITE; 626 sc->sc_stacr_bits = STACR_OC; 627 sc->sc_stacr_completed = false; 628 } else { 629 sc->sc_stacr_read = STACR_READ; 630 sc->sc_stacr_write = STACR_WRITE; 631 sc->sc_stacr_completed = true; 632 } 633 } else { 634 /* 635 * Set up Mode Register 1 - set receive and transmit FIFOs to 636 * maximum size, allow transmit of multiple packets (only 637 * channel 0 is used). 638 * 639 * XXX: Allow pause packets?? 640 */ 641 sc->sc_mr1 = 642 MR1_RFS(MR1__FS_4KB) | 643 MR1_TFS(MR1__FS_2KB) | 644 MR1_TR0_MULTIPLE; 645 646 sc->sc_stacr_read = STACR_READ; 647 sc->sc_stacr_write = STACR_WRITE; 648 sc->sc_stacr_bits = STACR_OPBC(opbc); 649 sc->sc_stacr_completed = true; 650 } 651 652 intr_establish_xname(oaa->opb_irq, IST_LEVEL, IPL_NET, emac_intr, sc, 653 device_xname(self)); 654 mal_intr_establish(sc->sc_instance, sc); 655 656 if (oaa->opb_flags & OPB_FLAGS_EMAC_HT256) 657 sc->sc_htsize = 256; 658 else 659 sc->sc_htsize = 64; 660 661 /* Clear all interrupts */ 662 EMAC_WRITE(sc, EMAC_ISR, ISR_ALL); 663 664 /* 665 * Initialise the media structures. 666 */ 667 mii->mii_ifp = ifp; 668 mii->mii_readreg = emac_mii_readreg; 669 mii->mii_writereg = emac_mii_writereg; 670 mii->mii_statchg = emac_mii_statchg; 671 672 sc->sc_ethercom.ec_mii = mii; 673 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 674 mii_attach(self, mii, 0xffffffff, mii_phy, MII_OFFSET_ANY, 675 MIIF_DOPAUSE); 676 if (LIST_FIRST(&mii->mii_phys) == NULL) { 677 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 678 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 679 } else 680 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 681 682 ifp = &sc->sc_ethercom.ec_if; 683 strcpy(ifp->if_xname, xname); 684 ifp->if_softc = sc; 685 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 686 ifp->if_start = emac_start; 687 ifp->if_ioctl = emac_ioctl; 688 ifp->if_init = emac_init; 689 ifp->if_stop = emac_stop; 690 ifp->if_watchdog = emac_watchdog; 691 IFQ_SET_READY(&ifp->if_snd); 692 693 /* 694 * We can support 802.1Q VLAN-sized frames. 695 */ 696 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 697 698 #ifdef EMAC_TAH 699 /* 700 * The TAH generates IPv4/TCP/UDP checksums on tx and rx 701 */ 702 if (sc->sc_tah) { 703 ifp->if_capabilities |= 704 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 705 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 706 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 707 IFCAP_TSOv4; 708 #ifdef INET6 709 /* no IPv6 header checksum, hence no IFCAP for it.*/ 710 ifp->if_capabilities |= 711 IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_TCPv6_Rx | 712 IFCAP_CSUM_UDPv6_Tx | IFCAP_CSUM_UDPv6_Rx | 713 IFCAP_TSOv6; 714 #endif 715 } 716 #endif 717 718 /* 719 * Attach the interface. 720 */ 721 if_attach(ifp); 722 if_deferred_start_init(ifp, NULL); 723 ether_ifattach(ifp, enaddr); 724 725 rnd_attach_source(&sc->rnd_source, xname, RND_TYPE_NET, 726 RND_FLAG_DEFAULT); 727 728 #ifdef EMAC_EVENT_COUNTERS 729 /* 730 * Attach the event counters. 731 */ 732 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 733 NULL, xname, "txintr"); 734 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 735 NULL, xname, "rxintr"); 736 evcnt_attach_dynamic(&sc->sc_ev_txde, EVCNT_TYPE_INTR, 737 NULL, xname, "txde"); 738 evcnt_attach_dynamic(&sc->sc_ev_rxde, EVCNT_TYPE_INTR, 739 NULL, xname, "rxde"); 740 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 741 NULL, xname, "intr"); 742 743 evcnt_attach_dynamic(&sc->sc_ev_txreap, EVCNT_TYPE_MISC, 744 NULL, xname, "txreap"); 745 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 746 NULL, xname, "txsstall"); 747 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 748 NULL, xname, "txdstall"); 749 evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC, 750 NULL, xname, "txdrop"); 751 evcnt_attach_dynamic(&sc->sc_ev_tu, EVCNT_TYPE_MISC, 752 NULL, xname, "tu"); 753 #ifdef EMAC_TAH 754 evcnt_attach_dynamic(&sc->sc_ev_txcsum, EVCNT_TYPE_MISC, 755 NULL, xname, "txcsum"); 756 evcnt_attach_dynamic(&sc->sc_ev_tahted, EVCNT_TYPE_MISC, 757 NULL, xname, "tahted"); 758 evcnt_attach_dynamic(&sc->sc_ev_rxcsum, EVCNT_TYPE_MISC, 759 NULL, xname, "rxcsum"); 760 evcnt_attach_dynamic(&sc->sc_ev_rxcsumbad, EVCNT_TYPE_MISC, 761 NULL, xname, "rxcsumbad"); 762 evcnt_attach_dynamic(&sc->sc_ev_txtso, EVCNT_TYPE_MISC, 763 NULL, xname, "txtso"); 764 evcnt_attach_dynamic(&sc->sc_ev_txtsofb, EVCNT_TYPE_MISC, 765 NULL, xname, "txtsofb"); 766 #endif 767 #endif /* EMAC_EVENT_COUNTERS */ 768 769 /* 770 * Make sure the interface is shutdown during reboot. 771 */ 772 sc->sc_sdhook = shutdownhook_establish(emac_shutdown, sc); 773 if (sc->sc_sdhook == NULL) 774 aprint_error_dev(self, 775 "WARNING: unable to establish shutdown hook\n"); 776 777 return; 778 779 /* 780 * Free any resources we've allocated during the failed attach 781 * attempt. Do this in reverse order and fall through. 782 */ 783 fail_5: 784 for (i = 0; i < EMAC_NRXDESC; i++) { 785 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 786 bus_dmamap_destroy(sc->sc_dmat, 787 sc->sc_rxsoft[i].rxs_dmamap); 788 } 789 fail_4: 790 for (i = 0; i < EMAC_TXQUEUELEN; i++) { 791 if (sc->sc_txsoft[i].txs_dmamap != NULL) 792 bus_dmamap_destroy(sc->sc_dmat, 793 sc->sc_txsoft[i].txs_dmamap); 794 } 795 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 796 fail_3: 797 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 798 fail_2: 799 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 800 sizeof(struct emac_control_data)); 801 fail_1: 802 bus_dmamem_free(sc->sc_dmat, &seg, nseg); 803 fail_0: 804 return; 805 } 806 807 /* 808 * EMAC General interrupt handler 809 */ 810 static int 811 emac_intr(void *arg) 812 { 813 struct emac_softc *sc = arg; 814 uint32_t status; 815 816 EMAC_EVCNT_INCR(&sc->sc_ev_intr); 817 status = EMAC_READ(sc, EMAC_ISR); 818 819 /* Clear the interrupt status bits. */ 820 EMAC_WRITE(sc, EMAC_ISR, status); 821 822 #ifdef EMAC_TAH 823 if (__predict_false( 824 sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG)) { 825 static const struct timeval rate = { 1, 0 }; 826 827 sc->sc_isr_seen |= status; 828 if (status == 0) 829 sc->sc_isr_zero++; 830 if (ratecheck(&sc->sc_isr_last, &rate)) 831 aprint_normal_ifnet(&sc->sc_ethercom.ec_if, 832 "ISR 0x%08x (seen 0x%08x, %u empty)\n", 833 status, sc->sc_isr_seen, sc->sc_isr_zero); 834 } 835 #endif 836 837 return 1; 838 } 839 840 static void 841 emac_shutdown(void *arg) 842 { 843 struct emac_softc *sc = arg; 844 845 emac_stop(&sc->sc_ethercom.ec_if, 0); 846 847 #ifdef EMAC_TAH 848 /* 849 * Put the TAH back into bypass 850 */ 851 if (sc->sc_tah) { 852 uint32_t sdr; 853 854 sdr = mfsdr(DCR_SDR0_ETH_CFG); 855 sdr |= SDR0_ETH_CFG_TAH_BYPASS(sc->sc_instance); 856 mtsdr(DCR_SDR0_ETH_CFG, sdr); 857 } 858 #endif 859 } 860 861 862 /* 863 * ifnet interface functions 864 */ 865 866 #ifdef EMAC_TAH 867 /* 868 * Decide what the TAH can do for this packet. 869 */ 870 #define EMAC_TAHTX_SW 0 /* software handling required */ 871 #define EMAC_TAHTX_CSUM 1 /* HAC = 111: checksum insertion */ 872 #define EMAC_TAHTX_TSO 2 /* HAC = SSRn: checksum + segmentation */ 873 874 static int 875 emac_tah_tx_classify(struct mbuf *m0, u_int *ssr_bytesp) 876 { 877 const struct ether_header *eh; 878 const struct ip *ip; 879 #ifdef INET6 880 const struct ip6_hdr *ip6; 881 #endif 882 const struct tcphdr *th; 883 const int tso = m0->m_pkthdr.csum_flags & (M_CSUM_TSOv4 884 #ifdef INET6 885 | M_CSUM_TSOv6 886 #endif 887 ); 888 u_int bytes; 889 890 /* 891 * The headers of locally generated packets are contiguous in 892 * the first mbuf; anything else falls back to software. 893 */ 894 if (m0->m_len < sizeof(*eh)) 895 return EMAC_TAHTX_SW; 896 eh = mtod(m0, const struct ether_header *); 897 898 switch (ntohs(eh->ether_type)) { 899 case ETHERTYPE_IP: 900 if (m0->m_len < sizeof(*eh) + sizeof(*ip)) 901 return EMAC_TAHTX_SW; 902 ip = (const struct ip *)(mtod(m0, const char *) + 903 sizeof(*eh)); 904 if (ip->ip_hl != 5) 905 return EMAC_TAHTX_SW; /* options: TAH_TSR[IPOP] */ 906 if (ip->ip_off & htons(IP_OFFMASK | IP_MF)) 907 return EMAC_TAHTX_SW; /* fragment: TAH_TSR[IPFP] */ 908 if (tso == 0) { 909 if (ip->ip_p != IPPROTO_TCP && 910 ip->ip_p != IPPROTO_UDP) 911 return EMAC_TAHTX_SW; /* TAH_TSR[UP] */ 912 if (ntohs(ip->ip_len) < 40) 913 return EMAC_TAHTX_SW; /* TAH_TSR[ILTS] */ 914 return EMAC_TAHTX_CSUM; 915 } 916 /* M_CSUM_TSOv4; M_CSUM_IPv4 may ride along (ip_output) */ 917 if (ip->ip_p != IPPROTO_TCP) 918 return EMAC_TAHTX_SW; /* TAH_TSR[SUDP] */ 919 if (m0->m_len < sizeof(*eh) + sizeof(*ip) + sizeof(*th)) 920 return EMAC_TAHTX_SW; 921 if (ntohs(ip->ip_len) != m0->m_pkthdr.len - sizeof(*eh)) 922 return EMAC_TAHTX_SW; /* TAH_TSR[DLM] */ 923 th = (const struct tcphdr *)((const char *)ip + sizeof(*ip)); 924 bytes = m0->m_pkthdr.segsz + sizeof(*ip) + sizeof(*th); 925 goto tso_common; 926 927 #ifdef INET6 928 case ETHERTYPE_IPV6: 929 if (m0->m_len < sizeof(*eh) + sizeof(*ip6)) 930 return EMAC_TAHTX_SW; 931 ip6 = (const struct ip6_hdr *)(mtod(m0, const char *) + 932 sizeof(*eh)); 933 /* extension headers: TAH_TSR[IP6EHP]/[IP6UNH] */ 934 if (tso == 0) { 935 if (ip6->ip6_nxt != IPPROTO_TCP && 936 ip6->ip6_nxt != IPPROTO_UDP) 937 return EMAC_TAHTX_SW; 938 return EMAC_TAHTX_CSUM; 939 } 940 /* M_CSUM_TSOv6 */ 941 if (ip6->ip6_nxt != IPPROTO_TCP) 942 return EMAC_TAHTX_SW; 943 if (m0->m_len < sizeof(*eh) + sizeof(*ip6) + sizeof(*th)) 944 return EMAC_TAHTX_SW; 945 if (ntohs(ip6->ip6_plen) != 946 m0->m_pkthdr.len - sizeof(*eh) - sizeof(*ip6)) 947 return EMAC_TAHTX_SW; /* TAH_TSR[IP6HPLM] */ 948 th = (const struct tcphdr *)((const char *)ip6 + 949 sizeof(*ip6)); 950 bytes = m0->m_pkthdr.segsz + sizeof(*ip6) + sizeof(*th); 951 goto tso_common; 952 #endif 953 954 default: 955 /* VLAN-tagged or LLC/SNAP frames? */ 956 return EMAC_TAHTX_SW; 957 } 958 959 tso_common: 960 /* 961 * TAH does not replicate TCP options! 962 */ 963 if (th->th_off != sizeof(*th) >> 2) 964 return EMAC_TAHTX_SW; 965 if (th->th_flags & (TH_SYN | TH_RST)) 966 return EMAC_TAHTX_SW; /* TAH_TSR[TFP] */ 967 /* TAH_SSR holds halfwords; bounds per TAH_TSR[SSTS]/FIFO size */ 968 if ((bytes & 1) != 0 || 969 bytes < EMAC_TSO_SEG_MIN || bytes > EMAC_TSO_SEG_MAX) 970 return EMAC_TAHTX_SW; 971 *ssr_bytesp = bytes; 972 return EMAC_TAHTX_TSO; 973 } 974 975 /* 976 * Claim a TAH segment-size register slot for byte-sized segments 977 */ 978 static int 979 emac_tso_ssr_claim(struct emac_softc *sc, u_int bytes) 980 { 981 int i, free = -1; 982 983 for (i = 0; i < EMAC_TSO_NSSR; i++) { 984 if (sc->sc_ssr_bytes[i] == bytes) { 985 sc->sc_ssr_refs[i]++; 986 return i; 987 } 988 if (free < 0 && sc->sc_ssr_refs[i] == 0) 989 free = i; 990 } 991 if (free >= 0) { 992 TAH_WRITE(sc, TAH_SSR(free), TAH_SSR_SS(bytes / 2)); 993 sc->sc_ssr_bytes[free] = bytes; 994 sc->sc_ssr_refs[free] = 1; 995 } 996 return free; 997 } 998 999 static void 1000 emac_tso_ssr_release(struct emac_softc *sc, struct emac_txsoft *txs) 1001 { 1002 1003 if (txs->txs_ssr >= 0) { 1004 KASSERT(sc->sc_ssr_refs[txs->txs_ssr] > 0); 1005 sc->sc_ssr_refs[txs->txs_ssr]--; 1006 txs->txs_ssr = -1; 1007 } 1008 } 1009 1010 /* 1011 * Segment a TSO combined packet in software 1012 */ 1013 static int 1014 emac_tso_sw_segment(struct emac_softc *sc, struct ifnet *ifp, 1015 struct mbuf *m0) 1016 { 1017 const struct ether_header *eh; 1018 const struct tcphdr *th; 1019 struct mbuf *m; 1020 u_int hdrlen = 0; 1021 #ifdef INET6 1022 bool v6 = false; 1023 #endif 1024 1025 /* 1026 * tcp[46]_segment() silently truncates a payload that is not a 1027 * multiple of segsz (see DIAGNOSTIC). 1028 */ 1029 if (m0->m_len >= sizeof(*eh)) { 1030 eh = mtod(m0, const struct ether_header *); 1031 switch (ntohs(eh->ether_type)) { 1032 case ETHERTYPE_IP: { 1033 const struct ip *ip; 1034 1035 if (m0->m_len < sizeof(*eh) + sizeof(*ip)) 1036 break; 1037 ip = (const struct ip *)(mtod(m0, const char *) + 1038 sizeof(*eh)); 1039 if (ip->ip_p != IPPROTO_TCP || 1040 m0->m_len < sizeof(*eh) + (ip->ip_hl << 2) + 1041 sizeof(*th)) 1042 break; 1043 th = (const struct tcphdr *)((const char *)ip + 1044 (ip->ip_hl << 2)); 1045 hdrlen = sizeof(*eh) + (ip->ip_hl << 2) + 1046 (th->th_off << 2); 1047 break; 1048 } 1049 #ifdef INET6 1050 case ETHERTYPE_IPV6: { 1051 const struct ip6_hdr *ip6; 1052 1053 if (m0->m_len < sizeof(*eh) + sizeof(*ip6) + 1054 sizeof(*th)) 1055 break; 1056 ip6 = (const struct ip6_hdr *) 1057 (mtod(m0, const char *) + sizeof(*eh)); 1058 if (ip6->ip6_nxt != IPPROTO_TCP) 1059 break; 1060 th = (const struct tcphdr *)((const char *)ip6 + 1061 sizeof(*ip6)); 1062 hdrlen = sizeof(*eh) + sizeof(*ip6) + 1063 (th->th_off << 2); 1064 v6 = true; 1065 break; 1066 } 1067 #endif 1068 } 1069 } 1070 if (m0->m_pkthdr.segsz == 0 || hdrlen == 0 || 1071 hdrlen >= m0->m_pkthdr.len || 1072 (m0->m_pkthdr.len - hdrlen) % m0->m_pkthdr.segsz != 0) { 1073 m_freem(m0); 1074 return -1; 1075 } 1076 1077 EMAC_EVCNT_INCR(&sc->sc_ev_txtsofb); 1078 1079 /* 1080 * tcp[46]_segment() consume m0, recompute all checksums in 1081 * software 1082 */ 1083 #ifdef INET6 1084 if (v6) 1085 m = tcp6_segment(m0, ETHER_HDR_LEN); 1086 else 1087 #endif 1088 m = tcp4_segment(m0, ETHER_HDR_LEN); 1089 if (m == NULL) 1090 return -1; 1091 KASSERT(sc->sc_txpending == NULL); 1092 sc->sc_txpending = m; 1093 return 0; 1094 } 1095 1096 /* 1097 * Translate the TAH RX verification result into mbuf checksum flags. 1098 */ 1099 static void 1100 emac_rx_csum(struct emac_softc *sc, struct mbuf *m, bool bad) 1101 { 1102 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1103 const struct ether_header *eh; 1104 const struct ip *ip; 1105 #ifdef INET6 1106 const struct ip6_hdr *ip6; 1107 #endif 1108 const struct udphdr *uh; 1109 int flags = 0; 1110 1111 if (m->m_len < sizeof(*eh)) 1112 return; 1113 eh = mtod(m, const struct ether_header *); 1114 1115 switch (ntohs(eh->ether_type)) { 1116 case ETHERTYPE_IP: 1117 if (m->m_len < sizeof(*eh) + sizeof(*ip)) 1118 return; 1119 ip = (const struct ip *)(mtod(m, const char *) + 1120 sizeof(*eh)); 1121 if (ip->ip_hl != 5 || 1122 (ip->ip_off & htons(IP_OFFMASK | IP_MF)) != 0) 1123 return; /* not verified by the TAH */ 1124 1125 /* 1126 * The TAH verifies TCP and UDP packets ONLY 1127 */ 1128 switch (ip->ip_p) { 1129 case IPPROTO_TCP: 1130 flags = M_CSUM_IPv4 | M_CSUM_TCPv4 | 1131 (bad ? M_CSUM_IPv4_BAD | M_CSUM_TCP_UDP_BAD : 0); 1132 break; 1133 case IPPROTO_UDP: 1134 /* 1135 * A zero UDP checksum means "no checksum" 1136 */ 1137 if (m->m_len < sizeof(*eh) + sizeof(*ip) + 1138 sizeof(*uh)) 1139 return; 1140 uh = (const struct udphdr *)((const char *)ip + 1141 sizeof(*ip)); 1142 if (uh->uh_sum == 0) 1143 return; 1144 flags = M_CSUM_IPv4 | M_CSUM_UDPv4 | 1145 (bad ? M_CSUM_IPv4_BAD | M_CSUM_TCP_UDP_BAD : 0); 1146 break; 1147 default: 1148 return; 1149 } 1150 break; 1151 1152 #ifdef INET6 1153 case ETHERTYPE_IPV6: 1154 if (m->m_len < sizeof(*eh) + sizeof(*ip6)) 1155 return; 1156 ip6 = (const struct ip6_hdr *)(mtod(m, const char *) + 1157 sizeof(*eh)); 1158 /* No header checksum in IPv6, no flags for ext headers. */ 1159 switch (ip6->ip6_nxt) { 1160 case IPPROTO_TCP: 1161 flags = M_CSUM_TCPv6 | 1162 (bad ? M_CSUM_TCP_UDP_BAD : 0); 1163 break; 1164 case IPPROTO_UDP: 1165 flags = M_CSUM_UDPv6 | 1166 (bad ? M_CSUM_TCP_UDP_BAD : 0); 1167 break; 1168 } 1169 break; 1170 #endif 1171 1172 default: 1173 return; 1174 } 1175 1176 if (flags == 0) 1177 return; 1178 1179 #ifdef EMAC_EVENT_COUNTERS 1180 if (bad) 1181 EMAC_EVCNT_INCR(&sc->sc_ev_rxcsumbad); 1182 else 1183 EMAC_EVCNT_INCR(&sc->sc_ev_rxcsum); 1184 #endif 1185 1186 /* Claim only the enabled "good" flags; propagate BAD always. */ 1187 m->m_pkthdr.csum_flags |= flags & (ifp->if_csum_flags_rx | 1188 M_CSUM_IPv4_BAD | M_CSUM_TCP_UDP_BAD); 1189 } 1190 #endif /* EMAC_TAH */ 1191 1192 static void 1193 emac_start(struct ifnet *ifp) 1194 { 1195 struct emac_softc *sc = ifp->if_softc; 1196 struct mbuf *m0; 1197 struct emac_txsoft *txs; 1198 bus_dmamap_t dmamap; 1199 int error, firsttx, nexttx, lasttx, ofree, seg; 1200 #ifdef EMAC_TAH 1201 uint16_t txc; 1202 u_int tso_bytes; 1203 int tah_ssr, tah_cls; 1204 bool tah_pending; 1205 #endif 1206 1207 lasttx = 0; /* XXX gcc */ 1208 1209 if ((ifp->if_flags & IFF_RUNNING) == 0) 1210 return; 1211 1212 /* 1213 * Remember the previous number of free descriptors. 1214 */ 1215 ofree = sc->sc_txfree; 1216 1217 /* 1218 * Loop through the send queue, setting up transmit descriptors 1219 * until we drain the queue, or use up all available transmit 1220 * descriptors. 1221 */ 1222 for (;;) { 1223 #ifdef EMAC_TAH 1224 txc = 0; 1225 tso_bytes = 0; 1226 tah_ssr = -1; 1227 tah_pending = false; 1228 1229 if ((m0 = sc->sc_txpending) != NULL) 1230 tah_pending = true; 1231 else 1232 #endif 1233 { 1234 /* Grab a packet off the queue. */ 1235 IFQ_POLL(&ifp->if_snd, m0); 1236 if (m0 == NULL) 1237 break; 1238 } 1239 1240 /* 1241 * Get a work queue entry. Reclaim used Tx descriptors if 1242 * we are running low. 1243 */ 1244 if (sc->sc_txsfree < EMAC_TXQUEUE_GC) { 1245 emac_txreap(sc); 1246 if (sc->sc_txsfree == 0) { 1247 EMAC_EVCNT_INCR(&sc->sc_ev_txsstall); 1248 break; 1249 } 1250 } 1251 1252 #ifdef EMAC_TAH 1253 /* 1254 * Decide what the TAH should do for this packet 1255 */ 1256 if (sc->sc_tah && m0->m_pkthdr.csum_flags != 0) { 1257 tah_cls = emac_tah_tx_classify(m0, &tso_bytes); 1258 1259 if (tah_cls == EMAC_TAHTX_TSO) { 1260 tah_ssr = emac_tso_ssr_claim(sc, tso_bytes); 1261 if (tah_ssr < 0) /* all slots busy */ 1262 tah_cls = EMAC_TAHTX_SW; 1263 } 1264 1265 switch (tah_cls) { 1266 case EMAC_TAHTX_TSO: 1267 txc = EMAC_TXC_HAC_SSR(tah_ssr); 1268 EMAC_EVCNT_INCR(&sc->sc_ev_txtso); 1269 break; 1270 1271 case EMAC_TAHTX_CSUM: 1272 txc = EMAC_TXC_HAC_CSUM; 1273 EMAC_EVCNT_INCR(&sc->sc_ev_txcsum); 1274 break; 1275 1276 case EMAC_TAHTX_SW: 1277 if (m0->m_pkthdr.csum_flags & 1278 (M_CSUM_TSOv4 | M_CSUM_TSOv6)) { 1279 /* Segment in software. */ 1280 IFQ_DEQUEUE(&ifp->if_snd, m0); 1281 if (emac_tso_sw_segment(sc, ifp, 1282 m0) != 0) 1283 if_statinc(ifp, if_oerrors); 1284 continue; 1285 } 1286 1287 /* Compute the checksums in software. */ 1288 { 1289 const int cf4 = 1290 m0->m_pkthdr.csum_flags & 1291 (M_CSUM_IPv4 | M_CSUM_TCPv4 | 1292 M_CSUM_UDPv4); 1293 #ifdef INET6 1294 const int cf6 = 1295 m0->m_pkthdr.csum_flags & 1296 (M_CSUM_TCPv6 | M_CSUM_UDPv6); 1297 #else 1298 const int cf6 = 0; 1299 #endif 1300 if (cf4 != 0) 1301 in_undefer_cksum(m0, 1302 ETHER_HDR_LEN, cf4); 1303 #ifdef INET6 1304 if (cf6 != 0) 1305 in6_undefer_cksum(m0, 1306 ETHER_HDR_LEN, cf6); 1307 #endif 1308 m0->m_pkthdr.csum_flags &= 1309 ~(cf4 | cf6); 1310 } 1311 break; 1312 } 1313 } 1314 #endif 1315 1316 txs = &sc->sc_txsoft[sc->sc_txsnext]; 1317 dmamap = txs->txs_dmamap; 1318 1319 /* 1320 * Load the DMA map. If this fails, the packet either 1321 * didn't fit in the allotted number of segments, or we 1322 * were short on resources. In this case, we'll copy 1323 * and try again. 1324 */ 1325 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1326 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1327 if (error) { 1328 if (error == EFBIG) { 1329 #ifdef EMAC_TAH 1330 if (tah_ssr >= 0) { 1331 /* 1332 * A TSO burst with too many 1333 * segments: segment it in 1334 * software instead of dropping. 1335 */ 1336 sc->sc_ssr_refs[tah_ssr]--; 1337 IFQ_DEQUEUE(&ifp->if_snd, m0); 1338 if (emac_tso_sw_segment(sc, ifp, 1339 m0) != 0) 1340 if_statinc(ifp, if_oerrors); 1341 continue; 1342 } 1343 #endif 1344 EMAC_EVCNT_INCR(&sc->sc_ev_txdrop); 1345 aprint_error_ifnet(ifp, 1346 "Tx packet consumes too many " 1347 "DMA segments, dropping...\n"); 1348 #ifdef EMAC_TAH 1349 if (tah_pending) { 1350 sc->sc_txpending = m0->m_nextpkt; 1351 m0->m_nextpkt = NULL; 1352 } else 1353 #endif 1354 IFQ_DEQUEUE(&ifp->if_snd, m0); 1355 m_freem(m0); 1356 continue; 1357 } 1358 /* Short on resources, just stop for now. */ 1359 #ifdef EMAC_TAH 1360 if (tah_ssr >= 0) 1361 sc->sc_ssr_refs[tah_ssr]--; 1362 #endif 1363 break; 1364 } 1365 1366 /* 1367 * Ensure we have enough descriptors free to describe 1368 * the packet. 1369 */ 1370 if (dmamap->dm_nsegs > sc->sc_txfree) { 1371 /* 1372 * Not enough free descriptors to transmit this 1373 * packet. We haven't committed anything yet, 1374 * so just unload the DMA map, put the packet 1375 * back on the queue, and punt. Notify the upper 1376 * layer that there are not more slots left. 1377 * 1378 */ 1379 bus_dmamap_unload(sc->sc_dmat, dmamap); 1380 EMAC_EVCNT_INCR(&sc->sc_ev_txdstall); 1381 #ifdef EMAC_TAH 1382 if (tah_ssr >= 0) 1383 sc->sc_ssr_refs[tah_ssr]--; 1384 #endif 1385 break; 1386 } 1387 1388 #ifdef EMAC_TAH 1389 if (tah_pending) { 1390 sc->sc_txpending = m0->m_nextpkt; 1391 m0->m_nextpkt = NULL; 1392 } else 1393 #endif 1394 IFQ_DEQUEUE(&ifp->if_snd, m0); 1395 1396 /* 1397 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1398 */ 1399 1400 /* Sync the DMA map. */ 1401 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1402 BUS_DMASYNC_PREWRITE); 1403 1404 /* 1405 * Store a pointer to the packet so that we can free it 1406 * later. 1407 */ 1408 txs->txs_mbuf = m0; 1409 txs->txs_firstdesc = sc->sc_txnext; 1410 txs->txs_ndesc = dmamap->dm_nsegs; 1411 #ifdef EMAC_TAH 1412 txs->txs_ssr = tah_ssr; 1413 if (tah_ssr >= 0) 1414 /* 1415 * Wire packets this burst produces; tso_bytes - 1416 * segsz is the IP + TCP header length. 1417 */ 1418 txs->txs_opackets = howmany(m0->m_pkthdr.len - 1419 ETHER_HDR_LEN - (tso_bytes - m0->m_pkthdr.segsz), 1420 m0->m_pkthdr.segsz); 1421 else 1422 txs->txs_opackets = 1; 1423 #endif 1424 1425 /* 1426 * Initialize the transmit descriptor. 1427 */ 1428 firsttx = sc->sc_txnext; 1429 for (nexttx = sc->sc_txnext, seg = 0; 1430 seg < dmamap->dm_nsegs; 1431 seg++, nexttx = EMAC_NEXTTX(nexttx)) { 1432 struct mal_descriptor *txdesc = 1433 &sc->sc_txdescs[nexttx]; 1434 1435 /* 1436 * If this is the first descriptor we're 1437 * enqueueing, don't set the TX_READY bit just 1438 * yet. That could cause a race condition. 1439 * We'll do it below. 1440 */ 1441 txdesc->md_data = dmamap->dm_segs[seg].ds_addr; 1442 txdesc->md_data_len = dmamap->dm_segs[seg].ds_len; 1443 txdesc->md_stat_ctrl = 1444 (txdesc->md_stat_ctrl & MAL_TX_WRAP) | 1445 (nexttx == firsttx ? 0 : MAL_TX_READY) | 1446 #ifdef EMAC_TAH 1447 txc | 1448 #endif 1449 EMAC_TXC_GFCS | EMAC_TXC_GPAD; 1450 lasttx = nexttx; 1451 } 1452 1453 /* Set the LAST bit on the last segment. */ 1454 sc->sc_txdescs[lasttx].md_stat_ctrl |= MAL_TX_LAST; 1455 1456 /* 1457 * Request a Tx-complete interrupt for this packet. 1458 */ 1459 sc->sc_txdescs[lasttx].md_stat_ctrl |= MAL_TX_INTERRUPT; 1460 1461 txs->txs_lastdesc = lasttx; 1462 1463 /* Sync the descriptors we're using. */ 1464 EMAC_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1465 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1466 1467 /* 1468 * The entire packet chain is set up. Give the 1469 * first descriptor to the chip now. 1470 */ 1471 sc->sc_txdescs[firsttx].md_stat_ctrl |= MAL_TX_READY; 1472 EMAC_CDTXSYNC(sc, firsttx, 1, 1473 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1474 /* 1475 * Tell the EMAC that a new packet is available. 1476 */ 1477 EMAC_WRITE(sc, EMAC_TMR0, TMR0_GNP0 | TMR0_TFAE_2); 1478 1479 /* Advance the tx pointer. */ 1480 sc->sc_txfree -= txs->txs_ndesc; 1481 sc->sc_txnext = nexttx; 1482 1483 sc->sc_txsfree--; 1484 sc->sc_txsnext = EMAC_NEXTTXS(sc->sc_txsnext); 1485 1486 /* 1487 * Pass the packet to any BPF listeners. 1488 */ 1489 bpf_mtap(ifp, m0, BPF_D_OUT); 1490 } 1491 1492 if (sc->sc_txfree != ofree) 1493 /* Set a watchdog timer in case the chip flakes out. */ 1494 ifp->if_timer = 5; 1495 } 1496 1497 static int 1498 emac_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1499 { 1500 struct emac_softc *sc = ifp->if_softc; 1501 int s, error; 1502 1503 s = splnet(); 1504 1505 switch (cmd) { 1506 case SIOCSIFMTU: 1507 { 1508 struct ifreq *ifr = (struct ifreq *)data; 1509 int maxmtu; 1510 1511 if (sc->sc_ethercom.ec_capabilities & ETHERCAP_JUMBO_MTU) 1512 maxmtu = EMAC_MAX_MTU; 1513 else 1514 maxmtu = ETHERMTU; 1515 1516 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > maxmtu) 1517 error = EINVAL; 1518 else if ((error = ifioctl_common(ifp, cmd, data)) != ENETRESET) 1519 break; 1520 else if (ifp->if_flags & IFF_UP) 1521 error = emac_init(ifp); 1522 else 1523 error = 0; 1524 break; 1525 } 1526 1527 default: 1528 error = ether_ioctl(ifp, cmd, data); 1529 if (error == ENETRESET) { 1530 #ifdef EMAC_TAH 1531 if (cmd == SIOCSIFCAP) { 1532 /* 1533 * Checksum offload changed, reinitialize 1534 */ 1535 if (ifp->if_flags & IFF_RUNNING) 1536 error = emac_init(ifp); 1537 else 1538 error = 0; 1539 break; 1540 } 1541 #endif 1542 /* 1543 * Multicast list has changed; set the hardware filter 1544 * accordingly. 1545 */ 1546 if (ifp->if_flags & IFF_RUNNING) 1547 error = emac_set_filter(sc); 1548 else 1549 error = 0; 1550 } 1551 } 1552 1553 /* try to get more packets going */ 1554 emac_start(ifp); 1555 1556 splx(s); 1557 return error; 1558 } 1559 1560 static int 1561 emac_init(struct ifnet *ifp) 1562 { 1563 struct emac_softc *sc = ifp->if_softc; 1564 struct emac_rxsoft *rxs; 1565 const uint8_t *enaddr = CLLADDR(ifp->if_sadl); 1566 int error, i; 1567 1568 error = 0; 1569 1570 /* Cancel any pending I/O. */ 1571 emac_stop(ifp, 0); 1572 1573 /* Reset the chip to a known state. */ 1574 emac_soft_reset(sc); 1575 1576 #ifdef EMAC_TAH 1577 /* 1578 * Re-establish a sane TAH config 1579 */ 1580 if (sc->sc_tah) { 1581 sc->sc_tah_cvr = (ifp->if_csum_flags_rx & 1582 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4 | 1583 M_CSUM_TCPv6 | M_CSUM_UDPv6)) != 0; 1584 emac_tah_reset(sc); 1585 } 1586 #endif 1587 1588 /* 1589 * Initialise the transmit descriptor ring. 1590 */ 1591 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1592 /* set wrap on last descriptor */ 1593 sc->sc_txdescs[EMAC_NTXDESC - 1].md_stat_ctrl |= MAL_TX_WRAP; 1594 EMAC_CDTXSYNC(sc, 0, EMAC_NTXDESC, 1595 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1596 sc->sc_txfree = EMAC_NTXDESC; 1597 sc->sc_txnext = 0; 1598 1599 /* 1600 * Initialise the transmit job descriptors. 1601 */ 1602 for (i = 0; i < EMAC_TXQUEUELEN; i++) 1603 sc->sc_txsoft[i].txs_mbuf = NULL; 1604 sc->sc_txsfree = EMAC_TXQUEUELEN; 1605 sc->sc_txsnext = 0; 1606 sc->sc_txsdirty = 0; 1607 1608 /* 1609 * Initialise the receiver descriptor and receive job 1610 * descriptor rings. 1611 */ 1612 for (i = 0; i < EMAC_NRXDESC; i++) { 1613 rxs = &sc->sc_rxsoft[i]; 1614 if (rxs->rxs_mbuf == NULL) { 1615 if ((error = emac_add_rxbuf(sc, i)) != 0) { 1616 aprint_error_ifnet(ifp, 1617 "unable to allocate or map rx buffer %d," 1618 " error = %d\n", 1619 i, error); 1620 /* 1621 * XXX Should attempt to run with fewer receive 1622 * XXX buffers instead of just failing. 1623 */ 1624 emac_rxdrain(sc); 1625 goto out; 1626 } 1627 } else 1628 EMAC_INIT_RXDESC(sc, i); 1629 } 1630 sc->sc_rxptr = 0; 1631 1632 /* 1633 * Set the current media. 1634 */ 1635 if ((error = ether_mediachange(ifp)) != 0) 1636 goto out; 1637 1638 /* 1639 * Load the MAC address. 1640 */ 1641 EMAC_WRITE(sc, EMAC_IAHR, enaddr[0] << 8 | enaddr[1]); 1642 EMAC_WRITE(sc, EMAC_IALR, 1643 enaddr[2] << 24 | enaddr[3] << 16 | enaddr[4] << 8 | enaddr[5]); 1644 1645 /* Enable the transmit and receive channel on the MAL. */ 1646 error = mal_start(sc->sc_instance, 1647 EMAC_CDTXADDR(sc, 0), EMAC_CDRXADDR(sc, 0)); 1648 if (error) 1649 goto out; 1650 1651 sc->sc_mr1 &= ~MR1_JPSM; 1652 if (ifp->if_mtu > ETHERMTU) 1653 /* Enable Jumbo Packet Support Mode */ 1654 sc->sc_mr1 |= MR1_JPSM; 1655 1656 /* Set fifos, media modes. */ 1657 EMAC_WRITE(sc, EMAC_MR1, sc->sc_mr1); 1658 1659 /* 1660 * Enable Individual and (possibly) Broadcast Address modes, 1661 * runt packets, and strip padding. 1662 */ 1663 EMAC_WRITE(sc, EMAC_RMR, RMR_IAE | RMR_RRP | RMR_SP | RMR_TFAE_2 | 1664 (ifp->if_flags & IFF_PROMISC ? RMR_PME : 0) | 1665 (ifp->if_flags & IFF_BROADCAST ? RMR_BAE : 0)); 1666 1667 /* 1668 * Set multicast filter. 1669 */ 1670 emac_set_filter(sc); 1671 1672 /* 1673 * Set low- and urgent-priority request thresholds. 1674 */ 1675 EMAC_WRITE(sc, EMAC_TMR1, 1676 ((7 << TMR1_TLR_SHIFT) & TMR1_TLR_MASK) | /* 16 word burst */ 1677 ((15 << TMR1_TUR_SHIFT) & TMR1_TUR_MASK)); 1678 /* 1679 * Set Transmit Request Threshold Register. 1680 */ 1681 EMAC_WRITE(sc, EMAC_TRTR, TRTR_256); 1682 1683 /* 1684 * Set high and low receive watermarks. 1685 */ 1686 #ifdef EMAC_TAH 1687 /* 1688 * the fix probably is OK for all EMACs 1689 */ 1690 EMAC_WRITE(sc, EMAC_RWMR, 1691 30 << RWMR_RLWM_SHIFT | 64 << RWMR_RHWM_SHIFT); 1692 #else 1693 EMAC_WRITE(sc, EMAC_RWMR, 1694 30 << RWMR_RLWM_SHIFT | 64 << RWMR_RLWM_SHIFT); 1695 #endif 1696 1697 /* 1698 * Set frame gap. 1699 */ 1700 EMAC_WRITE(sc, EMAC_IPGVR, 8); 1701 1702 /* 1703 * Set interrupt status enable bits for EMAC. 1704 */ 1705 EMAC_WRITE(sc, EMAC_ISER, 1706 ISR_TXPE | /* TX Parity Error */ 1707 ISR_RXPE | /* RX Parity Error */ 1708 ISR_TXUE | /* TX Underrun Event */ 1709 #ifndef EMAC_TAH 1710 /* 1711 * With the TAH in the RX path, RXOE latches on most 1712 * received packets without any actual packet loss 1713 */ 1714 ISR_RXOE | /* RX Overrun Event */ 1715 #endif 1716 ISR_OVR | /* Overrun Error */ 1717 ISR_PP | /* Pause Packet */ 1718 ISR_BP | /* Bad Packet */ 1719 ISR_RP | /* Runt Packet */ 1720 ISR_SE | /* Short Event */ 1721 ISR_ALE | /* Alignment Error */ 1722 ISR_BFCS | /* Bad FCS */ 1723 ISR_PTLE | /* Packet Too Long Error */ 1724 ISR_ORE | /* Out of Range Error */ 1725 ISR_IRE | /* In Range Error */ 1726 ISR_SE0 | /* Signal Quality Error 0 (SQE) */ 1727 ISR_TE0 | /* Transmit Error 0 */ 1728 ISR_MOS | /* MMA Operation Succeeded */ 1729 ISR_MOF); /* MMA Operation Failed */ 1730 1731 /* 1732 * Enable the transmit and receive channel on the EMAC. 1733 */ 1734 EMAC_WRITE(sc, EMAC_MR0, MR0_TXE | MR0_RXE); 1735 1736 /* 1737 * Start the one second MII clock. 1738 */ 1739 callout_reset(&sc->sc_callout, hz, emac_mii_tick, sc); 1740 1741 /* 1742 * ... all done! 1743 */ 1744 ifp->if_flags |= IFF_RUNNING; 1745 1746 out: 1747 if (error) { 1748 ifp->if_flags &= ~IFF_RUNNING; 1749 ifp->if_timer = 0; 1750 aprint_error_ifnet(ifp, "interface not running\n"); 1751 } 1752 return error; 1753 } 1754 1755 static void 1756 emac_stop(struct ifnet *ifp, int disable) 1757 { 1758 struct emac_softc *sc = ifp->if_softc; 1759 struct emac_txsoft *txs; 1760 int i; 1761 1762 /* Stop the one second clock. */ 1763 callout_stop(&sc->sc_callout); 1764 1765 /* Down the MII */ 1766 mii_down(&sc->sc_mii); 1767 1768 /* Disable interrupts. */ 1769 EMAC_WRITE(sc, EMAC_ISER, 0); 1770 1771 /* Disable the receive and transmit channels. */ 1772 mal_stop(sc->sc_instance); 1773 1774 /* Disable the transmit enable and receive MACs. */ 1775 EMAC_WRITE(sc, EMAC_MR0, 1776 EMAC_READ(sc, EMAC_MR0) & ~(MR0_TXE | MR0_RXE)); 1777 1778 /* Release any queued transmit buffers. */ 1779 for (i = 0; i < EMAC_TXQUEUELEN; i++) { 1780 txs = &sc->sc_txsoft[i]; 1781 if (txs->txs_mbuf != NULL) { 1782 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1783 m_freem(txs->txs_mbuf); 1784 txs->txs_mbuf = NULL; 1785 #ifdef EMAC_TAH 1786 emac_tso_ssr_release(sc, txs); 1787 #endif 1788 } 1789 } 1790 1791 #ifdef EMAC_TAH 1792 /* Free any software-segmented packets awaiting transmission. */ 1793 while (sc->sc_txpending != NULL) { 1794 struct mbuf *m = sc->sc_txpending; 1795 1796 sc->sc_txpending = m->m_nextpkt; 1797 m->m_nextpkt = NULL; 1798 m_freem(m); 1799 } 1800 #endif 1801 1802 if (disable) 1803 emac_rxdrain(sc); 1804 1805 /* 1806 * Mark the interface down and cancel the watchdog timer. 1807 */ 1808 ifp->if_flags &= ~IFF_RUNNING; 1809 ifp->if_timer = 0; 1810 } 1811 1812 static void 1813 emac_watchdog(struct ifnet *ifp) 1814 { 1815 struct emac_softc *sc = ifp->if_softc; 1816 1817 /* 1818 * Since we're not interrupting every packet, sweep 1819 * up before we report an error. 1820 */ 1821 emac_txreap(sc); 1822 1823 if (sc->sc_txfree != EMAC_NTXDESC) { 1824 aprint_error_ifnet(ifp, 1825 "device timeout (txfree %d txsfree %d txnext %d)\n", 1826 sc->sc_txfree, sc->sc_txsfree, sc->sc_txnext); 1827 if_statinc(ifp, if_oerrors); 1828 1829 /* Reset the interface. */ 1830 (void)emac_init(ifp); 1831 } else if (ifp->if_flags & IFF_DEBUG) 1832 aprint_error_ifnet(ifp, "recovered from device timeout\n"); 1833 1834 /* try to get more packets going */ 1835 emac_start(ifp); 1836 } 1837 1838 static int 1839 emac_add_rxbuf(struct emac_softc *sc, int idx) 1840 { 1841 struct emac_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1842 struct mbuf *m; 1843 int error; 1844 1845 MGETHDR(m, M_DONTWAIT, MT_DATA); 1846 if (m == NULL) 1847 return ENOBUFS; 1848 1849 MCLGET(m, M_DONTWAIT); 1850 if ((m->m_flags & M_EXT) == 0) { 1851 m_freem(m); 1852 return ENOBUFS; 1853 } 1854 1855 if (rxs->rxs_mbuf != NULL) 1856 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1857 1858 rxs->rxs_mbuf = m; 1859 1860 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1861 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1862 if (error) { 1863 aprint_error_dev(sc->sc_dev, 1864 "can't load rx DMA map %d, error = %d\n", idx, error); 1865 panic("emac_add_rxbuf"); /* XXX */ 1866 } 1867 1868 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1869 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1870 1871 EMAC_INIT_RXDESC(sc, idx); 1872 1873 return 0; 1874 } 1875 1876 static void 1877 emac_rxdrain(struct emac_softc *sc) 1878 { 1879 struct emac_rxsoft *rxs; 1880 int i; 1881 1882 for (i = 0; i < EMAC_NRXDESC; i++) { 1883 rxs = &sc->sc_rxsoft[i]; 1884 if (rxs->rxs_mbuf != NULL) { 1885 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1886 m_freem(rxs->rxs_mbuf); 1887 rxs->rxs_mbuf = NULL; 1888 } 1889 } 1890 } 1891 1892 static int 1893 emac_set_filter(struct emac_softc *sc) 1894 { 1895 struct ethercom *ec = &sc->sc_ethercom; 1896 struct ether_multistep step; 1897 struct ether_multi *enm; 1898 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1899 uint32_t rmr, crc, mask, tmp, reg, gaht[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 1900 int regs, cnt = 0, i; 1901 1902 if (sc->sc_htsize == 256) { 1903 reg = EMAC_GAHT256(0); 1904 regs = 8; 1905 } else { 1906 reg = EMAC_GAHT64(0); 1907 regs = 4; 1908 } 1909 mask = (1ULL << (sc->sc_htsize / regs)) - 1; 1910 1911 rmr = EMAC_READ(sc, EMAC_RMR); 1912 rmr &= ~(RMR_PMME | RMR_MAE); 1913 ifp->if_flags &= ~IFF_ALLMULTI; 1914 1915 ETHER_LOCK(ec); 1916 ETHER_FIRST_MULTI(step, ec, enm); 1917 while (enm != NULL) { 1918 if (memcmp(enm->enm_addrlo, 1919 enm->enm_addrhi, ETHER_ADDR_LEN) != 0) { 1920 /* 1921 * We must listen to a range of multicast addresses. 1922 * For now, just accept all multicasts, rather than 1923 * trying to set only those filter bits needed to match 1924 * the range. (At this time, the only use of address 1925 * ranges is for IP multicast routing, for which the 1926 * range is big enough to require all bits set.) 1927 */ 1928 gaht[0] = gaht[1] = gaht[2] = gaht[3] = 1929 gaht[4] = gaht[5] = gaht[6] = gaht[7] = mask; 1930 break; 1931 } 1932 1933 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1934 1935 if (sc->sc_htsize == 256) 1936 EMAC_SET_FILTER256(gaht, crc); 1937 else 1938 EMAC_SET_FILTER(gaht, crc); 1939 1940 ETHER_NEXT_MULTI(step, enm); 1941 cnt++; 1942 } 1943 ETHER_UNLOCK(ec); 1944 1945 for (i = 1, tmp = gaht[0]; i < regs; i++) 1946 tmp &= gaht[i]; 1947 if (tmp == mask) { 1948 /* All categories are true. */ 1949 ifp->if_flags |= IFF_ALLMULTI; 1950 rmr |= RMR_PMME; 1951 } else if (cnt != 0) { 1952 /* Some categories are true. */ 1953 for (i = 0; i < regs; i++) 1954 EMAC_WRITE(sc, reg + (i << 2), gaht[i]); 1955 rmr |= RMR_MAE; 1956 } 1957 EMAC_WRITE(sc, EMAC_RMR, rmr); 1958 1959 return 0; 1960 } 1961 1962 /* 1963 * Reap completed Tx descriptors. 1964 */ 1965 static int 1966 emac_txreap(struct emac_softc *sc) 1967 { 1968 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1969 struct emac_txsoft *txs; 1970 int handled, i; 1971 uint32_t txstat, count; 1972 1973 EMAC_EVCNT_INCR(&sc->sc_ev_txreap); 1974 handled = 0; 1975 1976 count = 0; 1977 /* 1978 * Go through our Tx list and free mbufs for those 1979 * frames that have been transmitted. 1980 */ 1981 for (i = sc->sc_txsdirty; sc->sc_txsfree != EMAC_TXQUEUELEN; 1982 i = EMAC_NEXTTXS(i), sc->sc_txsfree++) { 1983 txs = &sc->sc_txsoft[i]; 1984 1985 EMAC_CDTXSYNC(sc, txs->txs_lastdesc, 1986 txs->txs_dmamap->dm_nsegs, 1987 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1988 1989 txstat = sc->sc_txdescs[txs->txs_lastdesc].md_stat_ctrl; 1990 if (txstat & MAL_TX_READY) 1991 break; 1992 1993 handled = 1; 1994 1995 #ifdef EMAC_TAH 1996 /* The TAH is done with this job's segment size slot. */ 1997 emac_tso_ssr_release(sc, txs); 1998 #endif 1999 2000 /* 2001 * Check for errors and collisions. 2002 */ 2003 if (txstat & (EMAC_TXS_UR | EMAC_TXS_ED)) 2004 if_statinc(ifp, if_oerrors); 2005 2006 #ifdef EMAC_EVENT_COUNTERS 2007 if (txstat & EMAC_TXS_UR) 2008 EMAC_EVCNT_INCR(&sc->sc_ev_tu); 2009 #endif /* EMAC_EVENT_COUNTERS */ 2010 2011 #ifdef EMAC_TAH 2012 /* 2013 * On TAH channels EMAC_TXS_TED (which overlays 2014 * EMAC_TXS_BPP) means the TAH aborted the packet 2015 */ 2016 if (sc->sc_tah && (txstat & EMAC_TXS_TED)) { 2017 uint32_t tsr = TAH_READ(sc, TAH_TSR); 2018 2019 EMAC_EVCNT_INCR(&sc->sc_ev_tahted); 2020 if_statinc(ifp, if_oerrors); 2021 if (ifp->if_flags & IFF_DEBUG) 2022 aprint_error_ifnet(ifp, 2023 "TAH transmit error, TSR = 0x%08x\n", tsr); 2024 } 2025 #endif 2026 2027 if (txstat & 2028 (EMAC_TXS_EC | EMAC_TXS_MC | EMAC_TXS_SC | EMAC_TXS_LC)) { 2029 if (txstat & EMAC_TXS_EC) 2030 if_statadd(ifp, if_collisions, 16); 2031 else if (txstat & EMAC_TXS_MC) 2032 if_statadd(ifp, if_collisions, 2); /* XXX? */ 2033 else if (txstat & EMAC_TXS_SC) 2034 if_statinc(ifp, if_collisions); 2035 if (txstat & EMAC_TXS_LC) 2036 if_statinc(ifp, if_collisions); 2037 } else { 2038 #ifdef EMAC_TAH 2039 /* a TSO burst produces several wire packets */ 2040 if_statadd(ifp, if_opackets, txs->txs_opackets); 2041 #else 2042 if_statinc(ifp, if_opackets); 2043 #endif 2044 } 2045 2046 if (ifp->if_flags & IFF_DEBUG) { 2047 if (txstat & EMAC_TXS_ED) 2048 aprint_error_ifnet(ifp, "excessive deferral\n"); 2049 if (txstat & EMAC_TXS_EC) 2050 aprint_error_ifnet(ifp, 2051 "excessive collisions\n"); 2052 } 2053 2054 sc->sc_txfree += txs->txs_ndesc; 2055 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 2056 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2057 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2058 m_freem(txs->txs_mbuf); 2059 txs->txs_mbuf = NULL; 2060 2061 count++; 2062 } 2063 2064 /* Update the dirty transmit buffer pointer. */ 2065 sc->sc_txsdirty = i; 2066 2067 /* 2068 * If there are no more pending transmissions, cancel the watchdog 2069 * timer. 2070 */ 2071 if (sc->sc_txsfree == EMAC_TXQUEUELEN) 2072 ifp->if_timer = 0; 2073 2074 if (count != 0) 2075 rnd_add_uint32(&sc->rnd_source, count); 2076 2077 return handled; 2078 } 2079 2080 2081 /* 2082 * Reset functions 2083 */ 2084 2085 static void 2086 emac_soft_reset(struct emac_softc *sc) 2087 { 2088 uint32_t sdr; 2089 int t = 0; 2090 2091 /* 2092 * The PHY must provide a TX Clk in order perform a soft reset the 2093 * EMAC. If none is present, select the internal clock, 2094 * SDR0_MFR[E0CS, E1CS]. After the soft reset, select the external 2095 * clock. 2096 */ 2097 2098 if (sc->sc_ethcfg_ecs) { 2099 sdr = mfsdr(DCR_SDR0_ETH_CFG); 2100 sdr |= SDR0_ETH_CFG_ECS(sc->sc_instance); 2101 mtsdr(DCR_SDR0_ETH_CFG, sdr); 2102 } else { 2103 sdr = mfsdr(DCR_SDR0_MFR); 2104 sdr |= SDR0_MFR_ECS(sc->sc_instance); 2105 mtsdr(DCR_SDR0_MFR, sdr); 2106 } 2107 2108 EMAC_WRITE(sc, EMAC_MR0, MR0_SRST); 2109 2110 if (sc->sc_ethcfg_ecs) { 2111 sdr = mfsdr(DCR_SDR0_ETH_CFG); 2112 sdr &= ~SDR0_ETH_CFG_ECS(sc->sc_instance); 2113 mtsdr(DCR_SDR0_ETH_CFG, sdr); 2114 } else { 2115 sdr = mfsdr(DCR_SDR0_MFR); 2116 sdr &= ~SDR0_MFR_ECS(sc->sc_instance); 2117 mtsdr(DCR_SDR0_MFR, sdr); 2118 } 2119 2120 delay(5); 2121 2122 /* wait finish */ 2123 while (EMAC_READ(sc, EMAC_MR0) & MR0_SRST) { 2124 if (++t == 1000000 /* 1sec XXXXX */) { 2125 aprint_error_dev(sc->sc_dev, "Soft Reset failed\n"); 2126 return; 2127 } 2128 delay(1); 2129 } 2130 } 2131 2132 static void 2133 emac_smart_reset(struct emac_softc *sc) 2134 { 2135 uint32_t mr0; 2136 int t = 0; 2137 2138 mr0 = EMAC_READ(sc, EMAC_MR0); 2139 if (mr0 & (MR0_TXE | MR0_RXE)) { 2140 mr0 &= ~(MR0_TXE | MR0_RXE); 2141 EMAC_WRITE(sc, EMAC_MR0, mr0); 2142 2143 /* wait idel state */ 2144 while ((EMAC_READ(sc, EMAC_MR0) & (MR0_TXI | MR0_RXI)) != 2145 (MR0_TXI | MR0_RXI)) { 2146 if (++t == 1000000 /* 1sec XXXXX */) { 2147 aprint_error_dev(sc->sc_dev, 2148 "Smart Reset failed\n"); 2149 return; 2150 } 2151 delay(1); 2152 } 2153 } 2154 } 2155 2156 #ifdef EMAC_TAH 2157 static void 2158 emac_tah_reset(struct emac_softc *sc) 2159 { 2160 int t = 0; 2161 2162 TAH_WRITE(sc, TAH_MR, TAH_MR_SR); 2163 2164 while (TAH_READ(sc, TAH_MR) & TAH_MR_SR) { 2165 if (++t == 1000000 /* 1sec XXXXX */) { 2166 aprint_error_dev(sc->sc_dev, 2167 "TAH Soft Reset failed\n"); 2168 return; 2169 } 2170 delay(1); 2171 } 2172 2173 TAH_WRITE(sc, TAH_MR, 2174 TAH_MR_ST(768 / 256) | TAH_MR_TFS_10K | TAH_MR_DTFP | 2175 TAH_MR_DIG | TAH_MR_IPV6 | 2176 (sc->sc_tah_cvr ? TAH_MR_CVR : 0)); 2177 2178 memset(sc->sc_ssr_bytes, 0, sizeof(sc->sc_ssr_bytes)); 2179 memset(sc->sc_ssr_refs, 0, sizeof(sc->sc_ssr_refs)); 2180 } 2181 #endif /* EMAC_TAH */ 2182 2183 2184 /* 2185 * MII related functions 2186 */ 2187 2188 static int 2189 emac_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 2190 { 2191 struct emac_softc *sc = device_private(self); 2192 uint32_t sta_reg; 2193 int rv; 2194 2195 if (sc->sc_rmii_enable) 2196 sc->sc_rmii_enable(device_parent(self), sc->sc_instance); 2197 2198 /* wait for PHY data transfer to complete */ 2199 if ((rv = emac_mii_wait(sc)) != 0) 2200 goto fail; 2201 2202 sta_reg = 2203 sc->sc_stacr_read | 2204 (reg << STACR_PRA_SHIFT) | 2205 (phy << STACR_PCDA_SHIFT) | 2206 sc->sc_stacr_bits; 2207 EMAC_WRITE(sc, EMAC_STACR, sta_reg); 2208 2209 if ((rv = emac_mii_wait(sc)) != 0) 2210 goto fail; 2211 sta_reg = EMAC_READ(sc, EMAC_STACR); 2212 2213 if (sta_reg & STACR_PHYE) { 2214 rv = -1; 2215 goto fail; 2216 } 2217 *val = sta_reg >> STACR_PHYD_SHIFT; 2218 2219 fail: 2220 if (sc->sc_rmii_disable) 2221 sc->sc_rmii_disable(device_parent(self), sc->sc_instance); 2222 return rv; 2223 } 2224 2225 static int 2226 emac_mii_writereg(device_t self, int phy, int reg, uint16_t val) 2227 { 2228 struct emac_softc *sc = device_private(self); 2229 uint32_t sta_reg; 2230 int rv; 2231 2232 if (sc->sc_rmii_enable) 2233 sc->sc_rmii_enable(device_parent(self), sc->sc_instance); 2234 2235 /* wait for PHY data transfer to complete */ 2236 if ((rv = emac_mii_wait(sc)) != 0) 2237 goto out; 2238 2239 sta_reg = 2240 (val << STACR_PHYD_SHIFT) | 2241 sc->sc_stacr_write | 2242 (reg << STACR_PRA_SHIFT) | 2243 (phy << STACR_PCDA_SHIFT) | 2244 sc->sc_stacr_bits; 2245 EMAC_WRITE(sc, EMAC_STACR, sta_reg); 2246 2247 if ((rv = emac_mii_wait(sc)) != 0) 2248 goto out; 2249 if (EMAC_READ(sc, EMAC_STACR) & STACR_PHYE) { 2250 aprint_error_dev(sc->sc_dev, "MII PHY Error\n"); 2251 rv = -1; 2252 } 2253 2254 out: 2255 if (sc->sc_rmii_disable) 2256 sc->sc_rmii_disable(device_parent(self), sc->sc_instance); 2257 2258 return rv; 2259 } 2260 2261 static void 2262 emac_mii_statchg(struct ifnet *ifp) 2263 { 2264 struct emac_softc *sc = ifp->if_softc; 2265 struct mii_data *mii = &sc->sc_mii; 2266 2267 /* 2268 * MR1 can only be written immediately after a reset... 2269 */ 2270 emac_smart_reset(sc); 2271 2272 sc->sc_mr1 &= ~(MR1_FDE | MR1_ILE | MR1_EIFC | MR1_MF_MASK | MR1_IST); 2273 if (mii->mii_media_active & IFM_FDX) 2274 sc->sc_mr1 |= (MR1_FDE | MR1_EIFC | MR1_IST); 2275 if (mii->mii_media_active & IFM_FLOW) 2276 sc->sc_mr1 |= MR1_EIFC; 2277 if (mii->mii_media_active & IFM_LOOP) 2278 sc->sc_mr1 |= MR1_ILE; 2279 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2280 case IFM_1000_T: 2281 sc->sc_mr1 |= (MR1_MF_1000MBS | MR1_IST); 2282 break; 2283 2284 case IFM_100_TX: 2285 sc->sc_mr1 |= (MR1_MF_100MBS | MR1_IST); 2286 break; 2287 2288 case IFM_10_T: 2289 sc->sc_mr1 |= MR1_MF_10MBS; 2290 break; 2291 2292 case IFM_NONE: 2293 break; 2294 2295 default: 2296 aprint_error_dev(sc->sc_dev, "unknown sub-type %d\n", 2297 IFM_SUBTYPE(mii->mii_media_active)); 2298 break; 2299 } 2300 if (sc->sc_rmii_speed) 2301 sc->sc_rmii_speed(device_parent(sc->sc_dev), sc->sc_instance, 2302 IFM_SUBTYPE(mii->mii_media_active)); 2303 2304 EMAC_WRITE(sc, EMAC_MR1, sc->sc_mr1); 2305 2306 /* Enable TX and RX if already RUNNING */ 2307 if (ifp->if_flags & IFF_RUNNING) 2308 EMAC_WRITE(sc, EMAC_MR0, MR0_TXE | MR0_RXE); 2309 } 2310 2311 static uint32_t 2312 emac_mii_wait(struct emac_softc *sc) 2313 { 2314 int i; 2315 uint32_t oc; 2316 2317 /* wait for PHY data transfer to complete */ 2318 i = 0; 2319 oc = EMAC_READ(sc, EMAC_STACR) & STACR_OC; 2320 while ((oc == STACR_OC) != sc->sc_stacr_completed) { 2321 delay(7); 2322 if (i++ > 5) { 2323 aprint_error_dev(sc->sc_dev, "MII timed out\n"); 2324 return ETIMEDOUT; 2325 } 2326 oc = EMAC_READ(sc, EMAC_STACR) & STACR_OC; 2327 } 2328 return 0; 2329 } 2330 2331 static void 2332 emac_mii_tick(void *arg) 2333 { 2334 struct emac_softc *sc = arg; 2335 int s; 2336 2337 if (!device_is_active(sc->sc_dev)) 2338 return; 2339 2340 s = splnet(); 2341 mii_tick(&sc->sc_mii); 2342 splx(s); 2343 2344 callout_reset(&sc->sc_callout, hz, emac_mii_tick, sc); 2345 } 2346 2347 int 2348 emac_txeob_intr(void *arg) 2349 { 2350 struct emac_softc *sc = arg; 2351 int handled = 0; 2352 2353 EMAC_EVCNT_INCR(&sc->sc_ev_txintr); 2354 handled |= emac_txreap(sc); 2355 2356 /* try to get more packets going */ 2357 if_schedule_deferred_start(&sc->sc_ethercom.ec_if); 2358 2359 return handled; 2360 } 2361 2362 int 2363 emac_rxeob_intr(void *arg) 2364 { 2365 struct emac_softc *sc = arg; 2366 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2367 struct emac_rxsoft *rxs; 2368 struct mbuf *m; 2369 uint32_t rxstat, count; 2370 int i, len; 2371 #ifdef EMAC_TAH 2372 bool csum_bad; 2373 #endif 2374 2375 EMAC_EVCNT_INCR(&sc->sc_ev_rxintr); 2376 2377 count = 0; 2378 for (i = sc->sc_rxptr; ; i = EMAC_NEXTRX(i)) { 2379 rxs = &sc->sc_rxsoft[i]; 2380 2381 EMAC_CDRXSYNC(sc, i, 2382 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2383 2384 rxstat = sc->sc_rxdescs[i].md_stat_ctrl; 2385 2386 if (rxstat & MAL_RX_EMPTY) { 2387 /* 2388 * We have processed all of the receive buffers. 2389 */ 2390 /* Flush current empty descriptor */ 2391 EMAC_CDRXSYNC(sc, i, 2392 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2393 break; 2394 } 2395 2396 #ifdef EMAC_TAH 2397 csum_bad = false; 2398 if (sc->sc_tah_cvr && 2399 (rxstat & EMAC_RXS_CSUM_MASK) == EMAC_RXS_CSUM_BAD) { 2400 rxstat &= ~EMAC_RXS_CSUM_MASK; 2401 csum_bad = true; 2402 } 2403 #endif 2404 2405 /* 2406 * If an error occurred, update stats, clear the status 2407 * word, and leave the packet buffer in place. It will 2408 * simply be reused the next time the ring comes around. 2409 */ 2410 if (rxstat & (EMAC_RXS_OE | EMAC_RXS_BP | EMAC_RXS_SE | 2411 EMAC_RXS_AE | EMAC_RXS_BFCS | EMAC_RXS_PTL | EMAC_RXS_ORE | 2412 EMAC_RXS_IRE)) { 2413 #define PRINTERR(bit, str) \ 2414 if (rxstat & (bit)) \ 2415 aprint_error_ifnet(ifp, \ 2416 "receive error: %s\n", str) 2417 if_statinc(ifp, if_ierrors); 2418 PRINTERR(EMAC_RXS_OE, "overrun error"); 2419 PRINTERR(EMAC_RXS_BP, "bad packet"); 2420 PRINTERR(EMAC_RXS_RP, "runt packet"); 2421 PRINTERR(EMAC_RXS_SE, "short event"); 2422 PRINTERR(EMAC_RXS_AE, "alignment error"); 2423 PRINTERR(EMAC_RXS_BFCS, "bad FCS"); 2424 PRINTERR(EMAC_RXS_PTL, "packet too long"); 2425 PRINTERR(EMAC_RXS_ORE, "out of range error"); 2426 PRINTERR(EMAC_RXS_IRE, "in range error"); 2427 #undef PRINTERR 2428 EMAC_INIT_RXDESC(sc, i); 2429 continue; 2430 } 2431 2432 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2433 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2434 2435 /* 2436 * No errors; receive the packet. Note, the 405GP emac 2437 * includes the CRC with every packet. 2438 */ 2439 len = sc->sc_rxdescs[i].md_data_len - ETHER_CRC_LEN; 2440 2441 /* 2442 * If the packet is small enough to fit in a 2443 * single header mbuf, allocate one and copy 2444 * the data into it. This greatly reduces 2445 * memory consumption when we receive lots 2446 * of small packets. 2447 * 2448 * Otherwise, we add a new buffer to the receive 2449 * chain. If this fails, we drop the packet and 2450 * recycle the old buffer. 2451 */ 2452 if (emac_copy_small != 0 && len <= MHLEN) { 2453 MGETHDR(m, M_DONTWAIT, MT_DATA); 2454 if (m == NULL) 2455 goto dropit; 2456 memcpy(mtod(m, void *), 2457 mtod(rxs->rxs_mbuf, void *), len); 2458 EMAC_INIT_RXDESC(sc, i); 2459 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2460 rxs->rxs_dmamap->dm_mapsize, 2461 BUS_DMASYNC_PREREAD); 2462 } else { 2463 m = rxs->rxs_mbuf; 2464 if (emac_add_rxbuf(sc, i) != 0) { 2465 dropit: 2466 if_statinc(ifp, if_ierrors); 2467 EMAC_INIT_RXDESC(sc, i); 2468 bus_dmamap_sync(sc->sc_dmat, 2469 rxs->rxs_dmamap, 0, 2470 rxs->rxs_dmamap->dm_mapsize, 2471 BUS_DMASYNC_PREREAD); 2472 continue; 2473 } 2474 } 2475 2476 m_set_rcvif(m, ifp); 2477 m->m_pkthdr.len = m->m_len = len; 2478 2479 #ifdef EMAC_TAH 2480 if (sc->sc_tah_cvr) 2481 emac_rx_csum(sc, m, csum_bad); 2482 #endif 2483 2484 /* Pass it on. */ 2485 if_percpuq_enqueue(ifp->if_percpuq, m); 2486 2487 count++; 2488 } 2489 2490 /* Update the receive pointer. */ 2491 sc->sc_rxptr = i; 2492 2493 if (count != 0) 2494 rnd_add_uint32(&sc->rnd_source, count); 2495 2496 return 1; 2497 } 2498 2499 int 2500 emac_txde_intr(void *arg) 2501 { 2502 struct emac_softc *sc = arg; 2503 2504 EMAC_EVCNT_INCR(&sc->sc_ev_txde); 2505 aprint_error_dev(sc->sc_dev, "emac_txde_intr\n"); 2506 return 1; 2507 } 2508 2509 int 2510 emac_rxde_intr(void *arg) 2511 { 2512 struct emac_softc *sc = arg; 2513 int i; 2514 2515 EMAC_EVCNT_INCR(&sc->sc_ev_rxde); 2516 aprint_error_dev(sc->sc_dev, "emac_rxde_intr\n"); 2517 /* 2518 * XXX! 2519 * This is a bit drastic; we just drop all descriptors that aren't 2520 * "clean". We should probably send any that are up the stack. 2521 */ 2522 for (i = 0; i < EMAC_NRXDESC; i++) { 2523 EMAC_CDRXSYNC(sc, i, 2524 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2525 2526 if (sc->sc_rxdescs[i].md_data_len != MCLBYTES) 2527 EMAC_INIT_RXDESC(sc, i); 2528 } 2529 2530 return 1; 2531 } 2532
Indexes created Sun Oct 25 00:26:45 UTC 2026