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  /xsrc/external/mit/MesaLib/dist/src/panfrost/midgard/
midgard_ops.h 35 #define OP_IS_ATOMIC(op) (load_store_opcode_props[op].props & LDST_ATOMIC)
36 #define OP_USES_ATTRIB(op) (load_store_opcode_props[op].props & LDST_ATTRIB)
37 #define OP_IS_STORE(op) (load_store_opcode_props[op].props & LDST_STORE)
38 #define OP_HAS_ADDRESS(op) (load_store_opcode_props[op].props & LDST_ADDRESS)
44 midgard_is_integer_op(int op)
46 return (op >= 0x40 && op <= 0x7E) || (op >= 0xA0 && op <= 0xC1)
    [all...]
helpers.h 30 #define OP_IS_LOAD_VARY_F(op) (\
31 op == midgard_op_ld_vary_16 || \
32 op == midgard_op_ld_vary_32 \
35 #define OP_IS_PROJECTION(op) ( \
36 op == midgard_op_ldst_perspective_div_y || \
37 op == midgard_op_ldst_perspective_div_z || \
38 op == midgard_op_ldst_perspective_div_w \
41 #define OP_IS_VEC4_ONLY(op) ( \
42 OP_IS_PROJECTION(op) || \
43 op == midgard_op_ld_cubemap_coords
    [all...]
  /xsrc/external/mit/MesaLib/src/compiler/glsl/
ir_expression_operation_constant.h 3 for (unsigned c = 0; c < op[0]->type->components(); c++) {
4 switch (op[0]->type->base_type) {
6 data.u[c] = ~ op[0]->value.u[c];
9 data.i[c] = ~ op[0]->value.i[c];
12 data.u64[c] = ~ op[0]->value.u64[c];
15 data.i64[c] = ~ op[0]->value.i64[c];
24 for (unsigned c = 0; c < op[0]->type->components(); c++) {
25 switch (op[0]->type->base_type) {
27 data.b[c] = !op[0]->value.b[c];
36 for (unsigned c = 0; c < op[0]->type->components(); c++)
    [all...]
  /xsrc/external/mit/xf86-video-geode/dist/src/
geode_blend.h 37 #define usesPasses(op) ((( \
41 0 ) >> (op)) & 1)
44 #define usesSrcAlpha(op) ((( \
51 0 ) >> (op)) & 1)
54 #define usesDstAlpha(op) ((( \
61 0 ) >> (op)) & 1)
64 #define usesChanB0(op) ((( \
72 0 ) >> (op)) & 1)
75 #define usesChanB1(op) ((( \
79 0 ) >> (op)) & 1
    [all...]
  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/swr/rasterizer/common/
simdlib_256_avx512_core.inl 36 #define SIMD_DWRAPPER_1_(op, intrin, mask) \
37 static SIMDINLINE Double SIMDCALL op(Double a) \
41 #define SIMD_DWRAPPER_1(op) SIMD_DWRAPPER_1_(op, op, __mmask8(0xf))
43 #define SIMD_DWRAPPER_1I_(op, intrin, mask) \
45 static SIMDINLINE Double SIMDCALL op(Double a) \
49 #define SIMD_DWRAPPER_1I(op) SIMD_DWRAPPER_1I_(op, op, __mmask8(0xf)
    [all...]
simdlib_512_avx512_knights.inl 32 #define SIMD_WRAPPER_1_(op, intrin) \
33 static SIMDINLINE Float SIMDCALL op(Float a) { return intrin(a); }
35 #define SIMD_WRAPPER_1(op) SIMD_WRAPPER_1_(op, _mm512_##op)
37 #define SIMD_WRAPPER_2_(op, intrin) \
38 static SIMDINLINE Float SIMDCALL op(Float a, Float b) { return _mm512_##intrin(a, b); }
39 #define SIMD_WRAPPER_2(op) SIMD_WRAPPER_2_(op, op)
    [all...]
simdlib_128_avx512_core.inl 36 #define SIMD_WRAPPER_1_(op, intrin, mask) \
37 static SIMDINLINE Float SIMDCALL op(Float a) \
41 #define SIMD_WRAPPER_1(op) SIMD_WRAPPER_1_(op, op, __mmask16(0xf))
43 #define SIMD_WRAPPER_1I_(op, intrin, mask) \
45 static SIMDINLINE Float SIMDCALL op(Float a) \
49 #define SIMD_WRAPPER_1I(op) SIMD_WRAPPER_1I_(op, op, __mmask16(0xf)
    [all...]
simdlib_512_avx512_core.inl 32 #define SIMD_WRAPPER_1_(op, intrin) \
33 static SIMDINLINE Float SIMDCALL op(Float a) { return intrin(a); }
35 #define SIMD_WRAPPER_1(op) SIMD_WRAPPER_1_(op, _mm512_##op)
37 #define SIMD_WRAPPER_2_(op, intrin) \
38 static SIMDINLINE Float SIMDCALL op(Float a, Float b) { return _mm512_##intrin(a, b); }
39 #define SIMD_WRAPPER_2(op) SIMD_WRAPPER_2_(op, op)
    [all...]
  /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/swr/rasterizer/common/
simdlib_256_avx512_core.inl 36 #define SIMD_DWRAPPER_1_(op, intrin, mask) \
37 static SIMDINLINE Double SIMDCALL op(Double a) \
41 #define SIMD_DWRAPPER_1(op) SIMD_DWRAPPER_1_(op, op, __mmask8(0xf))
43 #define SIMD_DWRAPPER_1I_(op, intrin, mask) \
45 static SIMDINLINE Double SIMDCALL op(Double a) \
49 #define SIMD_DWRAPPER_1I(op) SIMD_DWRAPPER_1I_(op, op, __mmask8(0xf)
    [all...]
simdlib_512_avx512_knights.inl 32 #define SIMD_WRAPPER_1_(op, intrin) \
33 static SIMDINLINE Float SIMDCALL op(Float a) { return intrin(a); }
35 #define SIMD_WRAPPER_1(op) SIMD_WRAPPER_1_(op, _mm512_##op)
37 #define SIMD_WRAPPER_2_(op, intrin) \
38 static SIMDINLINE Float SIMDCALL op(Float a, Float b) { return _mm512_##intrin(a, b); }
39 #define SIMD_WRAPPER_2(op) SIMD_WRAPPER_2_(op, op)
    [all...]
simdlib_128_avx512_core.inl 36 #define SIMD_WRAPPER_1_(op, intrin, mask) \
37 static SIMDINLINE Float SIMDCALL op(Float a) \
41 #define SIMD_WRAPPER_1(op) SIMD_WRAPPER_1_(op, op, __mmask16(0xf))
43 #define SIMD_WRAPPER_1I_(op, intrin, mask) \
45 static SIMDINLINE Float SIMDCALL op(Float a) \
49 #define SIMD_WRAPPER_1I(op) SIMD_WRAPPER_1I_(op, op, __mmask16(0xf)
    [all...]
simdlib_512_avx512_core.inl 32 #define SIMD_WRAPPER_1_(op, intrin) \
33 static SIMDINLINE Float SIMDCALL op(Float a) { return intrin(a); }
35 #define SIMD_WRAPPER_1(op) SIMD_WRAPPER_1_(op, _mm512_##op)
37 #define SIMD_WRAPPER_2_(op, intrin) \
38 static SIMDINLINE Float SIMDCALL op(Float a, Float b) { return _mm512_##intrin(a, b); }
39 #define SIMD_WRAPPER_2(op) SIMD_WRAPPER_2_(op, op)
    [all...]
  /xsrc/external/mit/MesaLib.old/src/compiler/glsl/
ir_expression_operation_constant.h 3 for (unsigned c = 0; c < op[0]->type->components(); c++) {
4 switch (op[0]->type->base_type) {
6 data.u[c] = ~ op[0]->value.u[c];
9 data.i[c] = ~ op[0]->value.i[c];
12 data.u64[c] = ~ op[0]->value.u64[c];
15 data.i64[c] = ~ op[0]->value.i64[c];
24 for (unsigned c = 0; c < op[0]->type->components(); c++) {
25 switch (op[0]->type->base_type) {
27 data.b[c] = !op[0]->value.b[c];
36 for (unsigned c = 0; c < op[0]->type->components(); c++)
    [all...]
  /xsrc/external/mit/xf86-video-intel-old/dist/src/
i915_3d.h 219 struct i915_fs_op op; local
221 op.ui[0] = D0_DCL | (REG_TYPE(reg) << D0_TYPE_SHIFT) |
223 op.ui[1] = 0;
224 op.ui[2] = 0;
226 op.ui[0] |= D0_CHANNEL_ALL;
228 return op;
247 struct i915_fs_op op; local
249 op.ui[0] = 0;
250 op.ui[1] = 0;
251 op.ui[2] = 0
275 struct i915_fs_op op; local
    [all...]
  /xsrc/external/mit/MesaLib.old/dist/src/compiler/nir/
nir_lower_bool_to_float.c 48 const nir_op_info *op_info = &nir_op_infos[alu->op];
54 switch (alu->op) {
61 case nir_op_b2f32: alu->op = nir_op_fmov; break;
62 case nir_op_b2i32: alu->op = nir_op_fmov; break;
69 case nir_op_flt: alu->op = nir_op_slt; break;
70 case nir_op_fge: alu->op = nir_op_sge; break;
71 case nir_op_feq: alu->op = nir_op_seq; break;
72 case nir_op_fne: alu->op = nir_op_sne; break;
73 case nir_op_ilt: alu->op = nir_op_slt; break;
74 case nir_op_ige: alu->op = nir_op_sge; break
    [all...]
nir_lower_bool_to_int32.c 47 const nir_op_info *op_info = &nir_op_infos[alu->op];
51 switch (alu->op) {
63 case nir_op_f2b1: alu->op = nir_op_f2b32; break;
64 case nir_op_i2b1: alu->op = nir_op_i2b32; break;
66 case nir_op_flt: alu->op = nir_op_flt32; break;
67 case nir_op_fge: alu->op = nir_op_fge32; break;
68 case nir_op_feq: alu->op = nir_op_feq32; break;
69 case nir_op_fne: alu->op = nir_op_fne32; break;
70 case nir_op_ilt: alu->op = nir_op_ilt32; break;
71 case nir_op_ige: alu->op = nir_op_ige32; break
    [all...]
  /xsrc/external/mit/MesaLib/dist/src/compiler/nir/
nir_lower_bool_to_int32.c 47 const nir_op_info *op_info = &nir_op_infos[alu->op];
51 switch (alu->op) {
68 case nir_op_f2b1: alu->op = nir_op_f2b32; break;
69 case nir_op_i2b1: alu->op = nir_op_i2b32; break;
77 alu->op = nir_op_mov;
80 case nir_op_flt: alu->op = nir_op_flt32; break;
81 case nir_op_fge: alu->op = nir_op_fge32; break;
82 case nir_op_feq: alu->op = nir_op_feq32; break;
83 case nir_op_fneu: alu->op = nir_op_fneu32; break;
84 case nir_op_ilt: alu->op = nir_op_ilt32; break
    [all...]
nir_lower_int_to_float.c 39 const nir_op_info *info = &nir_op_infos[alu->op];
56 switch (alu->op) {
65 case nir_op_b2i32: alu->op = nir_op_b2f32; break;
66 case nir_op_i2f32: alu->op = nir_op_mov; break;
67 case nir_op_u2f32: alu->op = nir_op_mov; break;
68 case nir_op_f2i32: alu->op = nir_op_ftrunc; break;
69 case nir_op_f2u32: alu->op = nir_op_ffloor; break;
70 case nir_op_i2b1: alu->op = nir_op_f2b1; break;
72 case nir_op_ilt: alu->op = nir_op_flt; break;
73 case nir_op_ige: alu->op = nir_op_fge; break
    [all...]
nir_constant_expressions.h 33 void nir_eval_const_opcode(nir_op op, nir_const_value *dest,
  /xsrc/external/mit/MesaLib/dist/src/compiler/glsl/
hir_field_selection.cpp 36 ir_rvalue *op; local
38 op = expr->subexpressions[0]->hir(instructions, state);
47 if (op->type->is_error()) {
49 } else if (op->type->is_struct() || op->type->is_interface()) {
50 result = new(ctx) ir_dereference_record(op,
58 } else if (op->type->is_vector() ||
59 (state->has_420pack() && op->type->is_scalar())) {
60 ir_swizzle *swiz = ir_swizzle::create(op,
62 op->type->vector_elements)
    [all...]
ast_expr.cpp 27 ast_expression::operator_string(enum ast_operators op)
75 assert((unsigned int)op < sizeof(operators) / sizeof(operators[0]));
77 return operators[op];
opt_add_neg_to_sub.h 43 ir_expression *const op = ir->operands[i]->as_expression(); local
45 if (op != NULL && op->operation == ir_unop_neg) {
52 ir->operands[1] = op->operands[0];
  /xsrc/external/mit/MesaLib.old/dist/src/compiler/glsl/
hir_field_selection.cpp 36 ir_rvalue *op; local
38 op = expr->subexpressions[0]->hir(instructions, state);
47 if (op->type->is_error()) {
49 } else if (op->type->is_struct() || op->type->is_interface()) {
50 result = new(ctx) ir_dereference_record(op,
58 } else if (op->type->is_vector() ||
59 (state->has_420pack() && op->type->is_scalar())) {
60 ir_swizzle *swiz = ir_swizzle::create(op,
62 op->type->vector_elements)
    [all...]
ast_expr.cpp 27 ast_expression::operator_string(enum ast_operators op)
75 assert((unsigned int)op < sizeof(operators) / sizeof(operators[0]));
77 return operators[op];
  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/svga/svgadump/
svga_shader_op.h 46 const struct sh_opcode_info *svga_opcode_info( unsigned op );

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