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  /src/sys/external/bsd/drm2/dist/drm/nouveau/dispnv50/
nouveau_dispnv50_core.c 49 } cores[] = { local in function:nv50_core_new
69 cid = nvif_mclass(&disp->disp->object, cores);
75 return cores[cid].new(drm, cores[cid].oclass, pcore);
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
socfpga_arria5.dtsi 7 /* First 4KB has trampoline code for secondary cores. */
socfpga_cyclone5.dtsi 7 /* First 4KB has trampoline code for secondary cores. */
exynos5422-odroidxu3-lite.dts 39 * than Odroid XU3/XU4 boards: 1.8 GHz for A15 cores & 1.3 GHz for A7 cores.
vexpress-v2p-ca15-tc1.dts 199 volt-cores {
203 regulator-name = "Cores";
207 label = "Cores";
210 amp-cores {
211 /* Total current for the two cores */
214 label = "Cores";
224 power-cores {
228 label = "Cores";
235 label = "Cores";
vexpress-v2p-ca15_a7.dts 360 /* Total current for the two A15 cores */
367 /* Total current for the three A7 cores */
381 /* Total power for the two A15 cores */
388 /* Total power for the three A7 cores */
395 /* Total energy for the two A15 cores */
402 /* Total energy for the three A7 cores */
ecx-2000.dts 8 /* First 4KB has pen for secondary cores. */
highbank.dts 8 /* First 4KB has pen for secondary cores. */
dove.dtsi 39 cores = <&gpu>;
bcm2711.dtsi 49 * bringing up secondary cores.
exynos5800-peach-pi.dts 160 * Peach Pi board uses SoC revision with lower maximum frequency for A7 cores
r8a7793.dtsi 428 /* The memory map in the User's Manual maps the cores to
r8a7794.dtsi 373 /* The memory map in the User's Manual maps the cores to
r8a7743.dtsi 429 /* The memory map in the User's Manual maps the cores to
r8a7744.dtsi 429 /* The memory map in the User's Manual maps the cores to
r8a7791.dtsi 453 /* The memory map in the User's Manual maps the cores to
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/marvell/
armada-ap810-ap0-octa-core.dtsi 5 * Device Tree file for Marvell Armada AP810 OCTA cores.
  /src/sys/arch/evbmips/cavium/
machdep.c 390 const int cores = popcount64(fuse); local in function:mach_init_memory
391 mem_clusters[0].start += cores * PAGE_SIZE;
392 mem_clusters[0].size -= cores * PAGE_SIZE;
  /src/sys/stand/efiboot/
smbios.h 234 uint8_t cores; /* cores per socket */ member in struct:smbios_processor
235 uint8_t enabled; /* enabled cores per socket */
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/arm/
vexpress-v2f-1xv7-ca53x2.dts 8 * Cortex-A53 (2 cores) Soft Macrocell Model
  /src/sys/dev/
smbiosvar.h 239 uint8_t cores; /* cores per socket */ member in struct:smbios_processor
240 uint8_t enabled; /* enabled cores per socket */
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/freescale/
imx8qxp.dtsi 55 /* We have 1 clusters with 4 Cortex-A35 cores */
fsl-ls1088a.dtsi 29 /* We have 2 clusters having 4 Cortex-A53 cores each */
fsl-lx2160a.dtsi 28 // 8 clusters having 2 Cortex-A72 cores each

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