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  /xsrc/external/mit/xf86-video-intel/dist/src/render_program/
exa_wm_noca.g4a 33 /* mul mask's alpha channel to src */
35 mul (16) src_sample_r_01<1>F src_sample_r_01<8,8,1>F mask_sample_a_01<8,8,1>F { compr align1 };
36 mul (16) src_sample_g_01<1>F src_sample_g_01<8,8,1>F mask_sample_a_01<8,8,1>F { compr align1 };
37 mul (16) src_sample_b_01<1>F src_sample_b_01<8,8,1>F mask_sample_a_01<8,8,1>F { compr align1 };
38 mul (16) src_sample_a_01<1>F src_sample_a_01<8,8,1>F mask_sample_a_01<8,8,1>F { compr align1 };
exa_wm_noca.g5a 33 /* mul mask's alpha channel to src */
35 mul (16) src_sample_r_01<1>F src_sample_r_01<8,8,1>F mask_sample_a_01<8,8,1>F { compr align1 };
36 mul (16) src_sample_g_01<1>F src_sample_g_01<8,8,1>F mask_sample_a_01<8,8,1>F { compr align1 };
37 mul (16) src_sample_b_01<1>F src_sample_b_01<8,8,1>F mask_sample_a_01<8,8,1>F { compr align1 };
38 mul (16) src_sample_a_01<1>F src_sample_a_01<8,8,1>F mask_sample_a_01<8,8,1>F { compr align1 };
exa_wm_projective.g4i 30 mul (16) temp_x<1>F dst_x<8,8,1>F dw_dx { compr align1 };
31 mul (16) temp_y<1>F dst_y<8,8,1>F dw_dy { compr align1 };
39 mul (16) temp_x<1>F dst_x<8,8,1>F du_dx { compr align1 };
40 mul (16) temp_y<1>F dst_y<8,8,1>F du_dy { compr align1 };
43 mul (16) u<1>F temp_x<8,8,1>F w<8,8,1>F { compr align1 };
47 mul (16) temp_x<1>F dst_x<8,8,1>F dv_dx { compr align1 };
48 mul (16) temp_y<1>F dst_y<8,8,1>F dv_dy { compr align1 };
51 mul (16) v<1>F temp_x<8,8,1>F w<8,8,1>F { compr align1 };
exa_wm_affine.g4i 34 mul (16) temp_x<1>F dst_x<8,8,1>F du_dx { compr align1 };
35 mul (16) temp_y<1>F dst_y<8,8,1>F du_dy { compr align1 };
41 mul (16) temp_x<1>F dst_x<8,8,1>F dv_dx { compr align1 };
42 mul (16) temp_y<1>F dst_y<8,8,1>F dv_dy { compr align1 };
exa_sf.g5a 90 mul (4) m1<1>F g7<4,4,1>F g6.0<0,1,0>F { align1 };
96 mul (4) m2<1>F g7<4,4,1>F g6.8<0,1,0>F {align1 };
exa_sf_mask.g5a 90 mul (8) m1<1>F g7<8,8,1>F g6.0<0,1,0>F { align1 };
96 mul (8) m2<1>F g7<8,8,1>F g6.8<0,1,0>F {align1 };
  /xsrc/external/mit/xf86-video-intel-2014/dist/src/render_program/
exa_wm_noca.g4a 33 /* mul mask's alpha channel to src */
35 mul (16) src_sample_r_01<1>F src_sample_r_01<8,8,1>F mask_sample_a_01<8,8,1>F { compr align1 };
36 mul (16) src_sample_g_01<1>F src_sample_g_01<8,8,1>F mask_sample_a_01<8,8,1>F { compr align1 };
37 mul (16) src_sample_b_01<1>F src_sample_b_01<8,8,1>F mask_sample_a_01<8,8,1>F { compr align1 };
38 mul (16) src_sample_a_01<1>F src_sample_a_01<8,8,1>F mask_sample_a_01<8,8,1>F { compr align1 };
exa_wm_noca.g5a 33 /* mul mask's alpha channel to src */
35 mul (16) src_sample_r_01<1>F src_sample_r_01<8,8,1>F mask_sample_a_01<8,8,1>F { compr align1 };
36 mul (16) src_sample_g_01<1>F src_sample_g_01<8,8,1>F mask_sample_a_01<8,8,1>F { compr align1 };
37 mul (16) src_sample_b_01<1>F src_sample_b_01<8,8,1>F mask_sample_a_01<8,8,1>F { compr align1 };
38 mul (16) src_sample_a_01<1>F src_sample_a_01<8,8,1>F mask_sample_a_01<8,8,1>F { compr align1 };
exa_wm_noca.g6a 33 /* mul mask's alpha channel to src */
35 mul (16) src_sample_r_01<1>F src_sample_r_01<8,8,1>F mask_sample_a_01<8,8,1>F { compr align1 };
36 mul (16) src_sample_g_01<1>F src_sample_g_01<8,8,1>F mask_sample_a_01<8,8,1>F { compr align1 };
37 mul (16) src_sample_b_01<1>F src_sample_b_01<8,8,1>F mask_sample_a_01<8,8,1>F { compr align1 };
38 mul (16) src_sample_a_01<1>F src_sample_a_01<8,8,1>F mask_sample_a_01<8,8,1>F { compr align1 };
exa_wm_projective.g4i 30 mul (16) temp_x<1>F dst_x<8,8,1>F dw_dx { compr align1 };
31 mul (16) temp_y<1>F dst_y<8,8,1>F dw_dy { compr align1 };
39 mul (16) temp_x<1>F dst_x<8,8,1>F du_dx { compr align1 };
40 mul (16) temp_y<1>F dst_y<8,8,1>F du_dy { compr align1 };
43 mul (16) u<1>F temp_x<8,8,1>F w<8,8,1>F { compr align1 };
47 mul (16) temp_x<1>F dst_x<8,8,1>F dv_dx { compr align1 };
48 mul (16) temp_y<1>F dst_y<8,8,1>F dv_dy { compr align1 };
51 mul (16) v<1>F temp_x<8,8,1>F w<8,8,1>F { compr align1 };
exa_wm_affine.g4i 34 mul (16) temp_x<1>F dst_x<8,8,1>F du_dx { compr align1 };
35 mul (16) temp_y<1>F dst_y<8,8,1>F du_dy { compr align1 };
41 mul (16) temp_x<1>F dst_x<8,8,1>F dv_dx { compr align1 };
42 mul (16) temp_y<1>F dst_y<8,8,1>F dv_dy { compr align1 };
exa_sf.g5a 90 mul (4) m1<1>F g7<4,4,1>F g6.0<0,1,0>F { align1 };
96 mul (4) m2<1>F g7<4,4,1>F g6.8<0,1,0>F {align1 };
exa_sf_mask.g5a 90 mul (8) m1<1>F g7<8,8,1>F g6.0<0,1,0>F { align1 };
96 mul (8) m2<1>F g7<8,8,1>F g6.8<0,1,0>F {align1 };
  /xsrc/external/mit/xf86-video-intel-old/dist/src/render_program/
exa_wm_noca.g4a 33 /* mul mask's alpha channel to src */
35 mul (16) src_sample_r_01<1>F src_sample_r_01<8,8,1>F mask_sample_a_01<8,8,1>F { compr align1 };
36 mul (16) src_sample_g_01<1>F src_sample_g_01<8,8,1>F mask_sample_a_01<8,8,1>F { compr align1 };
37 mul (16) src_sample_b_01<1>F src_sample_b_01<8,8,1>F mask_sample_a_01<8,8,1>F { compr align1 };
38 mul (16) src_sample_a_01<1>F src_sample_a_01<8,8,1>F mask_sample_a_01<8,8,1>F { compr align1 };
exa_wm_projective.g4i 30 mul (16) temp_x<1>F dst_x<8,8,1>F dw_dx { compr align1 };
31 mul (16) temp_y<1>F dst_y<8,8,1>F dw_dy { compr align1 };
39 mul (16) temp_x<1>F dst_x<8,8,1>F du_dx { compr align1 };
40 mul (16) temp_y<1>F dst_y<8,8,1>F du_dy { compr align1 };
43 mul (16) u<1>F temp_x<8,8,1>F w<8,8,1>F { compr align1 };
47 mul (16) temp_x<1>F dst_x<8,8,1>F dv_dx { compr align1 };
48 mul (16) temp_y<1>F dst_y<8,8,1>F dv_dy { compr align1 };
51 mul (16) v<1>F temp_x<8,8,1>F w<8,8,1>F { compr align1 };
exa_wm_affine.g4i 34 mul (16) temp_x<1>F dst_x<8,8,1>F du_dx { compr align1 };
35 mul (16) temp_y<1>F dst_y<8,8,1>F du_dy { compr align1 };
41 mul (16) temp_x<1>F dst_x<8,8,1>F dv_dx { compr align1 };
42 mul (16) temp_y<1>F dst_y<8,8,1>F dv_dy { compr align1 };
  /xsrc/external/mit/xf86-video-intel/dist/xvmc/shader/vld/
do_iq_intra.g4i 44 mul (16) g116.0<1>D g[a0.0]<8,8,1>W g112.0<8,8,1>UW {align1 compr};
45 mul (16) g116.0<1>D g116.0<8,8,1>D g109.0<8,8,0>UW {align1 compr};
47 mul (1) g116.0<1>D g111<1,1,1>W g109.4<1,1,1>UW {align1}; //intra_dc_mult
50 mul (16) g118.0<1>D g[a0.0]<8,8,1>W g113.0<8,8,1>UW {align1 compr};
51 mul (16) g118.0<1>D g118.0<8,8,1>D g109.0<8,8,0>UW {align1 compr};
55 mul (16) g120.0<1>D g[a0.0]<8,8,1>W g114.0<8,8,1>UW {align1 compr};
56 mul (16) g120.0<1>D g120.0<8,8,1>D g109.0<8,8,0>UW {align1 compr};
60 mul (16) g122.0<1>D g[a0.0]<8,8,1>W g115.0<8,8,1>UW {align1 compr};
61 mul (16) g122.0<1>D g122.0<8,8,1>D g109.0<8,8,0>UW {align1 compr};
do_iq_non_intra.g4i 40 mul (16) g116.0<1>D g[a0.0]<8,8,1>W g112.0<8,8,1>UW {align1 compr};
41 mul (16) g116.0<1>D g116.0<8,8,1>D g109.0<8,8,0>UW {align1 compr};
45 mul (16) g118.0<1>D g[a0.0]<8,8,1>W g113.0<8,8,1>UW {align1 compr};
46 mul (16) g118.0<1>D g118.0<8,8,1>D g109.0<8,8,0>UW {align1 compr};
50 mul (16) g120.0<1>D g[a0.0]<8,8,1>W g114.0<8,8,1>UW {align1 compr};
51 mul (16) g120.0<1>D g120.0<8,8,1>D g109.0<8,8,0>UW {align1 compr};
55 mul (16) g122.0<1>D g[a0.0]<8,8,1>W g115.0<8,8,1>UW {align1 compr};
56 mul (16) g122.0<1>D g122.0<8,8,1>D g109.0<8,8,0>UW {align1 compr};
  /xsrc/external/mit/xf86-video-intel-2014/dist/xvmc/shader/vld/
do_iq_intra.g4i 44 mul (16) g116.0<1>D g[a0.0]<8,8,1>W g112.0<8,8,1>UW {align1 compr};
45 mul (16) g116.0<1>D g116.0<8,8,1>D g109.0<8,8,0>UW {align1 compr};
47 mul (1) g116.0<1>D g111<1,1,1>W g109.4<1,1,1>UW {align1}; //intra_dc_mult
50 mul (16) g118.0<1>D g[a0.0]<8,8,1>W g113.0<8,8,1>UW {align1 compr};
51 mul (16) g118.0<1>D g118.0<8,8,1>D g109.0<8,8,0>UW {align1 compr};
55 mul (16) g120.0<1>D g[a0.0]<8,8,1>W g114.0<8,8,1>UW {align1 compr};
56 mul (16) g120.0<1>D g120.0<8,8,1>D g109.0<8,8,0>UW {align1 compr};
60 mul (16) g122.0<1>D g[a0.0]<8,8,1>W g115.0<8,8,1>UW {align1 compr};
61 mul (16) g122.0<1>D g122.0<8,8,1>D g109.0<8,8,0>UW {align1 compr};
do_iq_non_intra.g4i 40 mul (16) g116.0<1>D g[a0.0]<8,8,1>W g112.0<8,8,1>UW {align1 compr};
41 mul (16) g116.0<1>D g116.0<8,8,1>D g109.0<8,8,0>UW {align1 compr};
45 mul (16) g118.0<1>D g[a0.0]<8,8,1>W g113.0<8,8,1>UW {align1 compr};
46 mul (16) g118.0<1>D g118.0<8,8,1>D g109.0<8,8,0>UW {align1 compr};
50 mul (16) g120.0<1>D g[a0.0]<8,8,1>W g114.0<8,8,1>UW {align1 compr};
51 mul (16) g120.0<1>D g120.0<8,8,1>D g109.0<8,8,0>UW {align1 compr};
55 mul (16) g122.0<1>D g[a0.0]<8,8,1>W g115.0<8,8,1>UW {align1 compr};
56 mul (16) g122.0<1>D g122.0<8,8,1>D g109.0<8,8,0>UW {align1 compr};
  /xsrc/external/mit/xf86-video-intel-old/dist/src/xvmc/shader/vld/
do_iq_intra.g4i 44 mul (16) g116.0<1>D g[a0.0]<8,8,1>W g112.0<8,8,1>UW {align1 compr};
45 mul (16) g116.0<1>D g116.0<8,8,1>D g109.0<8,8,0>UW {align1 compr};
47 mul (1) g116.0<1>D g111<1,1,1>W g109.4<1,1,1>UW {align1}; //intra_dc_mult
50 mul (16) g118.0<1>D g[a0.0]<8,8,1>W g113.0<8,8,1>UW {align1 compr};
51 mul (16) g118.0<1>D g118.0<8,8,1>D g109.0<8,8,0>UW {align1 compr};
55 mul (16) g120.0<1>D g[a0.0]<8,8,1>W g114.0<8,8,1>UW {align1 compr};
56 mul (16) g120.0<1>D g120.0<8,8,1>D g109.0<8,8,0>UW {align1 compr};
60 mul (16) g122.0<1>D g[a0.0]<8,8,1>W g115.0<8,8,1>UW {align1 compr};
61 mul (16) g122.0<1>D g122.0<8,8,1>D g109.0<8,8,0>UW {align1 compr};
do_iq_non_intra.g4i 40 mul (16) g116.0<1>D g[a0.0]<8,8,1>W g112.0<8,8,1>UW {align1 compr};
41 mul (16) g116.0<1>D g116.0<8,8,1>D g109.0<8,8,0>UW {align1 compr};
45 mul (16) g118.0<1>D g[a0.0]<8,8,1>W g113.0<8,8,1>UW {align1 compr};
46 mul (16) g118.0<1>D g118.0<8,8,1>D g109.0<8,8,0>UW {align1 compr};
50 mul (16) g120.0<1>D g[a0.0]<8,8,1>W g114.0<8,8,1>UW {align1 compr};
51 mul (16) g120.0<1>D g120.0<8,8,1>D g109.0<8,8,0>UW {align1 compr};
55 mul (16) g122.0<1>D g[a0.0]<8,8,1>W g115.0<8,8,1>UW {align1 compr};
56 mul (16) g122.0<1>D g122.0<8,8,1>D g109.0<8,8,0>UW {align1 compr};
  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/nouveau/codegen/lib/
gf100.asm 19 mul $r3 u32 $r1 u32 $r2
20 add $r2 (mul high u32 $r2 u32 $r3) $r2
21 mul $r3 u32 $r1 u32 $r2
22 add $r2 (mul high u32 $r2 u32 $r3) $r2
23 mul $r3 u32 $r1 u32 $r2
24 add $r2 (mul high u32 $r2 u32 $r3) $r2
25 mul $r3 u32 $r1 u32 $r2
26 add $r2 (mul high u32 $r2 u32 $r3) $r2
27 mul $r3 u32 $r1 u32 $r2
28 add $r2 (mul high u32 $r2 u32 $r3) $r
    [all...]
  /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/nouveau/codegen/lib/
gf100.asm 19 mul $r3 u32 $r1 u32 $r2
20 add $r2 (mul high u32 $r2 u32 $r3) $r2
21 mul $r3 u32 $r1 u32 $r2
22 add $r2 (mul high u32 $r2 u32 $r3) $r2
23 mul $r3 u32 $r1 u32 $r2
24 add $r2 (mul high u32 $r2 u32 $r3) $r2
25 mul $r3 u32 $r1 u32 $r2
26 add $r2 (mul high u32 $r2 u32 $r3) $r2
27 mul $r3 u32 $r1 u32 $r2
28 add $r2 (mul high u32 $r2 u32 $r3) $r
    [all...]
  /xsrc/external/mit/MesaLib/dist/src/broadcom/compiler/
vir_opt_redundant_flags.c 83 a->qpu.alu.mul.op != b->qpu.alu.mul.op ||
87 a->qpu.alu.mul.a_unpack != b->qpu.alu.mul.a_unpack ||
88 a->qpu.alu.mul.b_unpack != b->qpu.alu.mul.b_unpack ||
89 a->qpu.alu.mul.output_pack != b->qpu.alu.mul.output_pack) {

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