1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Author:
24 *    Zou Nan hai <nanhai.zou@intel.com>
25 *    Yan Li <li.l.yan@intel.com>
26 *    Liu Xi bin<xibin.liu@intel.com>
27 */
28/* GRF allocation:
29   g1~g30: constant buffer
30           g1~g2:intra IQ matrix
31           g3~g4:non intra IQ matrix
32           g5~g20:IDCT table 
33   g112~g115: intra IQ matrix in UW format (in order to use instruction compress), copys from g1~g2
34   g[a0.0]:DCT data of a block
35   g125:   ip before jump
36   if(v==0 && u==0 && intra_mb) 
37        F''[v][u] = QF[v][u] * intra_dc_mult
38   else 
39        F''[v][u] = (QF[v][u]*W[w][v][u]*quantiser_scale*2)/32       
40*/
41DO_IQ_INTRA:
42add (1) a0.0<1>UD a0.0<1,1,1>UD 0x00200020UD {align1};
43mov (1) g111.0<1>W g[a0.0]<1,1,1>W  {align1};
44mul (16) g116.0<1>D g[a0.0]<8,8,1>W g112.0<8,8,1>UW {align1 compr};
45mul (16) g116.0<1>D g116.0<8,8,1>D g109.0<8,8,0>UW {align1 compr};
46asr (16) g116.0<1>D g116.0<8,8,1>D 4UW {align1 compr};
47mul (1) g116.0<1>D g111<1,1,1>W g109.4<1,1,1>UW {align1};  //intra_dc_mult
48
49add (1) a0.0<1>UD a0.0<1,1,1>UD 0x00200020UD {align1};
50mul (16) g118.0<1>D g[a0.0]<8,8,1>W g113.0<8,8,1>UW {align1 compr};
51mul (16) g118.0<1>D g118.0<8,8,1>D g109.0<8,8,0>UW {align1 compr};
52asr (16) g118.0<1>D g118.0<8,8,1>D 4UW {align1 compr};
53
54add (1) a0.0<1>UD a0.0<1,1,1>UD 0x00200020UD {align1};
55mul (16) g120.0<1>D g[a0.0]<8,8,1>W g114.0<8,8,1>UW {align1 compr};
56mul (16) g120.0<1>D g120.0<8,8,1>D g109.0<8,8,0>UW {align1 compr};
57asr (16) g120.0<1>D g120.0<8,8,1>D 4UW {align1 compr};
58
59add (1) a0.0<1>UD a0.0<1,1,1>UD 0x00200020UD {align1};
60mul (16) g122.0<1>D g[a0.0]<8,8,1>W g115.0<8,8,1>UW {align1 compr};
61mul (16) g122.0<1>D g122.0<8,8,1>D g109.0<8,8,0>UW {align1 compr};
62asr (16) g122.0<1>D g122.0<8,8,1>D 4UW {align1 compr};
63
64add (1) ip g125.0<1,1,1>UD 0x20UD {align1};            //jump back
65