| /src/sys/arch/arm/arm/ |
| cpufunc_asm_arm10.S | 42 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
43 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
46 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
47 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
53 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
56 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
73 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
74 mcr p15, 0, r0, c2, c0, 0 /* set the new TTB */
75 mcr p15, 0, r0, c8, c7, 0 /* and flush the I+D tlbs */
|
| cpufunc_asm_arm1136.S | 40 mcr p15, 0, r0, c7, c10, 2 /* clean data cache line (via index) */
41 mcr p15, 0, r0, c7, c10, 5 /* data memory barrier */
42 mcr p15, 0, r0, c7, c0, 4 /* wait for interrupt */
|
| cpufunc_asm_armv6.S | 52 mcrne p15, 0, r0, c7, c5, 0 /* Flush I cache */
53 mcrne p15, 0, r0, c7, c14, 0 /* clean and invalidate D cache */
55 mcrne p15, 0, r0, c7, c10, 4 /* drain the write buffer */
57 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
59 mcrne p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
71 mcrr p15, 0, r1, r0, c5 /* invalidate I cache range */
72 mcrr p15, 0, r1, r0, c12 /* clean D cache range */
73 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
84 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
85 mcr p15, 0, r0, c7, c10, 0 /* Clean D cache *
[all...] |
| cpufunc_asm_arm67.S | 53 mcrne p15, 0, r2, c7, c0, 0
56 mcr p15, 0, r0, c2, c0, 0
59 mcrne p15, 0, r0, c5, c0, 0
62 mcrne p15, 0, r0, c7, c0, 0
74 mcr p15, 0, r0, c5, c0, 0
78 mcr p15, 0, r0, c6, c0, 0
85 mcr p15, 0, r0, c7, c0, 0
96 mcr p15, 0, r0, c7, c0, 0 /* flush cache */
99 mcr p15, 0, r0, c2, c0, 0
102 mcr p15, 0, r0, c5, c0,
[all...] |
| cpufunc_asm_arm11.S | 50 mcr p15, 0, r0, c2, c0, 0 /* set the new TTBR0 */
52 mcreq p15, 0, r0, c2, c0, 1 /* set the new TTBR1 */
54 mcrne p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
55 mcrne p15, 0, r0, c7, c10, 4 /* drain write buffer */
71 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
72 mcr p15, 0, r0, c2, c0, 0 /* set the new TTBR0 */
75 mcreq p15, 0, r0, c2, c0, 1 /* set the new TTBR1 */
77 mcr p15, 0, r0, c8, c7, 0 /* and flush the I+D tlbs */
93 mcr p15, 0, r0, c8, c5, 0 /* flush I tlb */
94 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer *
[all...] |
| cpufunc_asm_arm11x6.S | 70 mcr p15, 0, Rtmp1, c7, c5, 0 /* Invalidate Entire I cache */
84 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
85 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
86 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
87 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
105 mcr p15, 0, reg, c7, c14, 0;/* Clean and Invalidate Entire Data Cache */ \
106 mcr p15, 0, reg, c7, c10, 4;/* Data Synchronization Barrier */
110 mcr p15, 0, reg, c7, c14, 0;/* Clean and Invalidate Entire Data Cache */ \
111 mrc p15, 0, reg, c7, c10, 6;/* Read Cache Dirty Status Register */ \
114 mcr p15, 0, reg, c7, c10, 4;/* Data Synchronization Barrier *
[all...] |
| cpufunc_asm_arm8.S | 43 mrc p15, 0, r3, c15, c0, 0 /* Read the clock register */
46 mcr p15, 0, r2, c15, c0, 0 /* Write clock register */
53 mcr p15, 0, r1, c15, c0, 0 /* Write clock register */
58 mcr p15, 0, r2, c15, c0, 0 /* Write clock register */
80 mcrne p15, 0, r0, c7, c7, 0 /* flush I+D cache */
83 mcr p15, 0, r0, c2, c0, 0
86 mcrne p15, 0, r0, c8, c7, 0
89 mcrne p15, 0, r0, c7, c7, 0
103 mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */
108 mcr p15, 0, r0, c8, c7, 1 /* flush I+D tlb single entry *
[all...] |
| cpufunc_asm_armv4.S | 47 mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */
53 mcr p15, 0, r0, c8, c5, 0 /* flush I tlb */
59 mcr p15, 0, r0, c8, c6, 0 /* flush D tlb */
64 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
67 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
76 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
|
| cpufunc_asm_sa1.S | 67 mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */
68 mcr p15, 0, r0, c7, c10, 4 /* drain write and fill buffer */
72 mcr p15, 0, r0, c2, c0, 0
75 mcrne p15, 0, r0, c8, c7, 0 /* invalidate I+D TLB */
78 mcrne p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */
95 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
96 mcr p15, 0, r0, c8, c5, 0 /* flush I tlb */
99 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
100 mcr p15, 0, r0, c8, c5, 0 /* flush I tlb */
109 mcr p15, 0, r0, c7, c7, 0 /* flush I+D cache *
[all...] |
| cpufunc_asm.S | 65 mrc p15, 0, r0, c0, c0, 0
70 mrc p15, 0, r0, c0, c0, 1
75 mrc p15, 0, r0, c1, c0, 0
80 mrc p15, 0, r0, c5, c0, 0
85 mrc p15, 0, r0, c6, c0, 0
103 mcr p15, 0, r0, c1, c0, 0
108 mcr p15, 0, r0, c3, c0, 0
123 mrc p15, 0, r3, c1, c0, 0 /* Read the control register */
131 mcrne p15, 0, r2, c1, c0, 0 /* Write new control register */
|
| cpufunc_asm_xscale.S | 96 mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\
103 mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\
117 mrc p15, 0, r3, c1, c0, 0 /* Read the control register */
122 mcrne p15, 0, r0, c7, c5, 6 /* Invalidate the BTB */
123 mcrne p15, 0, r2, c1, c0, 0 /* Write new control register */
150 mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */
151 mcr p15, 0, r0, c7, c10, 4 /* drain write and fill buffer */
159 mcr p15, 0, r0, c2, c0, 0
164 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLB */
167 mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB *
[all...] |
| cpufunc_asm_armv5_ec.S | 64 mcr p15, 0, r0, c7, c5, 0 /* Invalidate ICache */
65 2: mrc p15, 0, APSR_nzcv, c7, c14, 3 /* Test, clean and invalidate DCache */
67 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
70 1: mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
71 mcrne p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
90 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
91 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
95 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
105 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
110 mrc p15, 0, APSR_nzcv, c7, c10, 3 /* Test and clean (don't invalidate) *
[all...] |
| cpufunc_asm_arm9.S | 53 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
55 mcrne p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
63 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
64 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
67 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
68 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
92 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
93 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
107 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
116 mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index *
[all...] |
| cpufunc_asm_armv5.S | 55 1: mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
56 mcrne p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
79 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
80 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
84 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
94 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
103 mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index */
107 mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index */
110 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
127 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA *
[all...] |
| cpufunc_asm_sa11x0.S | 89 mcr p15, 0, r0, c15, c2, 2 /* disable clock switching */
91 mcr p15, 0, r0, c15, c8, 2 /* wait for interrupt
93 mcr p15, 0, r0, c15, c1, 2 /* re-enable clock switching */
113 mcr p15, 0, r0, c2, c0, 0
116 mcr p15, 0, r0, c8, c7, 0 /* flush the I+D tlb */
124 mcr p15, 0, r0, c9, c0, 0 /* drain read buffer */
|
| cpufunc_asm_arm7tdmi.S | 63 mcr p15, 0, r1, c2, c0, 0
83 mcr p15, 0, r0, c8, c7, 0
88 mcr p15, 0, r0, c8, c7, 1
91 mcr p15, 0, r0, c8, c7, 1
102 mcr p15, 0, r0, c7, c7, 0
|
| cpufunc_asm_ixp12x0.S | 54 mcr p15, 0, r0, c2, c0, 0
57 mcr p15, 0, r0, c8, c7, 0 /* flush the I+D tlb */
66 mcr p15, 0, r0, c9, c0, 0 /* drain read buffer */
|
| /src/sys/arch/evbarm/ixm1200/ |
| ixm1200_start.S | 62 mrc p15, 0, r0, c1, c0 ,0 /* read ctrl */
72 mcr p15, 0, r0, c1, c0 ,0 /* write ctrl */
80 mcr p15, 0, r0, c2, c0 ,0 /* write trans table base */
84 mcr p15, 0, r0, c3, c0 ,0 /* write domain */
87 mrc p15, 0, r0, c7, c7 ,0 /* flush D and I cache */
88 mrc p15, 0, r0, c7, c10 ,4 /* drain write buffer */
91 mcr p15, 0, r0, c8, c7 ,0 /* flush D and I TLB */
94 mcr p15, 0, r0, c9, c0 ,0 /* flush all entries */
95 mcr p15, 0, r0, c9, c0 ,4 /* disable user mode MCR access */
99 mcr p15, 0, r0, c13, c0 ,0 /* process ID
[all...] |
| /src/sys/arch/evbarm/iq80310/ |
| iq80310_start.S | 53 mrc p15, 0, r2, c1, c0, 0
55 mcr p15, 0, r2, c1, c0, 0
113 mcr p15, 0, r0, c2, c0, 0
116 mcr p15, 0, r0, c8, c7, 0
120 mcr p15, 0, r0, c3, c0, 0
126 mrc p15, 0, r2, c1, c0, 0
128 mcr p15, 0, r2, c1, c0, 0
135 mrc p15, 0, r2, c2, c0, 0 /* arbitrary read of CP15 */
|
| /src/sys/arch/shark/stand/ofwboot/ |
| srt0.S | 44 mrc p15, 0, r0, c0, c0, 0
71 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
72 mcr p15, 0, r0, c7, c5, 0 /* flush I$ */
|
| /src/sys/arch/zaurus/zaurus/ |
| zaurus_start.S | 48 mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\
80 mcr p15, 0, r0, c2, c0, 0 /* Set TTB */
81 mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */
85 mcr p15, 0, r0, c3, c0, 0
88 mrc p15, 0, r0, c1, c0, 0
91 mcr p15, 0, r0, c1, c0, 0
|
| /src/lib/libc/arch/arm/sys/ |
| __aeabi_read_tp.S | 12 mrc p15, 0, r0, c13, c0, 3
|
| /src/sys/arch/evbarm/g42xxeb/ |
| g42xxeb_start.S | 52 mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\
98 mrc p15, 0, r0, c2, c0, 0 /* get ttb prepared by redboot */
102 mrc p15, 0, r2, c1, c0, 0
123 mcr p15, 0, r0, c2, c0, 0 /* Set TTB */
124 mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */
128 mcr p15, 0, r0, c3, c0, 0
131 mrc p15, 0, r0, c1, c0, 0
133 mcr p15, 0, r0, c1, c0, 0
|
| /src/sys/arch/evbarm/iq80321/ |
| iq80321_start.S | 59 mrc p15, 0, r2, c1, c0, 0
61 mcr p15, 0, r2, c1, c0, 0
122 mcr p15, 0, r0, c2, c0, 0
125 mcr p15, 0, r0, c8, c7, 0
129 mcr p15, 0, r0, c3, c0, 0
135 mrc p15, 0, r2, c1, c0, 0
137 mcr p15, 0, r2, c1, c0, 0
144 mrc p15, 0, r2, c2, c0, 0 /* arbitrary read of CP15 */
|
| /src/sys/arch/evbarm/lubbock/ |
| lubbock_start.S | 52 mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\
98 mrc p15, 0, r0, c2, c0, 0 /* get ttb prepared by redboot */
102 mrc p15, 0, r2, c1, c0, 0
123 mcr p15, 0, r0, c2, c0, 0 /* Set TTB */
124 mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */
128 mcr p15, 0, r0, c3, c0, 0
131 mrc p15, 0, r0, c1, c0, 0
133 mcr p15, 0, r0, c1, c0, 0
|
