1 /* $Id: ar5315reg.h,v 1.3 2011/07/07 05:06:44 matt Exp $ */ 2 /* 3 * Copyright (c) 2006 Urbana-Champaign Independent Media Center. 4 * Copyright (c) 2006 Garrett D'Amore. 5 * All rights reserved. 6 * 7 * This code was written by Garrett D'Amore for the Champaign-Urbana 8 * Community Wireless Network Project. 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer in the documentation and/or other materials provided 18 * with the distribution. 19 * 3. All advertising materials mentioning features or use of this 20 * software must display the following acknowledgements: 21 * This product includes software developed by the Urbana-Champaign 22 * Independent Media Center. 23 * This product includes software developed by Garrett D'Amore. 24 * 4. Urbana-Champaign Independent Media Center's name and Garrett 25 * D'Amore's name may not be used to endorse or promote products 26 * derived from this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE URBANA-CHAMPAIGN INDEPENDENT 29 * MEDIA CENTER AND GARRETT D'AMORE ``AS IS'' AND ANY EXPRESS OR 30 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 31 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 32 * ARE DISCLAIMED. IN NO EVENT SHALL THE URBANA-CHAMPAIGN INDEPENDENT 33 * MEDIA CENTER OR GARRETT D'AMORE BE LIABLE FOR ANY DIRECT, INDIRECT, 34 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 35 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 36 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 39 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 40 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 41 */ 42 43 #ifndef _MIPS_ATHEROS_AR5315REG_H_ 44 #define _MIPS_ATHEROS_AR5315REG_H_ 45 46 #define AR5315_MEM0_BASE 0x00000000 /* sdram */ 47 #define AR5315_MEM1_BASE 0x08000000 /* spi flash */ 48 #define AR5315_WLAN_BASE 0x10000000 49 #define AR5315_PCI_BASE 0x10100000 50 #define AR5315_SDRAMCTL_BASE 0x10300000 51 #define AR5315_LOCAL_BASE 0x10400000 /* local bus */ 52 #define AR5315_ENET_BASE 0x10500000 53 #define AR5315_SYSREG_BASE 0x11000000 54 #define AR5315_UART_BASE 0x11100000 55 #define AR5315_SPI_BASE 0x11300000 /* spi flash */ 56 #define AR5315_BOOTROM_BASE 0x1FC00000 /* boot rom */ 57 #define AR5315_CONFIG_BASE 0x087D0000 /* flash start */ 58 #define AR5315_CONFIG_END 0x087FF000 /* flash end */ 59 #define AR5315_RADIO_END 0x1FFFF000 /* radio end */ 60 61 #if 0 62 #define AR5315_PCIEXT_BASE 0x80000000 /* pci external */ 63 #define AR5315_RAM2_BASE 0xc0000000 64 #define AR5315_RAM3_BASE 0xe0000000 65 #endif 66 67 /* 68 * SYSREG registers -- offset relative to AR531X_SYSREG_BASE 69 */ 70 #define AR5315_SYSREG_COLDRESET 0x0000 71 #define AR5315_SYSREG_RESETCTL 0x0004 72 #define AR5315_SYSREG_AHB_ARB_CTL 0x0008 73 #define AR5315_SYSREG_ENDIAN 0x000c 74 #define AR5315_SYSREG_SREV 0x0014 75 #define AR5315_SYSREG_MISC_INTSTAT 0x0020 76 #define AR5315_SYSREG_MISC_INTMASK 0x0024 77 #define AR5315_SYSREG_GISR 0x0028 78 #define AR5315_SYSREG_WDOG_TIMER 0x0038 79 #define AR5315_SYSREG_WDOG_CTL 0x003c 80 #define AR5315_SYSREG_AHB_ERR0 0x0050 81 #define AR5315_SYSREG_AHB_ERR1 0x0054 82 #define AR5315_SYSREG_AHB_ERR2 0x0058 83 #define AR5315_SYSREG_AHB_ERR3 0x005c 84 #define AR5315_SYSREG_AHB_ERR4 0x0060 85 #define AR5315_SYSREG_PLLC_CTL 0x0064 86 #define AR5315_SYSREG_PLLV_CTL 0x0068 87 #define AR5315_SYSREG_CPUCLK 0x006c 88 #define AR5315_SYSREG_AMBACLK 0x0070 89 90 /* Cold resets (AR5315_SYSREG_COLDRESET) */ 91 #define AR5315_COLD_AHB 0x00000001 92 #define AR5315_COLD_APB 0x00000002 93 #define AR5315_COLD_CPU 0x00000004 94 #define AR5315_COLD_CPU_WARM 0x00000008 95 96 /* Resets (AR5315_SYSREG_RESETCTL) */ 97 #define AR5315_RESET_WARM_WLAN0_MAC 0x00000001 98 #define AR5315_RESET_WARM_WLAN0_BB 0x00000002 99 #define AR5315_RESET_MPEGTS 0x00000004 /* MPEG-TS */ 100 #define AR5315_RESET_PCIDMA 0x00000008 /* PCI dma */ 101 #define AR5315_RESET_MEMCTL 0x00000010 102 #define AR5315_RESET_LOCAL 0x00000020 /* local bus */ 103 #define AR5315_RESET_I2C 0x00000040 /* i2c */ 104 #define AR5315_RESET_SPI 0x00000080 /* SPI */ 105 #define AR5315_RESET_UART 0x00000100 106 #define AR5315_RESET_IR 0x00000200 /* infrared */ 107 #define AR5315_RESET_PHY0 0x00000400 /* enet phy */ 108 #define AR5315_RESET_ENET0 0x00000800 109 110 /* Watchdog control (AR5315_SYSREG_WDOG_CTL) */ 111 #define AR5315_WDOG_CTL_IGNORE 0x0000 112 #define AR5315_WDOG_CTL_NMI 0x0001 113 #define AR5315_WDOG_CTL_RESET 0x0002 114 115 /* AR5315 AHB arbitration control (AR5315_SYSREG_AHB_ARB_CTL) */ 116 #define AR5315_ARB_CPU 0x00001 117 #define AR5315_ARB_WLAN 0x00002 118 #define AR5315_ARB_MPEGTS 0x00004 119 #define AR5315_ARB_LOCAL 0x00008 120 #define AR5315_ARB_PCI 0x00010 121 #define AR5315_ARB_ENET 0x00020 122 #define AR5315_ARB_RETRY 0x00100 123 124 /* AR5315 endianness control (AR5315_SYSREG_ENDIAN) */ 125 #define AR5315_ENDIAN_AHB 0x00001 126 #define AR5315_ENDIAN_WLAN 0x00002 127 #define AR5315_ENDIAN_MPEGTS 0x00004 128 #define AR5315_ENDIAN_PCI 0x00008 129 #define AR5315_ENDIAN_MEMCTL 0x00010 130 #define AR5315_ENDIAN_LOCAL 0x00020 131 #define AR5315_ENDIAN_ENET 0x00040 132 #define AR5315_ENDIAN_MERGE 0x00200 133 #define AR5315_ENDIAN_CPU 0x00400 134 #define AR5315_ENDIAN_PCIAHB 0x00800 135 #define AR5315_ENDIAN_PCIAHB_BRIDGE 0x01000 136 #define AR5315_ENDIAN_SPI 0x08000 137 #define AR5315_ENDIAN_CPU_DRAM 0x10000 138 #define AR5315_ENDIAN_CPU_PCI 0x20000 139 #define AR5315_ENDIAN_CPU_MMR 0x40000 140 141 /* AR5315 AHB error bits */ 142 #define AR5315_AHB_ERROR_DET 1 /* error detected */ 143 #define AR5315_AHB_ERROR_OVR 2 /* AHB overflow */ 144 #define AR5315_AHB_ERROR_WDT 4 /* wdt (not hresp) */ 145 146 /* AR5315 clocks */ 147 #define AR5315_PLLC_REF_DIV(reg) ((reg) & 0x3) 148 #define AR5315_PLLC_FB_DIV(reg) (((reg) & 0x7c) >> 2) 149 #define AR5315_PLLC_DIV_2(reg) (((reg) & 0x80) >> 7) 150 #define AR5315_PLLC_CLKC(reg) (((reg) & 0x1c000) >> 14) 151 #define AR5315_PLLC_CLKM(reg) (((reg) & 0x700000) >> 20) 152 153 #define AR5315_CLOCKCTL_SELECT(reg) ((reg) & 0x3) 154 #define AR5315_CLOCKCTL_DIV(reg) (((reg) & 0xc) >> 2) 155 156 /* 157 * SDRAMCTL registers -- offset relative to SDRAMCTL 158 */ 159 #define AR5315_SDRAMCTL_MEM_CFG 0x0000 160 #define AR5315_MEM_CFG_DATA_WIDTH __BITS(13,14) 161 #define AR5315_MEM_CFG_COL_WIDTH __BITS(9,12) 162 #define AR5315_MEM_CFG_ROW_WIDTH __BITS(5,8) 163 164 /* memory config 1 bits */ 165 #define AR531X_MEM_CFG1_BANK0 __BITS(8,10) 166 #define AR531X_MEM_CFG1_BANK1 __BITS(12,14) 167 168 /* 169 * PCI configuration stuff. I don't pretend to fully understand these 170 * registers, they seem to be magic numbers in the Linux code. 171 */ 172 #define AR5315_PCI_MAC_RC 0x4000 173 #define AR5315_PCI_MAC_SCR 0x4004 174 #define AR5315_PCI_MAC_INTPEND 0x4008 175 #define AR5315_PCI_MAC_SFR 0x400c 176 #define AR5315_PCI_MAC_PCICFG 0x4010 177 #define AR5315_PCI_MAC_SREV 0x4020 178 179 #define PCI_MAC_RC_MAC 0x1 180 #define PCI_MAC_RC_BB 0x2 181 182 #define PCI_MAC_SCR_SLM_MASK 0x00030000 183 #define PCI_MAC_SCR_SLM_FWAKE 0x00000000 184 #define PCI_MAC_SCR_SLM_FSLEEP 0x00010000 185 #define PCI_MAC_SCR_SLM_NORMAL 0x00020000 186 187 #define PCI_MAC_PCICFG_SPWR_DN 0x00010000 188 189 /* IRQS */ 190 #define AR5315_CPU_IRQ_MISC 0 191 #define AR5315_CPU_IRQ_WLAN 1 192 #define AR5315_CPU_IRQ_ENET 2 193 194 #define AR5315_MISC_IRQ_UART 0 195 #define AR5315_MISC_IRQ_I2C 1 196 #define AR5315_MISC_IRQ_SPI 2 197 #define AR5315_MISC_IRQ_AHBE 3 198 #define AR5315_MISC_IRQ_AHPE 4 199 #define AR5315_MISC_IRQ_TIMER 5 200 #define AR5315_MISC_IRQ_GPIO 6 201 #define AR5315_MISC_IRQ_WDOG 7 202 #define AR5315_MISC_IRQ_IR 8 203 204 #endif /* _MIPS_ATHEROS_AR531XREG_H_ */ 205
Indexes created Sat Sep 20 22:09:52 GMT 2025