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      1 /*	$NetBSD: cpuconf.h,v 1.28 2020/09/29 19:58:50 jmcneill Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 2002 Wasabi Systems, Inc.
      5  * All rights reserved.
      6  *
      7  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
      8  *
      9  * Redistribution and use in source and binary forms, with or without
     10  * modification, are permitted provided that the following conditions
     11  * are met:
     12  * 1. Redistributions of source code must retain the above copyright
     13  *    notice, this list of conditions and the following disclaimer.
     14  * 2. Redistributions in binary form must reproduce the above copyright
     15  *    notice, this list of conditions and the following disclaimer in the
     16  *    documentation and/or other materials provided with the distribution.
     17  * 3. All advertising materials mentioning features or use of this software
     18  *    must display the following acknowledgement:
     19  *	This product includes software developed for the NetBSD Project by
     20  *	Wasabi Systems, Inc.
     21  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
     22  *    or promote products derived from this software without specific prior
     23  *    written permission.
     24  *
     25  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
     26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
     29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     35  * POSSIBILITY OF SUCH DAMAGE.
     36  */
     37 
     38 #ifndef _ARM_CPUCONF_H_
     39 #define	_ARM_CPUCONF_H_
     40 
     41 #if defined(_KERNEL_OPT)
     42 #include "opt_cputypes.h"
     43 #include "opt_cpuoptions.h"
     44 #endif /* _KERNEL_OPT */
     45 
     46 #if defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270)
     47 #define	__CPU_XSCALE_PXA2XX
     48 #endif
     49 
     50 #ifdef CPU_XSCALE_PXA2X0
     51 #warning option CPU_XSCALE_PXA2X0 is obsolete. Use CPU_XSCALE_PXA250 and/or CPU_XSCALE_PXA270.
     52 #endif
     53 
     54 /*
     55  * IF YOU CHANGE THIS FILE, MAKE SURE TO UPDATE THE DEFINITION OF
     56  * "PMAP_NEEDS_PTE_SYNC" IN <arm/arm32/pmap.h> FOR THE CPU TYPE
     57  * YOU ARE ADDING SUPPORT FOR.
     58  */
     59 
     60 #if 0
     61 /*
     62  * Step 1: Count the number of CPU types configured into the kernel.
     63  */
     64 #if defined(_KERNEL_OPT)
     65 #define	CPU_NTYPES	(defined(CPU_ARM6) + defined(CPU_ARM7) +	\
     66 			 defined(CPU_ARM7TDMI) +			\
     67 			 defined(CPU_ARM8) + defined(CPU_ARM9) +	\
     68 			 defined(CPU_ARM9E) +				\
     69 			 defined(CPU_ARM10) +				\
     70 			 defined(CPU_ARM11) +				\
     71 			 defined(CPU_ARM1136) +				\
     72 			 defined(CPU_ARM1176) +				\
     73 			 defined(CPU_ARM11MPCORE) +			\
     74 			 defined(CPU_CORTEX) +				\
     75 			 defined(CPU_SA110) + defined(CPU_SA1100) +	\
     76 			 defined(CPU_SA1110) +				\
     77 			 defined(CPU_FA526) +				\
     78 			 defined(CPU_IXP12X0) +				\
     79 			 defined(CPU_XSCALE) +				\
     80 			 defined(CPU_SHEEVA))
     81 #else
     82 #define	CPU_NTYPES	2
     83 #endif /* _KERNEL_OPT */
     84 #endif
     85 
     86 /*
     87  * Step 2: Determine which ARM architecture versions are configured.
     88  */
     89 #if !defined(_KERNEL_OPT)
     90 #define	ARM_ARCH_2	1
     91 #else
     92 #define	ARM_ARCH_2	0
     93 #endif
     94 
     95 #if !defined(_KERNEL_OPT) ||						\
     96     (defined(CPU_ARM6) || defined(CPU_ARM7))
     97 #define	ARM_ARCH_3	1
     98 #else
     99 #define	ARM_ARCH_3	0
    100 #endif
    101 
    102 #if !defined(_KERNEL_OPT) ||						\
    103     (defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined(CPU_ARM9) ||	\
    104      defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_FA526) || \
    105      defined(CPU_SA1110) || defined(CPU_IXP12X0))
    106 #define	ARM_ARCH_4	1
    107 #else
    108 #define	ARM_ARCH_4	0
    109 #endif
    110 
    111 #if !defined(_KERNEL_OPT) ||						\
    112     (defined(CPU_ARM9E) || defined(CPU_ARM10) ||			\
    113      defined(CPU_XSCALE) || defined(CPU_SHEEVA))
    114 #define	ARM_ARCH_5	1
    115 #else
    116 #define	ARM_ARCH_5	0
    117 #endif
    118 
    119 #if defined(CPU_ARM11) || defined(CPU_ARM11MPCORE)
    120 #define ARM_ARCH_6	1
    121 #else
    122 #define ARM_ARCH_6	0
    123 #endif
    124 
    125 #if defined(CPU_CORTEX) || defined(CPU_PJ4B)
    126 #define ARM_ARCH_7	1
    127 #else
    128 #define ARM_ARCH_7	0
    129 #endif
    130 
    131 #define	ARM_NARCH	(ARM_ARCH_2 + ARM_ARCH_3 + ARM_ARCH_4 + \
    132 			 ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7)
    133 #if ARM_NARCH == 0
    134 #error ARM_NARCH is 0
    135 #endif
    136 
    137 #if ARM_ARCH_5 || ARM_ARCH_6 || ARM_ARCH_7
    138 /*
    139  * We could support Thumb code on v4T, but the lack of clean interworking
    140  * makes that hard.
    141  */
    142 #define THUMB_CODE
    143 #endif
    144 
    145 /*
    146  * Step 3: Define which MMU classes are configured:
    147  *
    148  *	ARM_MMU_MEMC		Prehistoric, external memory controller
    149  *				and MMU for ARMv2 CPUs.
    150  *
    151  *	ARM_MMU_GENERIC		Generic ARM MMU, compatible with ARM6.
    152  *
    153  *	ARM_MMU_SA1		StrongARM SA-1 MMU.  Compatible with generic
    154  *				ARM MMU, but has no write-through cache mode.
    155  *
    156  *	ARM_MMU_XSCALE		XScale MMU.  Compatible with generic ARM
    157  *				MMU, but also has several extensions which
    158  *				require different PTE layout to use.
    159  *
    160  *	ARM_MMU_V6C		ARM v6 MMU in backward compatible mode.
    161  *                              Compatible with generic ARM MMU, but
    162  *                              also has several extensions which
    163  *				require different PTE layouts to use.
    164  *                              XP bit in CP15 control reg is cleared.
    165  *
    166  *	ARM_MMU_V6N		ARM v6 MMU with XP bit of CP15 control reg
    167  *                              set.  New features such as shared-bit
    168  *                              and excute-never bit are available.
    169  *                              Multiprocessor support needs this mode.
    170  *
    171  *	ARM_MMU_V7		ARM v7 MMU.
    172  */
    173 #if !defined(_KERNEL_OPT)
    174 #define	ARM_MMU_MEMC		1
    175 #else
    176 #define	ARM_MMU_MEMC		0
    177 #endif
    178 
    179 #if !defined(_KERNEL_OPT) ||						\
    180     (defined(CPU_ARM6) || defined(CPU_ARM7) || defined(CPU_ARM7TDMI) ||	\
    181      defined(CPU_ARM8) || defined(CPU_ARM9) || defined(CPU_ARM9E) ||	\
    182      defined(CPU_ARM10) || defined(CPU_FA526)) || defined(CPU_SHEEVA)
    183 #define	ARM_MMU_GENERIC		1
    184 #else
    185 #define	ARM_MMU_GENERIC		0
    186 #endif
    187 
    188 #if !defined(_KERNEL_OPT) ||						\
    189     (defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) ||\
    190      defined(CPU_IXP12X0))
    191 #define	ARM_MMU_SA1		1
    192 #else
    193 #define	ARM_MMU_SA1		0
    194 #endif
    195 
    196 #if !defined(_KERNEL_OPT) ||						\
    197     defined(CPU_XSCALE)
    198 #define	ARM_MMU_XSCALE		1
    199 #else
    200 #define	ARM_MMU_XSCALE		0
    201 #endif
    202 
    203 #if !defined(_KERNEL_OPT) ||						\
    204 	(defined(CPU_ARM11) && defined(ARM11_COMPAT_MMU))
    205 #define	ARM_MMU_V6C		1
    206 #else
    207 #define	ARM_MMU_V6C		0
    208 #endif
    209 
    210 #if !defined(_KERNEL_OPT) ||						\
    211 	(defined(CPU_ARM11) && !defined(ARM11_COMPAT_MMU))
    212 #define	ARM_MMU_V6N		1
    213 #else
    214 #define	ARM_MMU_V6N		0
    215 #endif
    216 
    217 #define	ARM_MMU_V6	(ARM_MMU_V6C + ARM_MMU_V6N)
    218 
    219 #if !defined(_KERNEL_OPT) ||						\
    220 	 defined(CPU_ARMV7)
    221 #define	ARM_MMU_V7		1
    222 #else
    223 #define	ARM_MMU_V7		0
    224 #endif
    225 
    226 #if !defined(_KERNEL_OPT) ||						\
    227 	 defined(CPU_ARMV8)
    228 #define	ARM_MMU_V8		1
    229 #else
    230 #define	ARM_MMU_V8		0
    231 #endif
    232 
    233 /*
    234  * Can we use the ASID support in armv6+ MMUs?
    235  */
    236 #if !defined(_LOCORE)
    237 #define	ARM_MMU_EXTENDED						\
    238     ((ARM_MMU_MEMC + ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_XSCALE +	\
    239      ARM_MMU_V6C) == 0 &&						\
    240     (ARM_MMU_V6N + ARM_MMU_V7 + ARM_MMU_V8) > 0)
    241 #if ARM_MMU_EXTENDED == 0
    242 #undef ARM_MMU_EXTENDED
    243 #endif
    244 #endif
    245 
    246 #define	ARM_NMMUS							\
    247     (ARM_MMU_MEMC + ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_XSCALE +	\
    248      ARM_MMU_V6N + ARM_MMU_V6C + ARM_MMU_V7 + ARM_MMU_V8)
    249 #if ARM_NMMUS == 0
    250 #error ARM_NMMUS is 0
    251 #endif
    252 
    253 /*
    254  * Step 4: Define features that may be present on a subset of CPUs
    255  *
    256  *	ARM_XSCALE_PMU		Performance Monitoring Unit on 80200 and 80321
    257  */
    258 
    259 #if !defined(_KERNEL_OPT) ||						\
    260     (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321))
    261 #define ARM_XSCALE_PMU	1
    262 #else
    263 #define ARM_XSCALE_PMU	0
    264 #endif
    265 
    266 #endif /* _ARM_CPUCONF_H_ */
    267