| History log of /src/sys/arch/arm/include/cpuconf.h |
| Revision | | Date | Author | Comments |
| 1.28 |
| 29-Sep-2020 |
jmcneill | Collapse all CPU_CORTEXA<n> options into CPU_CORTEX and do runtime
detection instead of ifdefs where required.
|
| 1.27 |
| 10-Aug-2018 |
maxv | Retire CPU_ARM2, CPU_ARM250 and CPU_ARM3, they are all leftovers of
acorn26.
ok jmcneill@ skrll@
|
| 1.26 |
| 01-Apr-2018 |
ryo | branches: 1.26.2;
Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@)
- sys/arch/evbarm64 is gone and integrated into sys/arch/evbarm. (by skrll@)
- add support fdt. evbarm/conf/GENERIC64 fdt (bcm2837,sunxi,tegra) based generic 64bit kernel config. (by skrll@, jmcneill@)
|
| 1.25 |
| 08-Jul-2015 |
skrll | branches: 1.25.16;
Remove CPU_CORTEXA8 from a conditional - it doesn't believe there.
|
| 1.24 |
| 14-Apr-2014 |
matt | branches: 1.24.4;
Support (untested) SHEEVA_L2_CACHE and SHEEVA_L2_CACHE_WT options.
Move prototypes out to <arm/cpufunc.h> to their own file.
Add sdcache routines to cpufunc_asm_sheeva.S
Add code sheeve_setup to init the sdcache and sdcache info.
|
| 1.23 |
| 30-Mar-2014 |
matt | branches: 1.23.2;
Make the ARM pmap use ASIDs, split TTBRs, and MP safe. This only happens for
ARMv6 or later CPUs. This means that on context switch that the TLBs and
caches no longer to cleaned/flushed. Also, eXecute Never (XN) protection has
been added so non-exec pages can not be run. Change the page size for ARMv6+
to be 8KB while allows a L1PT to be a normal page. This means that the L1PT
is not special. Use the XN support to only sync pages that are executed from.
|
| 1.22 |
| 25-Feb-2014 |
matt | Default ARM11 to ARM_MMU_V6N
|
| 1.21 |
| 19-May-2013 |
rkujawa | branches: 1.21.2;
Make PJ4B support code compilable.
Obtained from Marvell, Semihalf.
|
| 1.20 |
| 10-Mar-2011 |
bsh | branches: 1.20.4; 1.20.14;
Preliminary ARM11 MPCore support.
I have confirmed this commit doesn't affect existing evbarm kernels by
comparing binaries.
|
| 1.19 |
| 02-Oct-2010 |
kiyohara | branches: 1.19.2;
Add support Marvell Sheeva Core and SoC. (Orion/Kirkwood)
Discovery Innovation not yet.
|
| 1.18 |
| 19-Jun-2010 |
matt | Cleanup the armv7 changes. Add ARM_ARCH_7. Use CPU_CORTEX instead of
CPU_CORTEXA8 everywhere since there more types of Cortex than just the A8.
CPU_CORTEXA8 still exists but causes CPU_CORTEX to be defined.
Add CPU_CORTEXA9 as well. Use .arch armv7a to get us the isb/dsb
instructions.
Test booted to root device prompt on a Beagleboard.
All ARM kernels successfully test built.
|
| 1.17 |
| 16-Jun-2010 |
jmcneill | PR port-arm/43299: Support added for igepv2/cortexa8/omap3530
Apply patch from PR, with build fixes. ok skrll, matt
|
| 1.16 |
| 27-Feb-2009 |
msaitoh | branches: 1.16.2; 1.16.4;
IXP425 is not ARM_ARCH_4 but ARM_ARCH_5
|
| 1.15 |
| 14-Oct-2008 |
matt | branches: 1.15.2; 1.15.8; 1.15.12;
Add FA526 support (compile tested only)
|
| 1.14 |
| 27-Apr-2008 |
matt | branches: 1.14.6;
Merge kernel changes in matt-armv6 to HEAD.
|
| 1.13 |
| 06-Jan-2007 |
christos | branches: 1.13.26; 1.13.46; 1.13.48; 1.13.50;
Scott Allan in http://mail-index.netbsd.org/port-arm/2006/07/31/0000.html
Patch to add support for ARM9E
|
| 1.12 |
| 11-Dec-2005 |
christos | branches: 1.12.20; 1.12.24;
merge ktrace-lwp.
|
| 1.11 |
| 04-Jul-2005 |
bsh | branches: 1.11.2;
The first step to support Intel PXA270.
kernel config option CPU_XSCALE_PXA2X0 is now obsoleted by
CPU_XSCALE_PXA250 and CPU_XSCALE_PXA270. If both of them are defined,
CPU is determined run-time.
|
| 1.10 |
| 03-Jun-2005 |
rearnsha | Very basic support for the ARM1136.
This code takes no advantage of any 'new' features provided by
architecture 6 devices (such as physically tagged caches or new
MMU features), and basically runs the chip in a 'legacy v5' mode.
|
| 1.9 |
| 21-Aug-2004 |
rearnsha | ARM10 is an architecture 5 device (not 4).
If supporting architecture 5, enable Thumb code support.
Note: we could probably enable this for 4T processors as well, but
getting interworking right is much more tricky.
|
| 1.8 |
| 06-Sep-2003 |
rearnsha | Add support for ARM10 class devices.
|
| 1.7 |
| 23-May-2003 |
ichiro | branches: 1.7.2;
support IXP425 Intel Network Processor
running on BigEndian
|
| 1.6 |
| 22-Apr-2003 |
thorpej | Some ARM32_PMAP_NEW-related cleanup:
* Define a new "MMU type", ARM_MMU_SA1. While the SA-1's MMU is basically
compatible with the generic, the SA-1 cache does not have a write-through
mode, and it is useful to know have an indication of this.
* Add a new PMAP_NEEDS_PTE_SYNC indicator, and try to evaluate it at
compile time. We evaluate it like so:
- If SA-1-style MMU is the only type configured -> 1
- If SA-1-style MMU is not configured -> 0
- Otherwise, defer to a run-time variable.
If PMAP_NEEDS_PTE_SYNC might evaluate to true (SA-1 only or run-time
check), then we also define PMAP_INCLUDE_PTE_SYNC so that e.g. assembly
code can include the necessary run-time support. PMAP_INCLUDE_PTE_SYNC
largely replaces the ARM32_PMAP_NEEDS_PTE_SYNC manual setting Steve
included with the original new pmap.
* In the new pmap, make pmap_pte_init_generic() check to see if the CPU
has a write-back cache. If so, init the PT cache mode to C=1,B=0 to get
write-through mode. Otherwise, init the PT cache mode to C=1,B=1.
* Add a new pmap_pte_init_arm8(). Old pmap, same as generic. New pmap,
sets page table cacheability to 0 (ARM8 has a write-back cache, but
flushing it is quite expensive).
* In the new pmap, make pmap_pte_init_arm9() reset the PT cache mode to
C=1,B=0, since the write-back check in generic gets it wrong for ARM9,
since we use write-through mode all the time on ARM9 right now. (What
this really tells me is that the test for write-through cache is less
than perfect, but we can fix that later.)
* Add a new pmap_pte_init_sa1(). Old pmap, same as generic. New pmap,
does generic initialization, then resets page table cache mode to
C=1,B=1, since C=1,B=0 does not produce write-through on the SA-1.
|
| 1.5 |
| 09-Apr-2003 |
thorpej | Fix a typo.
|
| 1.4 |
| 07-Aug-2002 |
briggs | Implement pmc(9) -- An interface to hardware performance monitoring
counters. These counters do not exist on all CPUs, but where they
do exist, can be used for counting events such as dcache misses that
would otherwise be difficult or impossible to instrument by code
inspection or hardware simulation.
pmc(9) is meant to be a general interface. Initially, the Intel XScale
counters are the only ones supported.
|
| 1.3 |
| 15-Jul-2002 |
ichiro | add support for ixp12x0
|
| 1.2 |
| 03-May-2002 |
thorpej | branches: 1.2.2; 1.2.6;
Add support for the Intel PXA210 and PXA250. From Hiroyuki Bessho, PR 16617.
|
| 1.1 |
| 12-Apr-2002 |
thorpej | branches: 1.1.2;
Centralize ARM CPU configuration information by adding a new header
file, <arm/cpuconf.h>, which pulls in "opt_cputypes.h" and then defines
the following:
* CPU_NTYPES -- now many CPU types are configured into the kernel. What
you really want to know is "== 1" or "> 1".
* Defines ARM_ARCH_2, ARM_ARCH_3, ARM_ARCH_4, ARM_ARCH_5, depending
on which ARM architecture versions are configured (based on CPU_*
options). Also defines ARM_NARCH to determins how many architecture
versions are configured.
* Defines ARM_MMU_MEMC, ARM_MMU_GENERIC, ARM_MMU_XSCALE depending on
which classes of ARM MMUs are configured into the kernel, and ARM_NMMUS
to determine how many MMU classes are configured.
Remove the needless inclusion of "opt_cputypes.h" in several places.
Convert remaining users to <arm/cpuconf.h>.
|
| 1.1.2.5 |
| 13-Aug-2002 |
nathanw | Catch up to -current.
|
| 1.1.2.4 |
| 01-Aug-2002 |
nathanw | Catch up to -current.
|
| 1.1.2.3 |
| 20-Jun-2002 |
nathanw | Catch up to -current.
|
| 1.1.2.2 |
| 17-Apr-2002 |
nathanw | Catch up to -current.
|
| 1.1.2.1 |
| 12-Apr-2002 |
nathanw | file cpuconf.h was added on branch nathanw_sa on 2002-04-17 00:02:30 +0000
|
| 1.2.6.3 |
| 06-Sep-2002 |
jdolecek | sync kqueue branch with HEAD
|
| 1.2.6.2 |
| 23-Jun-2002 |
jdolecek | catch up with -current on kqueue branch
|
| 1.2.6.1 |
| 03-May-2002 |
jdolecek | file cpuconf.h was added on branch kqueue on 2002-06-23 17:34:51 +0000
|
| 1.2.2.2 |
| 30-Aug-2002 |
gehenna | catch up with -current.
|
| 1.2.2.1 |
| 21-Jul-2002 |
gehenna | catch up with -current.
|
| 1.7.2.5 |
| 10-Nov-2005 |
skrll | Sync with HEAD. Here we go again...
|
| 1.7.2.4 |
| 21-Sep-2004 |
skrll | Fix the sync with head I botched.
|
| 1.7.2.3 |
| 18-Sep-2004 |
skrll | Sync with HEAD.
|
| 1.7.2.2 |
| 25-Aug-2004 |
skrll | Sync with HEAD.
|
| 1.7.2.1 |
| 03-Aug-2004 |
skrll | Sync with HEAD
|
| 1.11.2.1 |
| 26-Feb-2007 |
yamt | sync with head.
|
| 1.12.24.1 |
| 21-Feb-2007 |
snj | branches: 1.12.24.1.4;
Pull up following revision(s) (requested by matt in ticket #457):
sys/arch/arm/include/cpufunc.h: revision 1.38
sys/arch/arm/arm/cpufunc.c: revision 1.78
sys/arch/arm/arm/cpufunc_asm_arm10.S: revision 1.6
sys/arch/arm/include/armreg.h: revision 1.37
sys/arch/arm/arm32/cpu.c: revision 1.64
sys/arch/arm/arm/cpufunc_asm_armv5.S: revision 1.3
sys/arch/arm/include/cpuconf.h: revision 1.13
sys/arch/arm/conf/files.arm: revision 1.82
sys/arch/arm/arm/cpufunc_asm_armv5_ec.S: revision 1.1
Scott Allan in http://mail-index.netbsd.org/port-arm/2006/07/31/0000.html
Patch to add support for ARM9E
|
| 1.12.24.1.4.1 |
| 10-Nov-2007 |
matt | Add AT91 support from Sami Kantoluoto
Add TI OMAP2430 support from Marty Fouts @ Danger Inc
|
| 1.12.20.1 |
| 12-Jan-2007 |
ad | Sync with head.
|
| 1.13.50.4 |
| 09-Oct-2010 |
yamt | sync with head
|
| 1.13.50.3 |
| 11-Aug-2010 |
yamt | sync with head.
|
| 1.13.50.2 |
| 04-May-2009 |
yamt | sync with head.
|
| 1.13.50.1 |
| 16-May-2008 |
yamt | sync with head.
|
| 1.13.48.1 |
| 18-May-2008 |
yamt | sync with head.
|
| 1.13.46.2 |
| 17-Jan-2009 |
mjf | Sync with HEAD.
|
| 1.13.46.1 |
| 02-Jun-2008 |
mjf | Sync with HEAD.
|
| 1.13.26.1 |
| 12-Oct-2007 |
matt | Import TI OMAP 2430 and ARM11/ARMv6 support. Now on ARMv6, the cache is
no longer purged on context switches.
|
| 1.14.6.1 |
| 19-Oct-2008 |
haad | Sync with HEAD.
|
| 1.15.12.1 |
| 15-Feb-2014 |
matt | Merge armv7 support from HEAD, specifically support for the BCM5301X
and BCM56340 evbarm kernels.
|
| 1.15.8.1 |
| 13-May-2009 |
jym | Sync with HEAD.
Commit is split, to avoid a "too many arguments" protocol error.
|
| 1.15.2.1 |
| 03-Mar-2009 |
skrll | Sync with HEAD.
|
| 1.16.4.3 |
| 21-Apr-2011 |
rmind | sync with head
|
| 1.16.4.2 |
| 05-Mar-2011 |
rmind | sync with head
|
| 1.16.4.1 |
| 03-Jul-2010 |
rmind | sync with head
|
| 1.16.2.2 |
| 22-Oct-2010 |
uebayasi | Sync with HEAD (-D20101022).
|
| 1.16.2.1 |
| 17-Aug-2010 |
uebayasi | Sync with HEAD.
|
| 1.19.2.1 |
| 06-Jun-2011 |
jruoho | Sync with HEAD.
|
| 1.20.14.3 |
| 03-Dec-2017 |
jdolecek | update from HEAD
|
| 1.20.14.2 |
| 20-Aug-2014 |
tls | Rebase to HEAD as of a few days ago.
|
| 1.20.14.1 |
| 23-Jun-2013 |
tls | resync from head
|
| 1.20.4.1 |
| 22-May-2014 |
yamt | sync with head.
for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.
this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
|
| 1.21.2.1 |
| 18-May-2014 |
rmind | sync with head
|
| 1.23.2.1 |
| 10-Aug-2014 |
tls | Rebase.
|
| 1.24.4.1 |
| 22-Sep-2015 |
skrll | Sync with HEAD
|
| 1.25.16.2 |
| 06-Sep-2018 |
pgoyette | Sync with HEAD
Resolve a couple of conflicts (result of the uimin/uimax changes)
|
| 1.25.16.1 |
| 07-Apr-2018 |
pgoyette | Sync with HEAD. 77 conflicts resolved - all of them $NetBSD$
|
| 1.26.2.1 |
| 10-Jun-2019 |
christos | Sync with HEAD
|
