1 /* $NetBSD: i80312reg.h,v 1.12 2018/02/08 09:05:17 dholland Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /*- 39 * Copyright (c) 2001 The NetBSD Foundation, Inc. 40 * All rights reserved. 41 * 42 * This code is derived from software contributed to The NetBSD Foundation 43 * by Matt Thomas <matt (at) 3am-software.com>. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice, this list of conditions and the following disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 55 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 56 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 57 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 58 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 59 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 60 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 61 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 62 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 63 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 64 * POSSIBILITY OF SUCH DAMAGE. 65 */ 66 67 #ifndef _ARM_XSCALE_I80312REG_H_ 68 #define _ARM_XSCALE_I80312REG_H_ 69 70 /* 71 * Register definitions for the Intel 80310 I/O Companion Chip. 72 */ 73 74 /* 75 * Physical addresses 0x1000..0x1fff are used by the Periphial Memory 76 * Mapped Registers. 77 */ 78 79 #define I80312_PMMR_BASE 0x00001000UL 80 #define I80312_PMMR_SIZE 0x00001000UL 81 82 /* 83 * The PMMR registers below are defined as offsets from the i80312 PMMR 84 * base. 85 */ 86 87 /* 88 * PCI-to-PCI Bridge Unit 89 */ 90 #define I80312_PPB_BASE (0) 91 #define I80312_PPB_SIZE 0x100 92 /* 93 * Performance Monitoring Unit 94 */ 95 #define I80312_PMU_BASE (I80312_PPB_BASE + I80312_PPB_SIZE) /* 0x100 */ 96 #define I80312_PMU_SIZE 0x100 97 /* 98 * Address Translation Unit 99 */ 100 #define I80312_ATU_BASE (I80312_PMU_BASE + I80312_PMU_SIZE) /* 0x200 */ 101 #define I80312_ATU_SIZE 0x100 102 /* 103 * Messaging Unit 104 */ 105 #define I80312_MSG_BASE (I80312_ATU_BASE + I80312_ATU_SIZE) /* 0x300 */ 106 #define I80312_MSG_SIZE 0x100 107 /* 108 * DMA Controller 109 */ 110 #define I80312_DMA_BASE (I80312_MSG_BASE + I80312_MSG_SIZE) /* 0x400 */ 111 #define I80312_DMA_SIZE 0x100 112 /* 113 * Memory Controller 114 */ 115 #define I80312_MEM_BASE (I80312_DMA_BASE + I80312_DMA_SIZE) /* 0x500 */ 116 #define I80312_MEM_SIZE 0x100 117 /* 118 * Internal Arbitration Unit 119 */ 120 #define I80312_IARB_BASE (I80312_MEM_BASE + I80312_MEM_SIZE) /* 0x600 */ 121 #define I80312_IARB_SIZE 0x040 122 /* 123 * Bus Interface Unit 124 */ 125 #define I80312_BUS_BASE (I80312_IARB_BASE + I80312_IARB_SIZE)/* 0x640 */ 126 #define I80312_BUS_SIZE 0x040 127 /* 128 * I2C Unit 129 */ 130 #define I80312_IIC_BASE (I80312_BUS_BASE + I80312_BUS_SIZE) /* 0x680 */ 131 #define I80312_IIC_SIZE 0x080 132 /* 133 * Interrupt Controller 134 */ 135 #define I80312_INTC_BASE (I80312_IIC_BASE + I80312_IIC_SIZE) /* 0x700 */ 136 #define I80312_INTC_SIZE 0x100 137 /* 138 * Application Accelerator Unit 139 */ 140 #define I80312_AAU_BASE (I80312_INTC_BASE + I80312_INTC_SIZE)/* 0x800 */ 141 #define I80312_AAU_SIZE 0x100 142 143 /* 144 * PCI-PCI Bridge Unit 145 * 146 * The PCI-PCI Bridge Unit supports both public (accessible to the 147 * host) and private (accessible only to the local system) devices: 148 * 149 * --------- 150 * S_AD[11] 151 * S_AD[12] 152 * Private S_AD[13] 153 * S_AD[14] 154 * S_AD[15] 155 * --------- 156 * S_AD[16] SISR bit 9 157 * S_AD[17] SISR bit 8 158 * S_AD[18] SISR bit 7 159 * Public S_AD[19] SISR bit 6 160 * or S_AD[20] SISR bit 5 161 * Private S_AD[21] SISR bit 4 162 * S_AD[22] SISR bit 3 163 * S_AD[23] SISR bit 2 164 * S_AD[24] SISR bit 1 165 * S_AD[25] SISR bit 0 166 * --------- 167 * S_AD[26] 168 * S_AD[27] 169 * Public S_AD[28] 170 * S_AD[29] 171 * S_AD[30] 172 * S_AD[31] 173 * --------- 174 * 175 * Setting the specified SISR bit makes the corresponding S_AD line 176 * a private service. 177 */ 178 #define I80312_PPB_EBCR 0x40 /* Extended Bridge Control */ 179 #define I80312_PPB_SISR 0x42 /* Secondary ID Select Register */ 180 #define I80312_PPB_PBISR 0x44 /* Primary Bridge Int. Stat. */ 181 #define I80312_PPB_SBISR 0x48 /* Secondary Bridge Int. Stat. */ 182 #define I80312_PPB_SACR XXX /* Secondary Arb. Control */ 183 #define I80312_PPB_PIRSR XXX /* PCI Int. Routing Select */ 184 #define I80312_PPB_SIOBR 0x54 /* Secondary I/O Base Register */ 185 #define I80312_PPB_SIOLR 0x55 /* Secondary I/O Limit Register */ 186 #define I80312_PPB_SCDR 0x56 /* Secondary Clock Disable Register */ 187 #define I80312_PPB_SMBR 0x58 /* Secondary Memory Base Register */ 188 #define I80312_PPB_SMLR 0x5a /* Secondary Memory Limit Register */ 189 #define I80312_PPB_SDER 0x5c /* Secondary Decode Enable Register */ 190 #define I80312_PPB_QCR 0x5e /* Queue Control Register */ 191 192 #define PPB_SDER_PMSE (1U << 2) /* Private Memory Space Enable */ 193 194 /* 195 * Performance Monitoring Unit 196 */ 197 #define I80312_PMU_GTMR 0x00 /* Global Timer Mode Register */ 198 #define I80312_PMU_ESR 0x04 /* Event Select Register */ 199 #define I80312_PMU_EMISR 0x08 /* Event Monitoring Int Stat Reg */ 200 #define I80312_PMU_GTSR 0x10 /* Global Time Stamp Register */ 201 /* Programmable Event Counter Regs */ 202 #define I80312_PMU_PECR(x) (0x14 + (4 * ((x) - 1))) 203 204 #define PMU_GTMR_INTEN (1U << 0) 205 #define PMU_GTMR_CNTRDIS (1U << 2) 206 207 #define PMU_ESR_MODE(x) ((x)) 208 #define PMU_ESR_PMIE (1U << 16) 209 210 #define PMU_EMISR_GTS (1U << 0) 211 #define PMU_EMISR_PECRS(x) (1U << (x)) 212 213 /* 214 * Address Translation Unit 215 * The first 64 bytes are identical to a PCI device's config space. 216 */ 217 /* BAR #0 0x10 Primary Inbound ATU Base Address */ 218 #define I80312_ATU_PIAL 0x40 /* Pri. Inbound ATU Limit */ 219 #define I80312_ATU_PIATV 0x44 /* Pri. Inbound ATU Translate Value */ 220 #define I80312_ATU_SIAM 0x48 /* Sec. Inbound ATU Base Address */ 221 #define I80312_ATU_SIAL 0x4c /* Sec. Inbound ATU Limit */ 222 #define I80312_ATU_SIATV 0x50 /* Sec. Inbound ATU Translate Value */ 223 #define I80312_ATU_POMWV 0x54 /* Pri. Outbound Memory Window Value */ 224 /* not used 0x58 */ 225 #define I80312_ATU_POIOWV 0x5c /* Pri. Outbound I/O Window Value */ 226 #define I80312_ATU_PODACWVL 0x60 /* Pri. Outbound DAC Window Value (Lo)*/ 227 #define I80312_ATU_PODACWVH 0x64 /* Pri. Outbound DAC Window Value (Hi)*/ 228 #define I80312_ATU_SOMWV 0x68 /* Sec. Outbound Memory Window Value */ 229 #define I80312_ATU_SOIOWV 0x6c /* Sec. Outbound I/O Window Value */ 230 /* not used 0x70 */ 231 #define I80312_ATU_ERL 0x74 /* Expansion ROM Limit */ 232 #define I80312_ATU_ERTV 0x78 /* Expansion ROM Translate Value */ 233 /* not used 0x7c */ 234 #define I80312_ATU_ACI 0x74 /* ATU Capability Identifier */ 235 #define I80312_ATU_ATNIP 0x78 /* ATU Next Item Pointer */ 236 #define I80312_ATU_APM 0x7c /* ATU Power Management */ 237 /* not used 0x84 */ 238 #define I80312_ATU_ACR 0x88 /* ATU Configuration */ 239 /* not used 0x8c */ 240 #define I80312_ATU_PAIS 0x90 /* Pri. ATU Interrupt Status */ 241 #define I80312_ATU_SAIS 0x94 /* Sec. ATU Interrupt Status */ 242 #define I80312_ATU_SACS 0x98 /* Sec. ATU Command/Status */ 243 #define I80312_ATU_SODACWVL 0x9c /* Sec. Outbound DAC Window Value (lo)*/ 244 #define I80312_ATU_SODACWVH 0xa0 /* Sec. Outbound DAC Window Value (hi)*/ 245 #define I80312_ATU_POCCA 0xa4 /* Pri. Outbound Config Address Data */ 246 #define I80312_ATU_SOCCA 0xa8 /* Sec. Outbound Config Address Data */ 247 #define I80312_ATU_POCCD 0xac /* Pri. Outbound Config Cycle Data */ 248 #define I80312_ATU_SOCCD 0xb0 /* Sec. Outbound Config Cycle Data */ 249 #define I80312_ATU_PAQC 0xb4 /* Pri. ATU Queue Control */ 250 #define I80312_ATU_SAQC 0xb8 /* Sec. ATU Queue Control */ 251 #define I80312_ATU_PAIM 0xbc /* Pri. ATU Interrupt Mask */ 252 #define I80312_ATU_SAIM 0xc0 /* Sec. ATU Interrupt Mask */ 253 /* not used 0xc4 .. 0xfc */ 254 255 #define ATU_LIMIT(x) \ 256 ((0xffffffffUL - ((x) - 1)) & 0xfffffff0UL) 257 258 #define ATU_ACR_POAE (1U << 1) 259 #define ATU_ACR_SOAE (1U << 2) 260 #define ATU_ACR_SDAS (1U << 7) 261 #define ATU_ACR_DAE (1U << 8) 262 #define ATU_ACR_PSERRIE (1U << 9) 263 #define ATU_ACR_SSERRIE (1U << 10) 264 #define ATU_ACR_SBMUAE (1U << 12) 265 #define ATU_ACR_ADTS (1U << 15) 266 #define ATU_ACR_PSERRMA (1U << 16) 267 #define ATU_ACR_SSERRMA (1U << 17) 268 #define ATU_ACR_DAU2GTE (1U << 18) 269 #define ATU_ACR_PATUDRCA (1U << 19) 270 #define ATU_ACR_SATUDRCA (1U << 20) 271 #define ATU_ACR_BFN (1U << 21) 272 273 #define ATU_AIM_AETAE (1U << 0) 274 #define ATU_AIM_AIESE (1U << 1) 275 #define ATU_AIM_MPEIM (1U << 2) 276 #define ATU_AIM_TATIM (1U << 3) 277 #define ATU_AIM_TAMIM (1U << 4) 278 #define ATU_AIM_MAIM (1U << 5) 279 #define ATU_AIM_SAIM (1U << 6) 280 #define ATU_AIM_DPEIM (1U << 7) 281 #define ATU_AIM_PSTIM (1U << 8) 282 283 /* 284 * Messaging Unit 285 */ 286 /* not used 0x00 .. 0x0c */ 287 #define I80312_MSG_IM0 0x10 /* Inbound Message 0 */ 288 #define I80312_MSG_IM1 0x14 /* Inbound Message 1 */ 289 #define I80312_MSG_OM0 0x18 /* Outbound Message 0 */ 290 #define I80312_MSG_OM1 0x1c /* Outbound Message 1 */ 291 #define I80312_MSG_ID 0x20 /* Inbound Doorbell */ 292 #define I80312_MSG_IIS 0x24 /* Inbound Interrupt Status */ 293 #define I80312_MSG_IIM 0x28 /* Inbound Interrupt Mask */ 294 #define I80312_MSG_OD 0x2c /* Outbound Doorbell */ 295 #define I80312_MSG_OIS 0x30 /* Outbound Interrupt Status */ 296 #define I80312_MSG_OIM 0x34 /* Outbound Interrupt Mask */ 297 /* not used 0x38 .. 0x4c */ 298 #define I80312_MSG_MC 0x50 /* MU Configuration */ 299 #define I80312_MSG_QBA 0x54 /* Queue Base Address */ 300 /* not used 0x58 .. 0x5c */ 301 #define I80312_MSG_IFHP 0x60 /* Inbound Free Head Pointer */ 302 #define I80312_MSG_IFTP 0x64 /* Inbound Free Tail Pointer */ 303 #define I80312_MSG_IPHP 0x68 /* Inbound Post Head Pointer */ 304 #define I80312_MSG_IPTP 0x6c /* Inbound Post Tail Pointer */ 305 #define I80312_MSG_OFHP 0x70 /* Outbound Free Head Pointer */ 306 #define I80312_MSG_OFTP 0x74 /* Outbound Free Tail Pointer */ 307 #define I80312_MSG_OPHP 0x78 /* Outbound Post Head Pointer */ 308 #define I80312_MSG_OPTP 0x7c /* Outbound Post Tail Pointer */ 309 #define I80312_MSG_IA 0x80 /* Index Address */ 310 /* not used 0x84 .. 0xfc */ 311 312 /* 313 * DMA Controller 314 */ 315 #define I80312_DMA_CHAN0 0x00 /* Channel 0 */ 316 #define I80312_DMA_CHAN1 0x40 /* Channel 1 */ 317 #define I80312_DMA_CHAN2 0x80 /* Channel 2 */ 318 /* not used 0xc0 .. 0xfc */ 319 320 #define I80312_DMA_CC 0x00 /* Channel Control */ 321 #define I80312_DMA_CS 0x04 /* Channel Status */ 322 /* not used 0x08 */ 323 #define I80312_DMA_DA 0x0c /* Descriptor Address */ 324 #define I80312_DMA_NDA 0x10 /* Next Descriptor Address */ 325 #define I80312_DMA_PA 0x14 /* PCI Address */ 326 #define I80312_DMA_PUA 0x18 /* PCI Upper Address */ 327 #define I80312_DMA_IBA 0x1c /* Internal Bus Address */ 328 #define I80312_DMA_BC 0x20 /* Byte Count */ 329 #define I80312_DMA_DC 0x24 /* Descriptor Control */ 330 /* not used 0x28 .. 0x3c */ 331 332 /* 333 * Memory Controller 334 */ 335 #define I80312_MEM_SI 0x00 /* SDRAM Initialization */ 336 #define I80312_MEM_SC 0x04 /* SDRAM Control */ 337 #define I80312_MEM_SB 0x08 /* SDRAM Base */ 338 #define I80312_MEM_SB0 0x0c /* SDRAM Bank 0 Size */ 339 #define I80312_MEM_SB1 0x10 /* SDRAM Bank 1 Size */ 340 /* not used 0x14 .. 0x30 */ 341 #define I80312_MEM_EC 0x34 /* ECC Control */ 342 #define I80312_MEM_EL0 0x38 /* ECC Log 0 */ 343 #define I80312_MEM_EL1 0x3c /* ECC Log 1 */ 344 #define I80312_MEM_EA0 0x40 /* ECC Address 0 */ 345 #define I80312_MEM_EA1 0x44 /* ECC Address 1 */ 346 #define I80312_MEM_ET 0x48 /* ECC Test */ 347 #define I80312_MEM_FB0 0x4c /* ECC Flash Base 0 */ 348 #define I80312_MEM_FB1 0x50 /* ECC Flash Base 1 */ 349 #define I80312_MEM_FB0S 0x54 /* ECC Flash Bank 0 Size */ 350 #define I80312_MEM_FB1S 0x58 /* ECC Flash Bank 1 Size */ 351 #define I80312_MEM_FWS1 0x5c /* ECC Wait State 1 Size */ 352 #define I80312_MEM_FWS0 0x60 /* ECC Wait State 0 Size */ 353 #define I80312_MEM_IS 0x65 /* ECC Interrupt Status */ 354 #define I80312_MEM_RF 0x68 /* ECC Refresh Frequency */ 355 #define I80312_MEM_RF 0x68 /* ECC Refresh Frequency */ 356 #define I80312_MEM_RF 0x68 /* ECC Refresh Frequency */ 357 #define I80312_MEM_RF 0x68 /* ECC Refresh Frequency */ 358 /* not used 0x6c .. 0xfc */ 359 360 /* 361 * Internal Arbitration Unit 362 */ 363 #define I80312_ARB_IAC 0x00 /* Internal Aribtration Control */ 364 #define I80312_ARB_MLT 0x04 /* Master Latency Timer */ 365 #define I80312_ARB_MTT 0x08 /* Multi-Transaction Timer */ 366 /* not used 0x0c .. 0x3c */ 367 368 /* 369 * Bus(Core) Interface Unit 370 */ 371 /* not used 0x40 */ 372 #define I80312_BUS_IS 0x44 /* Interrupt Status */ 373 /* not used 0x4c .. 0x7c */ 374 375 /* 376 * I2C Bus Interface Unit 377 */ 378 #define I80312_IIC_CTL 0x80 /* Control */ 379 #define I80312_IIC_STS 0x84 /* Status */ 380 #define I80312_IIC_SA 0x88 /* Slave Address */ 381 #define I80312_IIC_DB 0x8c /* Data Buffer */ 382 #define I80312_IIC_CC 0x90 /* Clock Control */ 383 #define I80312_IIC_BM 0x94 /* Bus Monitor */ 384 /* not used 0x98 .. 0xfc */ 385 386 /* 387 * PCI And Peripheral Interrupt (GPIO) Unit 388 */ 389 #define I80312_INTC_IIS 0x00 /* IRQ Interrupt Status */ 390 #define I80312_INTC_F2IS 0x04 /* FIQ2 Interrupt Status */ 391 #define I80312_INTC_F1IS 0x08 /* FIQ1 Interrupt Status */ 392 /* not used 0x0c */ 393 #define I80312_INTC_PDI 0x10 /* Processor Device ID */ 394 /* not used 0x14 .. 0x18 */ 395 #define I80312_INTC_GOE 0x1c /* GPIO Output Enable */ 396 #define I80312_INTC_GID 0x20 /* GPIO Input Data */ 397 #define I80312_INTC_GOD 0x24 /* GPIO Output Data */ 398 /* not used 0x28 .. 0xfc */ 399 400 /* 401 * Application Accelerator Registers 402 */ 403 #define I80312_AAU_CTL 0x00 /* Control */ 404 #define I80312_AAU_STS 0x04 /* Status */ 405 #define I80312_AAU_DSCA 0x08 /* Descriptor Address */ 406 #define I80312_AAU_NDA 0x0c /* Next Descriptor Address */ 407 #define I80312_AAU_SA1 0x10 /* i80200 Source Address 1 */ 408 #define I80312_AAU_SA2 0x14 /* i80200 Source Address 2 */ 409 #define I80312_AAU_SA3 0x18 /* i80200 Source Address 3 */ 410 #define I80312_AAU_SA4 0x1c /* i80200 Source Address 4 */ 411 #define I80312_AAU_DSTA 0x20 /* i80200 Destination Address */ 412 #define I80312_AAU_ABC 0x24 /* Accelerator Byte Count */ 413 #define I80312_AAU_ADC 0x28 /* Accelerator Descriptor Count */ 414 #define I80312_AAU_SA5 0x2c /* i80200 Source Address 5 */ 415 #define I80312_AAU_SA6 0x30 /* i80200 Source Address 6 */ 416 #define I80312_AAU_SA7 0x34 /* i80200 Source Address 7 */ 417 #define I80312_AAU_SA8 0x38 /* i80200 Source Address 8 */ 418 /* not used 0x3c .. 0xfc */ 419 420 /* 421 * Physical addresses 0x00002000..0x7fffffff are used by the 422 * ATU Outbound Direct Addressing Window. 423 */ 424 #define I80312_PCI_DIRECT_BASE 0x00002000UL 425 #define I80312_PCI_DIRECT_SIZE 0x7fffe000UL 426 427 /* 428 * Physical addresses 0x80000000..0x9001ffff are used by the 429 * ATU Outbound Transaction Windows. 430 */ 431 #define I80312_PCI_XLATE_BASE 0x80000000UL 432 #define I80312_PCI_XLATE_SIZE 0x10020000UL 433 434 #define I80312_PCI_XLATE_MSIZE 0x04000000UL /* 64M */ 435 #define I80312_PCI_XLATE_IOSIZE 0x00010000UL /* 64K */ 436 437 #define I80312_PCI_XLATE_PMW_BASE (I80312_PCI_XLATE_BASE) 438 439 #define I80312_PCI_XLATE_PDW_BASE (I80312_PCI_XLATE_PMW_BASE + \ 440 I80312_PCI_XLATE_MSIZE) 441 442 #define I80312_PCI_XLATE_SMW_BASE (I80312_PCI_XLATE_PDW_BASE + \ 443 I80312_PCI_XLATE_MSIZE) 444 445 #define I80312_PCI_XLATE_SDW_BASE (I80312_PCI_XLATE_SMW_BASE + \ 446 I80312_PCI_XLATE_MSIZE) 447 448 #define I80312_PCI_XLATE_PIOW_BASE (I80312_PCI_XLATE_SDW_BASE + \ 449 I80312_PCI_XLATE_MSIZE) 450 451 #define I80312_PCI_XLATE_SIOW_BASE (I80312_PCI_XLATE_PIOW_BASE + \ 452 I80312_PCI_XLATE_IOSIZE) 453 454 #endif /* _ARM_XSCALE_I80312REG_H_ */ 455
Indexes created Mon Sep 22 13:09:51 GMT 2025