1 /* $NetBSD: cputypes.h,v 1.20 2025/01/31 11:47:34 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001 Ben Harris 5 * Copyright (c) 1994-1996 Mark Brinicombe. 6 * Copyright (c) 1994 Brini. 7 * All rights reserved. 8 * 9 * This code is derived from software written for Brini by Mark Brinicombe 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by Brini. 22 * 4. The name of the company nor the name of the author may be used to 23 * endorse or promote products derived from this software without specific 24 * prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 28 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 31 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 32 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 */ 38 39 #ifndef _ARM_CPUTYPES_H_ 40 #define _ARM_CPUTYPES_H_ 41 42 /* 43 * The CPU ID register is theoretically structured, but the definitions of 44 * the fields keep changing. 45 */ 46 47 /* The high-order byte is always the implementor */ 48 #define CPU_ID_IMPLEMENTOR_MASK 0xff000000 49 #define CPU_ID_ARM_LTD 0x41000000 /* 'A' */ 50 #define CPU_ID_BROADCOM 0x42000000 /* 'B' */ 51 #define CPU_ID_CAVIUM 0x43000000 /* 'C' */ 52 #define CPU_ID_DEC 0x44000000 /* 'D' */ 53 #define CPU_ID_FUJITSU 0x46000000 /* 'F' */ 54 #define CPU_ID_INFINEON 0x49000000 /* 'I' */ 55 #define CPU_ID_MOTOROLA 0x4d000000 /* 'M' */ 56 #define CPU_ID_NVIDIA 0x4e000000 /* 'N' */ 57 #define CPU_ID_APM 0x50000000 /* 'P' */ 58 #define CPU_ID_QUALCOMM 0x51000000 /* 'Q' */ 59 #define CPU_ID_SAMSUNG 0x53000000 /* 'S' */ 60 #define CPU_ID_TI 0x54000000 /* 'T' */ 61 #define CPU_ID_MARVELL 0x56000000 /* 'V' */ 62 #define CPU_ID_APPLE 0x61000000 /* 'a' */ 63 #define CPU_ID_FARADAY 0x66000000 /* 'f' */ 64 #define CPU_ID_INTEL 0x69000000 /* 'i' */ 65 #define CPU_ID_AMPERE 0xc0000000 /* '' */ 66 67 /* How to decide what format the CPUID is in. */ 68 #define CPU_ID_ISOLD(x) (((x) & 0x0000f000) == 0x00000000) 69 #define CPU_ID_IS7(x) (((x) & 0x0000f000) == 0x00007000) 70 #define CPU_ID_ISNEW(x) (!CPU_ID_ISOLD(x) && !CPU_ID_IS7(x)) 71 72 /* On ARM3 and ARM6, this byte holds the foundry ID. */ 73 #define CPU_ID_FOUNDRY_MASK 0x00ff0000 74 #define CPU_ID_FOUNDRY_VLSI 0x00560000 75 76 /* On ARM7 it holds the architecture and variant (sub-model) */ 77 #define CPU_ID_7ARCH_MASK 0x00800000 78 #define CPU_ID_7ARCH_V3 0x00000000 79 #define CPU_ID_7ARCH_V4T 0x00800000 80 #define CPU_ID_7VARIANT_MASK 0x007f0000 81 82 /* On more recent ARMs, it does the same, but in a different format */ 83 #define CPU_ID_ARCH_MASK 0x000f0000 84 #define CPU_ID_ARCH_V3 0x00000000 85 #define CPU_ID_ARCH_V4 0x00010000 86 #define CPU_ID_ARCH_V4T 0x00020000 87 #define CPU_ID_ARCH_V5 0x00030000 88 #define CPU_ID_ARCH_V5T 0x00040000 89 #define CPU_ID_ARCH_V5TE 0x00050000 90 #define CPU_ID_ARCH_V5TEJ 0x00060000 91 #define CPU_ID_ARCH_V6 0x00070000 92 #define CPU_ID_VARIANT_MASK 0x00f00000 93 94 /* Next three nybbles are part number */ 95 #define CPU_ID_PARTNO_MASK 0x0000fff0 96 97 /* Intel XScale has sub fields in part number */ 98 #define CPU_ID_XSCALE_COREGEN_MASK 0x0000e000 /* core generation */ 99 #define CPU_ID_XSCALE_COREREV_MASK 0x00001c00 /* core revision */ 100 #define CPU_ID_XSCALE_PRODUCT_MASK 0x000003f0 /* product number */ 101 102 /* And finally, the revision number. */ 103 #define CPU_ID_REVISION_MASK 0x0000000f 104 105 /* Individual CPUs are probably best IDed by everything but the revision. */ 106 #define CPU_ID_CPU_MASK 0xfffffff0 107 108 /* Fake CPU IDs for ARMs without CP15 */ 109 #define CPU_ID_ARM2 0x41560200 110 #define CPU_ID_ARM250 0x41560250 111 112 /* Pre-ARM7 CPUs -- [15:12] == 0 */ 113 #define CPU_ID_ARM3 0x41560300 114 #define CPU_ID_ARM600 0x41560600 115 #define CPU_ID_ARM610 0x41560610 116 #define CPU_ID_ARM620 0x41560620 117 118 /* ARM7 CPUs -- [15:12] == 7 */ 119 #define CPU_ID_ARM700 0x41007000 /* XXX This is a guess. */ 120 #define CPU_ID_ARM710 0x41007100 121 #define CPU_ID_ARM7500 0x41027100 122 #define CPU_ID_ARM710A 0x41067100 123 #define CPU_ID_ARM7500FE 0x41077100 124 #define CPU_ID_ARM710T 0x41807100 125 #define CPU_ID_ARM720T 0x41807200 126 #define CPU_ID_ARM740T8K 0x41807400 /* XXX no MMU, 8KB cache */ 127 #define CPU_ID_ARM740T4K 0x41817400 /* XXX no MMU, 4KB cache */ 128 129 /* Post-ARM7 CPUs */ 130 #define CPU_ID_ARM810 0x41018100 131 #define CPU_ID_ARM920T 0x41129200 132 #define CPU_ID_ARM922T 0x41029220 133 #define CPU_ID_ARM926EJS 0x41069260 134 #define CPU_ID_ARM940T 0x41029400 /* XXX no MMU */ 135 #define CPU_ID_ARM946ES 0x41049460 /* XXX no MMU */ 136 #define CPU_ID_ARM966ES 0x41049660 /* XXX no MMU */ 137 #define CPU_ID_ARM966ESR1 0x41059660 /* XXX no MMU */ 138 #define CPU_ID_ARM1020E 0x4115a200 /* (AKA arm10 rev 1) */ 139 #define CPU_ID_ARM1022ES 0x4105a220 140 #define CPU_ID_ARM1026EJS 0x4106a260 141 #define CPU_ID_ARM11MPCORE 0x410fb020 142 #define CPU_ID_ARM1136JS 0x4107b360 143 #define CPU_ID_ARM1136JSR1 0x4117b360 144 #define CPU_ID_ARM1156T2S 0x4107b560 /* MPU only */ 145 #define CPU_ID_ARM1176JZS 0x410fb760 146 #define CPU_ID_ARM11_P(n) ((n & 0xff07f000) == 0x4107b000) 147 148 /* ARMv7 CPUs */ 149 #define CPU_ID_CORTEXA5R0 0x410fc050 150 #define CPU_ID_CORTEXA7R0 0x410fc070 151 #define CPU_ID_CORTEXA8R1 0x411fc080 152 #define CPU_ID_CORTEXA8R2 0x412fc080 153 #define CPU_ID_CORTEXA8R3 0x413fc080 154 #define CPU_ID_CORTEXA9R1 0x411fc090 155 #define CPU_ID_CORTEXA9R2 0x412fc090 156 #define CPU_ID_CORTEXA9R3 0x413fc090 157 #define CPU_ID_CORTEXA9R4 0x414fc090 158 #define CPU_ID_CORTEXA12R0 0x410fc0d0 159 #define CPU_ID_CORTEXA15R2 0x412fc0f0 160 #define CPU_ID_CORTEXA15R3 0x413fc0f0 161 #define CPU_ID_CORTEXA15R4 0x414fc0f0 162 #define CPU_ID_CORTEXA17R1 0x411fc0e0 163 164 /* ARMv8 CPUS */ 165 #define CPU_ID_CORTEXA32R1 0x411fd010 166 #define CPU_ID_CORTEXA35R0 0x410fd040 167 #define CPU_ID_CORTEXA35R1 0x411fd040 168 #define CPU_ID_CORTEXA53R0 0x410fd030 169 #define CPU_ID_CORTEXA55R1 0x411fd050 170 #define CPU_ID_CORTEXA57R0 0x410fd070 171 #define CPU_ID_CORTEXA57R1 0x411fd070 172 #define CPU_ID_CORTEXA65R0 0x410fd060 173 #define CPU_ID_CORTEXA72R0 0x410fd080 174 #define CPU_ID_CORTEXA73R0 0x410fd090 175 #define CPU_ID_CORTEXA75R2 0x412fd0a0 176 #define CPU_ID_CORTEXA76AER1 0x411fd0e0 177 #define CPU_ID_CORTEXA76R3 0x413fd0b0 178 #define CPU_ID_NEOVERSEN1R3 0x413fd0c0 179 #define CPU_ID_NEOVERSEE1R1 0x411fd4a0 180 #define CPU_ID_CORTEXA77R0 0x410fd0d0 181 #define CPU_ID_NEOVERSEV1R1 0x411fd400 182 #define CPU_ID_CORTEXA710R2 0x412fd470 183 #define CPU_ID_NEOVERSEN2R0 0x410fd490 184 #define CPU_ID_CORTEXA520R0 0x410fd800 185 #define CPU_ID_CORTEXA720R0 0x410fd810 186 187 #define CPU_ID_CORTEX_P(n) ((n & 0xff0fe000) == 0x410fc000) 188 #define CPU_ID_CORTEX_A5_P(n) ((n & 0xff0ff0f0) == 0x410fc050) 189 #define CPU_ID_CORTEX_A7_P(n) ((n & 0xff0ff0f0) == 0x410fc070) 190 #define CPU_ID_CORTEX_A8_P(n) ((n & 0xff0ff0f0) == 0x410fc080) 191 #define CPU_ID_CORTEX_A9_P(n) ((n & 0xff0ff0f0) == 0x410fc090) 192 #define CPU_ID_CORTEX_A12_P(n) ((n & 0xff0ff0f0) == 0x410fc0d0) 193 #define CPU_ID_CORTEX_A15_P(n) ((n & 0xff0ff0f0) == 0x410fc0f0) 194 #define CPU_ID_CORTEX_A17_P(n) ((n & 0xff0ff0f0) == 0x410fc0e0) 195 #define CPU_ID_CORTEX_A32_P(n) ((n & 0xff0ff0f0) == 0x410fd010) 196 #define CPU_ID_CORTEX_A35_P(n) ((n & 0xff0ff0f0) == 0x410fd040) 197 #define CPU_ID_CORTEX_A53_P(n) ((n & 0xff0ff0f0) == 0x410fd030) 198 #define CPU_ID_CORTEX_A55_P(n) ((n & 0xff0ff0f0) == 0x410fd050) 199 #define CPU_ID_CORTEX_A57_P(n) ((n & 0xff0ff0f0) == 0x410fd070) 200 #define CPU_ID_CORTEX_A65_P(n) ((n & 0xff0ff0f0) == 0x410fd060) 201 #define CPU_ID_CORTEX_A72_P(n) ((n & 0xff0ff0f0) == 0x410fd080) 202 #define CPU_ID_CORTEX_A73_P(n) ((n & 0xff0ff0f0) == 0x410fd090) 203 #define CPU_ID_CORTEX_A75_P(n) ((n & 0xff0ff0f0) == 0x410fd0a0) 204 #define CPU_ID_CORTEX_A76_P(n) ((n & 0xff0ff0f0) == 0x410fd0b0) 205 #define CPU_ID_CORTEX_A76AE_P(n) ((n & 0xff0ff0f0) == 0x410fd0e0) 206 #define CPU_ID_CORTEX_A77_P(n) ((n & 0xff0ff0f0) == 0x410fd0f0) 207 208 #define CPU_ID_NEOVERSEN1_P(n) ((n & 0xff0ffff0) == 0x410fd0c0) 209 210 #define CPU_ID_THUNDERXRX 0x43000a10 211 #define CPU_ID_THUNDERXP1d0 0x43000a10 212 #define CPU_ID_THUNDERXP1d1 0x43000a11 213 #define CPU_ID_THUNDERXP2d1 0x431f0a11 214 #define CPU_ID_THUNDERX81XXRX 0x43000a20 215 #define CPU_ID_THUNDERX83XXRX 0x43000a30 216 #define CPU_ID_THUNDERX2RX 0x43000af0 217 218 #define CPU_ID_A64FX 0x460f0010 219 220 #define CPU_ID_AMPERE1 0xc00fac30 221 #define CPU_ID_AMPERE1A 0xc00fac40 222 223 #define CPU_ID_ORYON 0x510f0010 224 #define CPU_ID_ORYON_P(n) ((n & 0xff0ffff0) == CPU_ID_ORYON) 225 226 /* 227 * Chip-specific errata. These defines are intended to be 228 * booleans used within if statements. When an appropriate 229 * kernel option is disabled, these defines must be defined 230 * as 0 to allow the compiler to remove a dead code thus 231 * produce better optimized kernel image. 232 */ 233 /* 234 * Vendor: Cavium 235 * Chip: ThunderX 236 * Revision(s): Pass 1.0, Pass 1.1 237 */ 238 #define CPU_ID_ERRATA_CAVIUM_THUNDERX_1_1_P(n) \ 239 (((n) & 0xfff0ffff) == CPU_ID_THUNDERXP1d0 || \ 240 ((n) & 0xfff0ffff) == CPU_ID_THUNDERXP1d1) 241 242 #define CPU_ID_APPLE_M1_ICESTORM 0x61000220 243 #define CPU_ID_APPLE_M1_FIRESTORM 0x61000230 244 245 #define CPU_ID_SA110 0x4401a100 246 #define CPU_ID_SA1100 0x4401a110 247 #define CPU_ID_NVIDIADENVER2 0x4e0f0030 248 #define CPU_ID_EMAG8180 0x503f0002 249 #define CPU_ID_TI925T 0x54029250 250 #define CPU_ID_MV88FR571_VD 0x56155710 251 #define CPU_ID_MV88SV131 0x56251310 252 #define CPU_ID_FA526 0x66015260 253 #define CPU_ID_SA1110 0x6901b110 254 #define CPU_ID_IXP1200 0x6901c120 255 #define CPU_ID_80200 0x69052000 256 #define CPU_ID_PXA250 0x69052100 /* sans core revision */ 257 #define CPU_ID_PXA210 0x69052120 258 #define CPU_ID_PXA250A 0x69052100 /* 1st version Core */ 259 #define CPU_ID_PXA210A 0x69052120 /* 1st version Core */ 260 #define CPU_ID_PXA250B 0x69052900 /* 3rd version Core */ 261 #define CPU_ID_PXA210B 0x69052920 /* 3rd version Core */ 262 #define CPU_ID_PXA250C 0x69052d00 /* 4th version Core */ 263 #define CPU_ID_PXA210C 0x69052d20 /* 4th version Core */ 264 #define CPU_ID_PXA27X 0x69054110 265 #define CPU_ID_80321_400 0x69052420 266 #define CPU_ID_80321_600 0x69052430 267 #define CPU_ID_80321_400_B0 0x69052c20 268 #define CPU_ID_80321_600_B0 0x69052c30 269 #define CPU_ID_80219_400 0x69052e20 270 #define CPU_ID_80219_600 0x69052e30 271 #define CPU_ID_IXP425_533 0x690541c0 272 #define CPU_ID_IXP425_400 0x690541d0 273 #define CPU_ID_IXP425_266 0x690541f0 274 #define CPU_ID_MV88SV58XX_P(n) ((n & 0xff0fff00) == 0x560f5800) 275 #define CPU_ID_MV88SV581X_V6 0x560f5810 /* Marvell Sheeva 88SV581x v6 Core */ 276 #define CPU_ID_MV88SV581X_V7 0x561f5810 /* Marvell Sheeva 88SV581x v7 Core */ 277 #define CPU_ID_MV88SV584X_V6 0x561f5840 /* Marvell Sheeva 88SV584x v6 Core */ 278 #define CPU_ID_MV88SV584X_V7 0x562f5840 /* Marvell Sheeva 88SV584x v7 Core */ 279 /* Marvell's CPUIDs with ARM ID in implementor field */ 280 #define CPU_ID_ARM_88SV581X_V6 0x410fb760 /* Marvell Sheeva 88SV581x v6 Core */ 281 #define CPU_ID_ARM_88SV581X_V7 0x413fc080 /* Marvell Sheeva 88SV581x v7 Core */ 282 #define CPU_ID_ARM_88SV584X_V6 0x410fb020 /* Marvell Sheeva 88SV584x v6 Core */ 283 284 #endif /* _ARM_CPUTYPES_H_ */ 285
Indexes created Sat Sep 20 22:09:52 GMT 2025