1 /* $NetBSD: rv515d.h,v 1.3 2021/12/18 23:45:43 riastradh Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 #ifndef __RV515D_H__ 31 #define __RV515D_H__ 32 33 /* 34 * RV515 registers 35 */ 36 #define PCIE_INDEX 0x0030 37 #define PCIE_DATA 0x0034 38 #define MC_IND_INDEX 0x0070 39 #define MC_IND_WR_EN (1 << 24) 40 #define MC_IND_DATA 0x0074 41 #define RBBM_SOFT_RESET 0x00F0 42 #define CONFIG_MEMSIZE 0x00F8 43 #define HDP_FB_LOCATION 0x0134 44 #define CP_CSQ_CNTL 0x0740 45 #define CP_CSQ_MODE 0x0744 46 #define CP_CSQ_ADDR 0x07F0 47 #define CP_CSQ_DATA 0x07F4 48 #define CP_CSQ_STAT 0x07F8 49 #define CP_CSQ2_STAT 0x07FC 50 #define RBBM_STATUS 0x0E40 51 #define DST_PIPE_CONFIG 0x170C 52 #define WAIT_UNTIL 0x1720 53 #define WAIT_2D_IDLE (1 << 14) 54 #define WAIT_3D_IDLE (1 << 15) 55 #define WAIT_2D_IDLECLEAN (1 << 16) 56 #define WAIT_3D_IDLECLEAN (1 << 17) 57 #define ISYNC_CNTL 0x1724 58 #define ISYNC_ANY2D_IDLE3D (1 << 0) 59 #define ISYNC_ANY3D_IDLE2D (1 << 1) 60 #define ISYNC_TRIG2D_IDLE3D (1 << 2) 61 #define ISYNC_TRIG3D_IDLE2D (1 << 3) 62 #define ISYNC_WAIT_IDLEGUI (1 << 4) 63 #define ISYNC_CPSCRATCH_IDLEGUI (1 << 5) 64 #define VAP_INDEX_OFFSET 0x208C 65 #define VAP_PVS_STATE_FLUSH_REG 0x2284 66 #define GB_ENABLE 0x4008 67 #define GB_MSPOS0 0x4010 68 #define MS_X0_SHIFT 0 69 #define MS_Y0_SHIFT 4 70 #define MS_X1_SHIFT 8 71 #define MS_Y1_SHIFT 12 72 #define MS_X2_SHIFT 16 73 #define MS_Y2_SHIFT 20 74 #define MSBD0_Y_SHIFT 24 75 #define MSBD0_X_SHIFT 28 76 #define GB_MSPOS1 0x4014 77 #define MS_X3_SHIFT 0 78 #define MS_Y3_SHIFT 4 79 #define MS_X4_SHIFT 8 80 #define MS_Y4_SHIFT 12 81 #define MS_X5_SHIFT 16 82 #define MS_Y5_SHIFT 20 83 #define MSBD1_SHIFT 24 84 #define GB_TILE_CONFIG 0x4018 85 #define ENABLE_TILING (1 << 0) 86 #define PIPE_COUNT_MASK 0x0000000E 87 #define PIPE_COUNT_SHIFT 1 88 #define TILE_SIZE_8 (0 << 4) 89 #define TILE_SIZE_16 (1 << 4) 90 #define TILE_SIZE_32 (2 << 4) 91 #define SUBPIXEL_1_12 (0 << 16) 92 #define SUBPIXEL_1_16 (1 << 16) 93 #define GB_SELECT 0x401C 94 #define GB_AA_CONFIG 0x4020 95 #define GB_PIPE_SELECT 0x402C 96 #define GA_ENHANCE 0x4274 97 #define GA_DEADLOCK_CNTL (1 << 0) 98 #define GA_FASTSYNC_CNTL (1 << 1) 99 #define GA_POLY_MODE 0x4288 100 #define FRONT_PTYPE_POINT (0 << 4) 101 #define FRONT_PTYPE_LINE (1 << 4) 102 #define FRONT_PTYPE_TRIANGE (2 << 4) 103 #define BACK_PTYPE_POINT (0 << 7) 104 #define BACK_PTYPE_LINE (1 << 7) 105 #define BACK_PTYPE_TRIANGE (2 << 7) 106 #define GA_ROUND_MODE 0x428C 107 #define GEOMETRY_ROUND_TRUNC (0 << 0) 108 #define GEOMETRY_ROUND_NEAREST (1 << 0) 109 #define COLOR_ROUND_TRUNC (0 << 2) 110 #define COLOR_ROUND_NEAREST (1 << 2) 111 #define SU_REG_DEST 0x42C8 112 #define RB3D_DSTCACHE_CTLSTAT 0x4E4C 113 #define RB3D_DC_FLUSH (2 << 0) 114 #define RB3D_DC_FREE (2 << 2) 115 #define RB3D_DC_FINISH (1 << 4) 116 #define ZB_ZCACHE_CTLSTAT 0x4F18 117 #define ZC_FLUSH (1 << 0) 118 #define ZC_FREE (1 << 1) 119 #define DC_LB_MEMORY_SPLIT 0x6520 120 #define DC_LB_MEMORY_SPLIT_MASK 0x00000003 121 #define DC_LB_MEMORY_SPLIT_SHIFT 0 122 #define DC_LB_MEMORY_SPLIT_D1HALF_D2HALF 0 123 #define DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q 1 124 #define DC_LB_MEMORY_SPLIT_D1_ONLY 2 125 #define DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q 3 126 #define DC_LB_MEMORY_SPLIT_SHIFT_MODE (1 << 2) 127 #define DC_LB_DISP1_END_ADR_SHIFT 4 128 #define DC_LB_DISP1_END_ADR_MASK 0x00007FF0 129 #define D1MODE_PRIORITY_A_CNT 0x6548 130 #define MODE_PRIORITY_MARK_MASK 0x00007FFF 131 #define MODE_PRIORITY_OFF (1 << 16) 132 #define MODE_PRIORITY_ALWAYS_ON (1 << 20) 133 #define MODE_PRIORITY_FORCE_MASK (1 << 24) 134 #define D1MODE_PRIORITY_B_CNT 0x654C 135 #define LB_MAX_REQ_OUTSTANDING 0x6D58 136 #define LB_D1_MAX_REQ_OUTSTANDING_MASK 0x0000000F 137 #define LB_D1_MAX_REQ_OUTSTANDING_SHIFT 0 138 #define LB_D2_MAX_REQ_OUTSTANDING_MASK 0x000F0000 139 #define LB_D2_MAX_REQ_OUTSTANDING_SHIFT 16 140 #define D2MODE_PRIORITY_A_CNT 0x6D48 141 #define D2MODE_PRIORITY_B_CNT 0x6D4C 142 143 /* ix[MC] registers */ 144 #define MC_FB_LOCATION 0x01 145 #define MC_FB_START_MASK 0x0000FFFF 146 #define MC_FB_START_SHIFT 0 147 #define MC_FB_TOP_MASK 0xFFFF0000 148 #define MC_FB_TOP_SHIFT 16 149 #define MC_AGP_LOCATION 0x02 150 #define MC_AGP_START_MASK 0x0000FFFF 151 #define MC_AGP_START_SHIFT 0 152 #define MC_AGP_TOP_MASK 0xFFFF0000 153 #define MC_AGP_TOP_SHIFT 16 154 #define MC_AGP_BASE 0x03 155 #define MC_AGP_BASE_2 0x04 156 #define MC_CNTL 0x5 157 #define MEM_NUM_CHANNELS_MASK 0x00000003 158 #define MC_STATUS 0x08 159 #define MC_STATUS_IDLE (1 << 4) 160 #define MC_MISC_LAT_TIMER 0x09 161 #define MC_CPR_INIT_LAT_MASK 0x0000000F 162 #define MC_VF_INIT_LAT_MASK 0x000000F0 163 #define MC_DISP0R_INIT_LAT_MASK 0x00000F00 164 #define MC_DISP0R_INIT_LAT_SHIFT 8 165 #define MC_DISP1R_INIT_LAT_MASK 0x0000F000 166 #define MC_DISP1R_INIT_LAT_SHIFT 12 167 #define MC_FIXED_INIT_LAT_MASK 0x000F0000 168 #define MC_E2R_INIT_LAT_MASK 0x00F00000 169 #define SAME_PAGE_PRIO_MASK 0x0F000000 170 #define MC_GLOBW_INIT_LAT_MASK 0xF0000000 171 172 173 /* 174 * PM4 packet 175 */ 176 #define CP_PACKET0 0x00000000 177 #define PACKET0_BASE_INDEX_SHIFT 0 178 #define PACKET0_BASE_INDEX_MASK (0x1ffff << 0) 179 #define PACKET0_COUNT_SHIFT 16 180 #define PACKET0_COUNT_MASK (0x3fff << 16) 181 #define CP_PACKET1 0x40000000 182 #define CP_PACKET2 0x80000000 183 #define PACKET2_PAD_SHIFT 0 184 #define PACKET2_PAD_MASK (0x3fffffff << 0) 185 #define CP_PACKET3 0xC0000000 186 #define PACKET3_IT_OPCODE_SHIFT 8 187 #define PACKET3_IT_OPCODE_MASK (0xff << 8) 188 #define PACKET3_COUNT_SHIFT 16 189 #define PACKET3_COUNT_MASK (0x3fff << 16) 190 /* PACKET3 op code */ 191 #define PACKET3_NOP 0x10 192 #define PACKET3_3D_DRAW_VBUF 0x28 193 #define PACKET3_3D_DRAW_IMMD 0x29 194 #define PACKET3_3D_DRAW_INDX 0x2A 195 #define PACKET3_3D_LOAD_VBPNTR 0x2F 196 #define PACKET3_INDX_BUFFER 0x33 197 #define PACKET3_3D_DRAW_VBUF_2 0x34 198 #define PACKET3_3D_DRAW_IMMD_2 0x35 199 #define PACKET3_3D_DRAW_INDX_2 0x36 200 #define PACKET3_BITBLT_MULTI 0x9B 201 202 #define PACKET0(reg, n) (CP_PACKET0 | \ 203 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \ 204 REG_SET(PACKET0_COUNT, (n))) 205 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 206 #define PACKET3(op, n) (CP_PACKET3 | \ 207 REG_SET(PACKET3_IT_OPCODE, (op)) | \ 208 REG_SET(PACKET3_COUNT, (n))) 209 210 /* Registers */ 211 #define R_0000F0_RBBM_SOFT_RESET 0x0000F0 212 #define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0) 213 #define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1) 214 #define C_0000F0_SOFT_RESET_CP 0xFFFFFFFE 215 #define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1) 216 #define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1) 217 #define C_0000F0_SOFT_RESET_HI 0xFFFFFFFD 218 #define S_0000F0_SOFT_RESET_VAP(x) (((x) & 0x1) << 2) 219 #define G_0000F0_SOFT_RESET_VAP(x) (((x) >> 2) & 0x1) 220 #define C_0000F0_SOFT_RESET_VAP 0xFFFFFFFB 221 #define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3) 222 #define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1) 223 #define C_0000F0_SOFT_RESET_RE 0xFFFFFFF7 224 #define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4) 225 #define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1) 226 #define C_0000F0_SOFT_RESET_PP 0xFFFFFFEF 227 #define S_0000F0_SOFT_RESET_E2(x) (((x) & 0x1) << 5) 228 #define G_0000F0_SOFT_RESET_E2(x) (((x) >> 5) & 0x1) 229 #define C_0000F0_SOFT_RESET_E2 0xFFFFFFDF 230 #define S_0000F0_SOFT_RESET_RB(x) (((x) & 0x1) << 6) 231 #define G_0000F0_SOFT_RESET_RB(x) (((x) >> 6) & 0x1) 232 #define C_0000F0_SOFT_RESET_RB 0xFFFFFFBF 233 #define S_0000F0_SOFT_RESET_HDP(x) (((x) & 0x1) << 7) 234 #define G_0000F0_SOFT_RESET_HDP(x) (((x) >> 7) & 0x1) 235 #define C_0000F0_SOFT_RESET_HDP 0xFFFFFF7F 236 #define S_0000F0_SOFT_RESET_MC(x) (((x) & 0x1) << 8) 237 #define G_0000F0_SOFT_RESET_MC(x) (((x) >> 8) & 0x1) 238 #define C_0000F0_SOFT_RESET_MC 0xFFFFFEFF 239 #define S_0000F0_SOFT_RESET_AIC(x) (((x) & 0x1) << 9) 240 #define G_0000F0_SOFT_RESET_AIC(x) (((x) >> 9) & 0x1) 241 #define C_0000F0_SOFT_RESET_AIC 0xFFFFFDFF 242 #define S_0000F0_SOFT_RESET_VIP(x) (((x) & 0x1) << 10) 243 #define G_0000F0_SOFT_RESET_VIP(x) (((x) >> 10) & 0x1) 244 #define C_0000F0_SOFT_RESET_VIP 0xFFFFFBFF 245 #define S_0000F0_SOFT_RESET_DISP(x) (((x) & 0x1) << 11) 246 #define G_0000F0_SOFT_RESET_DISP(x) (((x) >> 11) & 0x1) 247 #define C_0000F0_SOFT_RESET_DISP 0xFFFFF7FF 248 #define S_0000F0_SOFT_RESET_CG(x) (((x) & 0x1) << 12) 249 #define G_0000F0_SOFT_RESET_CG(x) (((x) >> 12) & 0x1) 250 #define C_0000F0_SOFT_RESET_CG 0xFFFFEFFF 251 #define S_0000F0_SOFT_RESET_GA(x) (((x) & 0x1) << 13) 252 #define G_0000F0_SOFT_RESET_GA(x) (((x) >> 13) & 0x1) 253 #define C_0000F0_SOFT_RESET_GA 0xFFFFDFFF 254 #define S_0000F0_SOFT_RESET_IDCT(x) (((x) & 0x1) << 14) 255 #define G_0000F0_SOFT_RESET_IDCT(x) (((x) >> 14) & 0x1) 256 #define C_0000F0_SOFT_RESET_IDCT 0xFFFFBFFF 257 #define R_0000F8_CONFIG_MEMSIZE 0x0000F8 258 #define S_0000F8_CONFIG_MEMSIZE(x) (((x) & 0xFFFFFFFF) << 0) 259 #define G_0000F8_CONFIG_MEMSIZE(x) (((x) >> 0) & 0xFFFFFFFF) 260 #define C_0000F8_CONFIG_MEMSIZE 0x00000000 261 #define R_000134_HDP_FB_LOCATION 0x000134 262 #define S_000134_HDP_FB_START(x) (((x) & 0xFFFF) << 0) 263 #define G_000134_HDP_FB_START(x) (((x) >> 0) & 0xFFFF) 264 #define C_000134_HDP_FB_START 0xFFFF0000 265 #define R_000300_VGA_RENDER_CONTROL 0x000300 266 #define S_000300_VGA_BLINK_RATE(x) (((x) & 0x1F) << 0) 267 #define G_000300_VGA_BLINK_RATE(x) (((x) >> 0) & 0x1F) 268 #define C_000300_VGA_BLINK_RATE 0xFFFFFFE0 269 #define S_000300_VGA_BLINK_MODE(x) (((x) & 0x3) << 5) 270 #define G_000300_VGA_BLINK_MODE(x) (((x) >> 5) & 0x3) 271 #define C_000300_VGA_BLINK_MODE 0xFFFFFF9F 272 #define S_000300_VGA_CURSOR_BLINK_INVERT(x) (((x) & 0x1) << 7) 273 #define G_000300_VGA_CURSOR_BLINK_INVERT(x) (((x) >> 7) & 0x1) 274 #define C_000300_VGA_CURSOR_BLINK_INVERT 0xFFFFFF7F 275 #define S_000300_VGA_EXTD_ADDR_COUNT_ENABLE(x) (((x) & 0x1) << 8) 276 #define G_000300_VGA_EXTD_ADDR_COUNT_ENABLE(x) (((x) >> 8) & 0x1) 277 #define C_000300_VGA_EXTD_ADDR_COUNT_ENABLE 0xFFFFFEFF 278 #define S_000300_VGA_VSTATUS_CNTL(x) (((x) & 0x3) << 16) 279 #define G_000300_VGA_VSTATUS_CNTL(x) (((x) >> 16) & 0x3) 280 #define C_000300_VGA_VSTATUS_CNTL 0xFFFCFFFF 281 #define S_000300_VGA_LOCK_8DOT(x) (((x) & 0x1) << 24) 282 #define G_000300_VGA_LOCK_8DOT(x) (((x) >> 24) & 0x1) 283 #define C_000300_VGA_LOCK_8DOT 0xFEFFFFFF 284 #define S_000300_VGAREG_LINECMP_COMPATIBILITY_SEL(x) (((x) & 0x1) << 25) 285 #define G_000300_VGAREG_LINECMP_COMPATIBILITY_SEL(x) (((x) >> 25) & 0x1) 286 #define C_000300_VGAREG_LINECMP_COMPATIBILITY_SEL 0xFDFFFFFF 287 #define R_000310_VGA_MEMORY_BASE_ADDRESS 0x000310 288 #define S_000310_VGA_MEMORY_BASE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) 289 #define G_000310_VGA_MEMORY_BASE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) 290 #define C_000310_VGA_MEMORY_BASE_ADDRESS 0x00000000 291 #define R_000328_VGA_HDP_CONTROL 0x000328 292 #define S_000328_VGA_MEM_PAGE_SELECT_EN(x) (((x) & 0x1) << 0) 293 #define G_000328_VGA_MEM_PAGE_SELECT_EN(x) (((x) >> 0) & 0x1) 294 #define C_000328_VGA_MEM_PAGE_SELECT_EN 0xFFFFFFFE 295 #define S_000328_VGA_RBBM_LOCK_DISABLE(x) (((x) & 0x1) << 8) 296 #define G_000328_VGA_RBBM_LOCK_DISABLE(x) (((x) >> 8) & 0x1) 297 #define C_000328_VGA_RBBM_LOCK_DISABLE 0xFFFFFEFF 298 #define S_000328_VGA_SOFT_RESET(x) (((x) & 0x1) << 16) 299 #define G_000328_VGA_SOFT_RESET(x) (((x) >> 16) & 0x1) 300 #define C_000328_VGA_SOFT_RESET 0xFFFEFFFF 301 #define S_000328_VGA_TEST_RESET_CONTROL(x) (((x) & 0x1) << 24) 302 #define G_000328_VGA_TEST_RESET_CONTROL(x) (((x) >> 24) & 0x1) 303 #define C_000328_VGA_TEST_RESET_CONTROL 0xFEFFFFFF 304 #define R_000330_D1VGA_CONTROL 0x000330 305 #define S_000330_D1VGA_MODE_ENABLE(x) (((x) & 0x1) << 0) 306 #define G_000330_D1VGA_MODE_ENABLE(x) (((x) >> 0) & 0x1) 307 #define C_000330_D1VGA_MODE_ENABLE 0xFFFFFFFE 308 #define S_000330_D1VGA_TIMING_SELECT(x) (((x) & 0x1) << 8) 309 #define G_000330_D1VGA_TIMING_SELECT(x) (((x) >> 8) & 0x1) 310 #define C_000330_D1VGA_TIMING_SELECT 0xFFFFFEFF 311 #define S_000330_D1VGA_SYNC_POLARITY_SELECT(x) (((x) & 0x1) << 9) 312 #define G_000330_D1VGA_SYNC_POLARITY_SELECT(x) (((x) >> 9) & 0x1) 313 #define C_000330_D1VGA_SYNC_POLARITY_SELECT 0xFFFFFDFF 314 #define S_000330_D1VGA_OVERSCAN_TIMING_SELECT(x) (((x) & 0x1) << 10) 315 #define G_000330_D1VGA_OVERSCAN_TIMING_SELECT(x) (((x) >> 10) & 0x1) 316 #define C_000330_D1VGA_OVERSCAN_TIMING_SELECT 0xFFFFFBFF 317 #define S_000330_D1VGA_OVERSCAN_COLOR_EN(x) (((x) & 0x1) << 16) 318 #define G_000330_D1VGA_OVERSCAN_COLOR_EN(x) (((x) >> 16) & 0x1) 319 #define C_000330_D1VGA_OVERSCAN_COLOR_EN 0xFFFEFFFF 320 #define S_000330_D1VGA_ROTATE(x) (((x) & 0x3) << 24) 321 #define G_000330_D1VGA_ROTATE(x) (((x) >> 24) & 0x3) 322 #define C_000330_D1VGA_ROTATE 0xFCFFFFFF 323 #define R_000338_D2VGA_CONTROL 0x000338 324 #define S_000338_D2VGA_MODE_ENABLE(x) (((x) & 0x1) << 0) 325 #define G_000338_D2VGA_MODE_ENABLE(x) (((x) >> 0) & 0x1) 326 #define C_000338_D2VGA_MODE_ENABLE 0xFFFFFFFE 327 #define S_000338_D2VGA_TIMING_SELECT(x) (((x) & 0x1) << 8) 328 #define G_000338_D2VGA_TIMING_SELECT(x) (((x) >> 8) & 0x1) 329 #define C_000338_D2VGA_TIMING_SELECT 0xFFFFFEFF 330 #define S_000338_D2VGA_SYNC_POLARITY_SELECT(x) (((x) & 0x1) << 9) 331 #define G_000338_D2VGA_SYNC_POLARITY_SELECT(x) (((x) >> 9) & 0x1) 332 #define C_000338_D2VGA_SYNC_POLARITY_SELECT 0xFFFFFDFF 333 #define S_000338_D2VGA_OVERSCAN_TIMING_SELECT(x) (((x) & 0x1) << 10) 334 #define G_000338_D2VGA_OVERSCAN_TIMING_SELECT(x) (((x) >> 10) & 0x1) 335 #define C_000338_D2VGA_OVERSCAN_TIMING_SELECT 0xFFFFFBFF 336 #define S_000338_D2VGA_OVERSCAN_COLOR_EN(x) (((x) & 0x1) << 16) 337 #define G_000338_D2VGA_OVERSCAN_COLOR_EN(x) (((x) >> 16) & 0x1) 338 #define C_000338_D2VGA_OVERSCAN_COLOR_EN 0xFFFEFFFF 339 #define S_000338_D2VGA_ROTATE(x) (((x) & 0x3) << 24) 340 #define G_000338_D2VGA_ROTATE(x) (((x) >> 24) & 0x3) 341 #define C_000338_D2VGA_ROTATE 0xFCFFFFFF 342 #define R_0007C0_CP_STAT 0x0007C0 343 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) 344 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) 345 #define C_0007C0_MRU_BUSY 0xFFFFFFFE 346 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) 347 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) 348 #define C_0007C0_MWU_BUSY 0xFFFFFFFD 349 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) 350 #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) 351 #define C_0007C0_RSIU_BUSY 0xFFFFFFFB 352 #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3) 353 #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1) 354 #define C_0007C0_RCIU_BUSY 0xFFFFFFF7 355 #define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9) 356 #define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1) 357 #define C_0007C0_CSF_PRIMARY_BUSY 0xFFFFFDFF 358 #define S_0007C0_CSF_INDIRECT_BUSY(x) (((x) & 0x1) << 10) 359 #define G_0007C0_CSF_INDIRECT_BUSY(x) (((x) >> 10) & 0x1) 360 #define C_0007C0_CSF_INDIRECT_BUSY 0xFFFFFBFF 361 #define S_0007C0_CSQ_PRIMARY_BUSY(x) (((x) & 0x1) << 11) 362 #define G_0007C0_CSQ_PRIMARY_BUSY(x) (((x) >> 11) & 0x1) 363 #define C_0007C0_CSQ_PRIMARY_BUSY 0xFFFFF7FF 364 #define S_0007C0_CSQ_INDIRECT_BUSY(x) (((x) & 0x1) << 12) 365 #define G_0007C0_CSQ_INDIRECT_BUSY(x) (((x) >> 12) & 0x1) 366 #define C_0007C0_CSQ_INDIRECT_BUSY 0xFFFFEFFF 367 #define S_0007C0_CSI_BUSY(x) (((x) & 0x1) << 13) 368 #define G_0007C0_CSI_BUSY(x) (((x) >> 13) & 0x1) 369 #define C_0007C0_CSI_BUSY 0xFFFFDFFF 370 #define S_0007C0_CSF_INDIRECT2_BUSY(x) (((x) & 0x1) << 14) 371 #define G_0007C0_CSF_INDIRECT2_BUSY(x) (((x) >> 14) & 0x1) 372 #define C_0007C0_CSF_INDIRECT2_BUSY 0xFFFFBFFF 373 #define S_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) & 0x1) << 15) 374 #define G_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) >> 15) & 0x1) 375 #define C_0007C0_CSQ_INDIRECT2_BUSY 0xFFFF7FFF 376 #define S_0007C0_GUIDMA_BUSY(x) (((x) & 0x1) << 28) 377 #define G_0007C0_GUIDMA_BUSY(x) (((x) >> 28) & 0x1) 378 #define C_0007C0_GUIDMA_BUSY 0xEFFFFFFF 379 #define S_0007C0_VIDDMA_BUSY(x) (((x) & 0x1) << 29) 380 #define G_0007C0_VIDDMA_BUSY(x) (((x) >> 29) & 0x1) 381 #define C_0007C0_VIDDMA_BUSY 0xDFFFFFFF 382 #define S_0007C0_CMDSTRM_BUSY(x) (((x) & 0x1) << 30) 383 #define G_0007C0_CMDSTRM_BUSY(x) (((x) >> 30) & 0x1) 384 #define C_0007C0_CMDSTRM_BUSY 0xBFFFFFFF 385 #define S_0007C0_CP_BUSY(x) (((x) & 0x1) << 31) 386 #define G_0007C0_CP_BUSY(x) (((x) >> 31) & 0x1) 387 #define C_0007C0_CP_BUSY 0x7FFFFFFF 388 #define R_000E40_RBBM_STATUS 0x000E40 389 #define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0) 390 #define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F) 391 #define C_000E40_CMDFIFO_AVAIL 0xFFFFFF80 392 #define S_000E40_HIRQ_ON_RBB(x) (((x) & 0x1) << 8) 393 #define G_000E40_HIRQ_ON_RBB(x) (((x) >> 8) & 0x1) 394 #define C_000E40_HIRQ_ON_RBB 0xFFFFFEFF 395 #define S_000E40_CPRQ_ON_RBB(x) (((x) & 0x1) << 9) 396 #define G_000E40_CPRQ_ON_RBB(x) (((x) >> 9) & 0x1) 397 #define C_000E40_CPRQ_ON_RBB 0xFFFFFDFF 398 #define S_000E40_CFRQ_ON_RBB(x) (((x) & 0x1) << 10) 399 #define G_000E40_CFRQ_ON_RBB(x) (((x) >> 10) & 0x1) 400 #define C_000E40_CFRQ_ON_RBB 0xFFFFFBFF 401 #define S_000E40_HIRQ_IN_RTBUF(x) (((x) & 0x1) << 11) 402 #define G_000E40_HIRQ_IN_RTBUF(x) (((x) >> 11) & 0x1) 403 #define C_000E40_HIRQ_IN_RTBUF 0xFFFFF7FF 404 #define S_000E40_CPRQ_IN_RTBUF(x) (((x) & 0x1) << 12) 405 #define G_000E40_CPRQ_IN_RTBUF(x) (((x) >> 12) & 0x1) 406 #define C_000E40_CPRQ_IN_RTBUF 0xFFFFEFFF 407 #define S_000E40_CFRQ_IN_RTBUF(x) (((x) & 0x1) << 13) 408 #define G_000E40_CFRQ_IN_RTBUF(x) (((x) >> 13) & 0x1) 409 #define C_000E40_CFRQ_IN_RTBUF 0xFFFFDFFF 410 #define S_000E40_CF_PIPE_BUSY(x) (((x) & 0x1) << 14) 411 #define G_000E40_CF_PIPE_BUSY(x) (((x) >> 14) & 0x1) 412 #define C_000E40_CF_PIPE_BUSY 0xFFFFBFFF 413 #define S_000E40_ENG_EV_BUSY(x) (((x) & 0x1) << 15) 414 #define G_000E40_ENG_EV_BUSY(x) (((x) >> 15) & 0x1) 415 #define C_000E40_ENG_EV_BUSY 0xFFFF7FFF 416 #define S_000E40_CP_CMDSTRM_BUSY(x) (((x) & 0x1) << 16) 417 #define G_000E40_CP_CMDSTRM_BUSY(x) (((x) >> 16) & 0x1) 418 #define C_000E40_CP_CMDSTRM_BUSY 0xFFFEFFFF 419 #define S_000E40_E2_BUSY(x) (((x) & 0x1) << 17) 420 #define G_000E40_E2_BUSY(x) (((x) >> 17) & 0x1) 421 #define C_000E40_E2_BUSY 0xFFFDFFFF 422 #define S_000E40_RB2D_BUSY(x) (((x) & 0x1) << 18) 423 #define G_000E40_RB2D_BUSY(x) (((x) >> 18) & 0x1) 424 #define C_000E40_RB2D_BUSY 0xFFFBFFFF 425 #define S_000E40_RB3D_BUSY(x) (((x) & 0x1) << 19) 426 #define G_000E40_RB3D_BUSY(x) (((x) >> 19) & 0x1) 427 #define C_000E40_RB3D_BUSY 0xFFF7FFFF 428 #define S_000E40_VAP_BUSY(x) (((x) & 0x1) << 20) 429 #define G_000E40_VAP_BUSY(x) (((x) >> 20) & 0x1) 430 #define C_000E40_VAP_BUSY 0xFFEFFFFF 431 #define S_000E40_RE_BUSY(x) (((x) & 0x1) << 21) 432 #define G_000E40_RE_BUSY(x) (((x) >> 21) & 0x1) 433 #define C_000E40_RE_BUSY 0xFFDFFFFF 434 #define S_000E40_TAM_BUSY(x) (((x) & 0x1) << 22) 435 #define G_000E40_TAM_BUSY(x) (((x) >> 22) & 0x1) 436 #define C_000E40_TAM_BUSY 0xFFBFFFFF 437 #define S_000E40_TDM_BUSY(x) (((x) & 0x1) << 23) 438 #define G_000E40_TDM_BUSY(x) (((x) >> 23) & 0x1) 439 #define C_000E40_TDM_BUSY 0xFF7FFFFF 440 #define S_000E40_PB_BUSY(x) (((x) & 0x1) << 24) 441 #define G_000E40_PB_BUSY(x) (((x) >> 24) & 0x1) 442 #define C_000E40_PB_BUSY 0xFEFFFFFF 443 #define S_000E40_TIM_BUSY(x) (((x) & 0x1) << 25) 444 #define G_000E40_TIM_BUSY(x) (((x) >> 25) & 0x1) 445 #define C_000E40_TIM_BUSY 0xFDFFFFFF 446 #define S_000E40_GA_BUSY(x) (((x) & 0x1) << 26) 447 #define G_000E40_GA_BUSY(x) (((x) >> 26) & 0x1) 448 #define C_000E40_GA_BUSY 0xFBFFFFFF 449 #define S_000E40_CBA2D_BUSY(x) (((x) & 0x1) << 27) 450 #define G_000E40_CBA2D_BUSY(x) (((x) >> 27) & 0x1) 451 #define C_000E40_CBA2D_BUSY 0xF7FFFFFF 452 #define S_000E40_RBBM_HIBUSY(x) (((x) & 0x1) << 28) 453 #define G_000E40_RBBM_HIBUSY(x) (((x) >> 28) & 0x1) 454 #define C_000E40_RBBM_HIBUSY 0xEFFFFFFF 455 #define S_000E40_SKID_CFBUSY(x) (((x) & 0x1) << 29) 456 #define G_000E40_SKID_CFBUSY(x) (((x) >> 29) & 0x1) 457 #define C_000E40_SKID_CFBUSY 0xDFFFFFFF 458 #define S_000E40_VAP_VF_BUSY(x) (((x) & 0x1) << 30) 459 #define G_000E40_VAP_VF_BUSY(x) (((x) >> 30) & 0x1) 460 #define C_000E40_VAP_VF_BUSY 0xBFFFFFFF 461 #define S_000E40_GUI_ACTIVE(x) (((x) & 0x1) << 31) 462 #define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1) 463 #define C_000E40_GUI_ACTIVE 0x7FFFFFFF 464 #define R_006080_D1CRTC_CONTROL 0x006080 465 #define S_006080_D1CRTC_MASTER_EN(x) (((x) & 0x1) << 0) 466 #define G_006080_D1CRTC_MASTER_EN(x) (((x) >> 0) & 0x1) 467 #define C_006080_D1CRTC_MASTER_EN 0xFFFFFFFE 468 #define S_006080_D1CRTC_SYNC_RESET_SEL(x) (((x) & 0x1) << 4) 469 #define G_006080_D1CRTC_SYNC_RESET_SEL(x) (((x) >> 4) & 0x1) 470 #define C_006080_D1CRTC_SYNC_RESET_SEL 0xFFFFFFEF 471 #define S_006080_D1CRTC_DISABLE_POINT_CNTL(x) (((x) & 0x3) << 8) 472 #define G_006080_D1CRTC_DISABLE_POINT_CNTL(x) (((x) >> 8) & 0x3) 473 #define C_006080_D1CRTC_DISABLE_POINT_CNTL 0xFFFFFCFF 474 #define S_006080_D1CRTC_CURRENT_MASTER_EN_STATE(x) (((x) & 0x1) << 16) 475 #define G_006080_D1CRTC_CURRENT_MASTER_EN_STATE(x) (((x) >> 16) & 0x1) 476 #define C_006080_D1CRTC_CURRENT_MASTER_EN_STATE 0xFFFEFFFF 477 #define S_006080_D1CRTC_DISP_READ_REQUEST_DISABLE(x) (((x) & 0x1) << 24) 478 #define G_006080_D1CRTC_DISP_READ_REQUEST_DISABLE(x) (((x) >> 24) & 0x1) 479 #define C_006080_D1CRTC_DISP_READ_REQUEST_DISABLE 0xFEFFFFFF 480 #define R_0060E8_D1CRTC_UPDATE_LOCK 0x0060E8 481 #define S_0060E8_D1CRTC_UPDATE_LOCK(x) (((x) & 0x1) << 0) 482 #define G_0060E8_D1CRTC_UPDATE_LOCK(x) (((x) >> 0) & 0x1) 483 #define C_0060E8_D1CRTC_UPDATE_LOCK 0xFFFFFFFE 484 #define R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x006110 485 #define S_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) 486 #define G_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) 487 #define C_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x00000000 488 #define R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x006118 489 #define S_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) 490 #define G_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) 491 #define C_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x00000000 492 #define R_006880_D2CRTC_CONTROL 0x006880 493 #define S_006880_D2CRTC_MASTER_EN(x) (((x) & 0x1) << 0) 494 #define G_006880_D2CRTC_MASTER_EN(x) (((x) >> 0) & 0x1) 495 #define C_006880_D2CRTC_MASTER_EN 0xFFFFFFFE 496 #define S_006880_D2CRTC_SYNC_RESET_SEL(x) (((x) & 0x1) << 4) 497 #define G_006880_D2CRTC_SYNC_RESET_SEL(x) (((x) >> 4) & 0x1) 498 #define C_006880_D2CRTC_SYNC_RESET_SEL 0xFFFFFFEF 499 #define S_006880_D2CRTC_DISABLE_POINT_CNTL(x) (((x) & 0x3) << 8) 500 #define G_006880_D2CRTC_DISABLE_POINT_CNTL(x) (((x) >> 8) & 0x3) 501 #define C_006880_D2CRTC_DISABLE_POINT_CNTL 0xFFFFFCFF 502 #define S_006880_D2CRTC_CURRENT_MASTER_EN_STATE(x) (((x) & 0x1) << 16) 503 #define G_006880_D2CRTC_CURRENT_MASTER_EN_STATE(x) (((x) >> 16) & 0x1) 504 #define C_006880_D2CRTC_CURRENT_MASTER_EN_STATE 0xFFFEFFFF 505 #define S_006880_D2CRTC_DISP_READ_REQUEST_DISABLE(x) (((x) & 0x1) << 24) 506 #define G_006880_D2CRTC_DISP_READ_REQUEST_DISABLE(x) (((x) >> 24) & 0x1) 507 #define C_006880_D2CRTC_DISP_READ_REQUEST_DISABLE 0xFEFFFFFF 508 #define R_0068E8_D2CRTC_UPDATE_LOCK 0x0068E8 509 #define S_0068E8_D2CRTC_UPDATE_LOCK(x) (((x) & 0x1) << 0) 510 #define G_0068E8_D2CRTC_UPDATE_LOCK(x) (((x) >> 0) & 0x1) 511 #define C_0068E8_D2CRTC_UPDATE_LOCK 0xFFFFFFFE 512 #define R_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS 0x006910 513 #define S_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) 514 #define G_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) 515 #define C_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS 0x00000000 516 #define R_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS 0x006918 517 #define S_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) 518 #define G_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) 519 #define C_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS 0x00000000 520 521 522 #define R_000001_MC_FB_LOCATION 0x000001 523 #define S_000001_MC_FB_START(x) (((x) & 0xFFFF) << 0) 524 #define G_000001_MC_FB_START(x) (((x) >> 0) & 0xFFFF) 525 #define C_000001_MC_FB_START 0xFFFF0000 526 #define S_000001_MC_FB_TOP(x) (((x) & 0xFFFF) << 16) 527 #define G_000001_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF) 528 #define C_000001_MC_FB_TOP 0x0000FFFF 529 #define R_000002_MC_AGP_LOCATION 0x000002 530 #define S_000002_MC_AGP_START(x) (((x) & 0xFFFF) << 0) 531 #define G_000002_MC_AGP_START(x) (((x) >> 0) & 0xFFFF) 532 #define C_000002_MC_AGP_START 0xFFFF0000 533 #define S_000002_MC_AGP_TOP(x) (((x) & 0xFFFF) << 16) 534 #define G_000002_MC_AGP_TOP(x) (((x) >> 16) & 0xFFFF) 535 #define C_000002_MC_AGP_TOP 0x0000FFFF 536 #define R_000003_MC_AGP_BASE 0x000003 537 #define S_000003_AGP_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0) 538 #define G_000003_AGP_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) 539 #define C_000003_AGP_BASE_ADDR 0x00000000 540 #define R_000004_MC_AGP_BASE_2 0x000004 541 #define S_000004_AGP_BASE_ADDR_2(x) (((x) & 0xF) << 0) 542 #define G_000004_AGP_BASE_ADDR_2(x) (((x) >> 0) & 0xF) 543 #define C_000004_AGP_BASE_ADDR_2 0xFFFFFFF0 544 545 546 #define R_00000F_CP_DYN_CNTL 0x00000F 547 #define S_00000F_CP_FORCEON(x) (((x) & 0x1) << 0) 548 #define G_00000F_CP_FORCEON(x) (((x) >> 0) & 0x1) 549 #define C_00000F_CP_FORCEON 0xFFFFFFFE 550 #define S_00000F_CP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 1) 551 #define G_00000F_CP_MAX_DYN_STOP_LAT(x) (((x) >> 1) & 0x1) 552 #define C_00000F_CP_MAX_DYN_STOP_LAT 0xFFFFFFFD 553 #define S_00000F_CP_CLOCK_STATUS(x) (((x) & 0x1) << 2) 554 #define G_00000F_CP_CLOCK_STATUS(x) (((x) >> 2) & 0x1) 555 #define C_00000F_CP_CLOCK_STATUS 0xFFFFFFFB 556 #define S_00000F_CP_PROG_SHUTOFF(x) (((x) & 0x1) << 3) 557 #define G_00000F_CP_PROG_SHUTOFF(x) (((x) >> 3) & 0x1) 558 #define C_00000F_CP_PROG_SHUTOFF 0xFFFFFFF7 559 #define S_00000F_CP_PROG_DELAY_VALUE(x) (((x) & 0xFF) << 4) 560 #define G_00000F_CP_PROG_DELAY_VALUE(x) (((x) >> 4) & 0xFF) 561 #define C_00000F_CP_PROG_DELAY_VALUE 0xFFFFF00F 562 #define S_00000F_CP_LOWER_POWER_IDLE(x) (((x) & 0xFF) << 12) 563 #define G_00000F_CP_LOWER_POWER_IDLE(x) (((x) >> 12) & 0xFF) 564 #define C_00000F_CP_LOWER_POWER_IDLE 0xFFF00FFF 565 #define S_00000F_CP_LOWER_POWER_IGNORE(x) (((x) & 0x1) << 20) 566 #define G_00000F_CP_LOWER_POWER_IGNORE(x) (((x) >> 20) & 0x1) 567 #define C_00000F_CP_LOWER_POWER_IGNORE 0xFFEFFFFF 568 #define S_00000F_CP_NORMAL_POWER_IGNORE(x) (((x) & 0x1) << 21) 569 #define G_00000F_CP_NORMAL_POWER_IGNORE(x) (((x) >> 21) & 0x1) 570 #define C_00000F_CP_NORMAL_POWER_IGNORE 0xFFDFFFFF 571 #define S_00000F_SPARE(x) (((x) & 0x3) << 22) 572 #define G_00000F_SPARE(x) (((x) >> 22) & 0x3) 573 #define C_00000F_SPARE 0xFF3FFFFF 574 #define S_00000F_CP_NORMAL_POWER_BUSY(x) (((x) & 0xFF) << 24) 575 #define G_00000F_CP_NORMAL_POWER_BUSY(x) (((x) >> 24) & 0xFF) 576 #define C_00000F_CP_NORMAL_POWER_BUSY 0x00FFFFFF 577 #define R_000011_E2_DYN_CNTL 0x000011 578 #define S_000011_E2_FORCEON(x) (((x) & 0x1) << 0) 579 #define G_000011_E2_FORCEON(x) (((x) >> 0) & 0x1) 580 #define C_000011_E2_FORCEON 0xFFFFFFFE 581 #define S_000011_E2_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 1) 582 #define G_000011_E2_MAX_DYN_STOP_LAT(x) (((x) >> 1) & 0x1) 583 #define C_000011_E2_MAX_DYN_STOP_LAT 0xFFFFFFFD 584 #define S_000011_E2_CLOCK_STATUS(x) (((x) & 0x1) << 2) 585 #define G_000011_E2_CLOCK_STATUS(x) (((x) >> 2) & 0x1) 586 #define C_000011_E2_CLOCK_STATUS 0xFFFFFFFB 587 #define S_000011_E2_PROG_SHUTOFF(x) (((x) & 0x1) << 3) 588 #define G_000011_E2_PROG_SHUTOFF(x) (((x) >> 3) & 0x1) 589 #define C_000011_E2_PROG_SHUTOFF 0xFFFFFFF7 590 #define S_000011_E2_PROG_DELAY_VALUE(x) (((x) & 0xFF) << 4) 591 #define G_000011_E2_PROG_DELAY_VALUE(x) (((x) >> 4) & 0xFF) 592 #define C_000011_E2_PROG_DELAY_VALUE 0xFFFFF00F 593 #define S_000011_E2_LOWER_POWER_IDLE(x) (((x) & 0xFF) << 12) 594 #define G_000011_E2_LOWER_POWER_IDLE(x) (((x) >> 12) & 0xFF) 595 #define C_000011_E2_LOWER_POWER_IDLE 0xFFF00FFF 596 #define S_000011_E2_LOWER_POWER_IGNORE(x) (((x) & 0x1) << 20) 597 #define G_000011_E2_LOWER_POWER_IGNORE(x) (((x) >> 20) & 0x1) 598 #define C_000011_E2_LOWER_POWER_IGNORE 0xFFEFFFFF 599 #define S_000011_E2_NORMAL_POWER_IGNORE(x) (((x) & 0x1) << 21) 600 #define G_000011_E2_NORMAL_POWER_IGNORE(x) (((x) >> 21) & 0x1) 601 #define C_000011_E2_NORMAL_POWER_IGNORE 0xFFDFFFFF 602 #define S_000011_SPARE(x) (((x) & 0x3) << 22) 603 #define G_000011_SPARE(x) (((x) >> 22) & 0x3) 604 #define C_000011_SPARE 0xFF3FFFFF 605 #define S_000011_E2_NORMAL_POWER_BUSY(x) (((x) & 0xFF) << 24) 606 #define G_000011_E2_NORMAL_POWER_BUSY(x) (((x) >> 24) & 0xFF) 607 #define C_000011_E2_NORMAL_POWER_BUSY 0x00FFFFFF 608 #define R_000013_IDCT_DYN_CNTL 0x000013 609 #define S_000013_IDCT_FORCEON(x) (((x) & 0x1) << 0) 610 #define G_000013_IDCT_FORCEON(x) (((x) >> 0) & 0x1) 611 #define C_000013_IDCT_FORCEON 0xFFFFFFFE 612 #define S_000013_IDCT_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 1) 613 #define G_000013_IDCT_MAX_DYN_STOP_LAT(x) (((x) >> 1) & 0x1) 614 #define C_000013_IDCT_MAX_DYN_STOP_LAT 0xFFFFFFFD 615 #define S_000013_IDCT_CLOCK_STATUS(x) (((x) & 0x1) << 2) 616 #define G_000013_IDCT_CLOCK_STATUS(x) (((x) >> 2) & 0x1) 617 #define C_000013_IDCT_CLOCK_STATUS 0xFFFFFFFB 618 #define S_000013_IDCT_PROG_SHUTOFF(x) (((x) & 0x1) << 3) 619 #define G_000013_IDCT_PROG_SHUTOFF(x) (((x) >> 3) & 0x1) 620 #define C_000013_IDCT_PROG_SHUTOFF 0xFFFFFFF7 621 #define S_000013_IDCT_PROG_DELAY_VALUE(x) (((x) & 0xFF) << 4) 622 #define G_000013_IDCT_PROG_DELAY_VALUE(x) (((x) >> 4) & 0xFF) 623 #define C_000013_IDCT_PROG_DELAY_VALUE 0xFFFFF00F 624 #define S_000013_IDCT_LOWER_POWER_IDLE(x) (((x) & 0xFF) << 12) 625 #define G_000013_IDCT_LOWER_POWER_IDLE(x) (((x) >> 12) & 0xFF) 626 #define C_000013_IDCT_LOWER_POWER_IDLE 0xFFF00FFF 627 #define S_000013_IDCT_LOWER_POWER_IGNORE(x) (((x) & 0x1) << 20) 628 #define G_000013_IDCT_LOWER_POWER_IGNORE(x) (((x) >> 20) & 0x1) 629 #define C_000013_IDCT_LOWER_POWER_IGNORE 0xFFEFFFFF 630 #define S_000013_IDCT_NORMAL_POWER_IGNORE(x) (((x) & 0x1) << 21) 631 #define G_000013_IDCT_NORMAL_POWER_IGNORE(x) (((x) >> 21) & 0x1) 632 #define C_000013_IDCT_NORMAL_POWER_IGNORE 0xFFDFFFFF 633 #define S_000013_SPARE(x) (((x) & 0x3) << 22) 634 #define G_000013_SPARE(x) (((x) >> 22) & 0x3) 635 #define C_000013_SPARE 0xFF3FFFFF 636 #define S_000013_IDCT_NORMAL_POWER_BUSY(x) (((x) & 0xFF) << 24) 637 #define G_000013_IDCT_NORMAL_POWER_BUSY(x) (((x) >> 24) & 0xFF) 638 #define C_000013_IDCT_NORMAL_POWER_BUSY 0x00FFFFFF 639 640 #endif 641
Indexes created Sat Sep 20 22:09:52 GMT 2025