1 /* $NetBSD: ar9344reg.h,v 1.2 2011/07/10 23:13:23 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _MIPS_ATHEROS_AR9344REG_H_ 33 #define _MIPS_ATHEROS_AR9344REG_H_ 34 35 #define AR9344_MEM0_BASE 0x00000000 /* sdram */ 36 #define AR9344_MEM1_BASE 0x08000000 /* sdram/flash */ 37 #define AR9344_MEM3_BASE 0x10000000 /* flash */ 38 #define AR7100_PCI_BASE 0x17001000 39 #define ARCHIP_DDR_BASE 0x18000000 40 #define AR9344_UART0_BASE 0x18020000 /* low speed */ 41 #define AR7100_UART_BASE 0x18020000 /* low speed */ 42 #define AR9344_USB_CONFIG_BASE 0x18030000 43 #define AR9344_GPIO_BASE 0x18040000 44 #define ARCHIP_PLL_BASE 0x18050000 45 #define ARCHIP_RESET_BASE 0x18060000 46 #define AR9344_GMAC_BASE 0x18070000 47 #define AR7100_MII_BASE 0x18070000 48 #define AR9344_GMAC0_INGRESS_BASE 0x18080000 49 #define AR7100_GMAC0_BASE 0x18090000 50 #define AR9344_MBOX_BASE 0x180A0000 51 #define AR7100_GMAC1_BASE 0x180A0000 52 #define AR9344_SLIC_BASE 0x180A9000 53 #define AR9344_STEREO_BASE 0x180B0000 54 #define AR9344_MDIO_BASE 0x180B8000 55 #define AR9344_PCIE_RC_BASE 0x180C0000 56 #define AR9344_PCIE_RC_BASE2 0x180F0000 57 #define AR9344_WDMA_BASE 0x18100000 58 #define AR9344_RTC_BASE 0x18107000 59 #define AR9344_UART1_BASE 0x18150000 /* high speed */ 60 #define AR9344_GMAC0_BASE 0x19000000 61 #define AR9344_GMAC1_BASE 0x1A000000 62 #define AR9344_USB_BASE 0x1B000000 63 #define AR7100_EHCI_BASE 0x1B000000 64 #define AR9344_NAND_BASE 0x1B000200 65 #define AR7100_OHCI_BASE 0x1C000000 66 #define AR7100_SPI_BASE 0x1F000000 67 #define AR9344_SPI_BASE 0x1FFF0000 68 69 /* 70 * PLL registers -- offset relative to AR9344_PLL_BASE 71 */ 72 #define ARCHIP_PLL_CPU_PLL_CONFIG 0x0000 73 #define ARCHIP_PLL_DDR_PLL_CONFIG 0x0004 74 #define ARCHIP_PLL_CPU_DDR_CLOCK_CONTROL 0x0008 75 76 #define AR9344_PLL_PCIE_PLL_CONFIG 0x0010 77 #define AR9344_PLL_PCIE_PLL_DITHER_DIV_MAX 0x0014 78 #define AR9344_PLL_PCIE_PLL_DITHER_DIV_MIN 0x0018 79 #define AR9344_PLL_PCIE_PLL_DITHER_STEP 0x001c 80 #define AR9344_PLL_SWITCH_CLOCK_SPARE 0x0024 81 #define AR9344_PLL_CURRENT_PCIE_PLL_DITHER 0x0028 82 #define AR9344_PLL_ETH_XMII_CONTROL 0x002c 83 #define AR9344_PLL_AUDIO_PLL_CONFIG 0x0030 84 #define AR9344_PLL_AUDIO_PLL_MODULATION 0x0034 85 #define AR9344_PLL_AUDIO_PLL_MOD_STEP 0x0038 86 #define AR9344_PLL_CURRENT_AUDIO_PLL_MODULATION 0x003c 87 #define AR9344_PLL_DDR_PLL_DITHER 0x0044 88 #define AR9344_PLL_CPU_PLL_DITHER 0x0048 89 90 #define AR9344_CPU_PLL_CONFIG_UPDATING __BIT(31) 91 #define AR9344_CPU_PLL_CONFIG_PLLPWD __BIT(30) 92 #define AR9344_CPU_PLL_CONFIG_OUTDIV __BITS(19,21) 93 #define AR9344_CPU_PLL_CONFIG_RANGE __BITS(18,17) 94 #define AR9344_CPU_PLL_CONFIG_REFDIV __BITS(12,16) 95 #define AR9344_CPU_PLL_CONFIG_NINT __BITS(6,11) 96 #define AR9344_CPU_PLL_CONFIG_NFRAC __BITS(0,5) 97 98 #define AR7100_CPU_PLL_SW_UPDATE __BIT(31) 99 #define AR7100_PLL_LOCKED __BIT(30) 100 #define AR7100_CPU_PLL_AHB_DIV __BITS(22,20) 101 #define AR7100_CPU_PLL_DDR_DIV_SEL __BITS(19,18) 102 #define AR7100_CPU_PLL_CPU_DIV_SEL __BITS(17,16) 103 #define AR7100_PLL_PLL_LOOP_BW __BITS(15,12) 104 #define AR7100_PLL_PLL_DIV_IN __BITS(11,10) 105 #define AR7100_PLL_PLL_DIV_OUT __BITS(9,8) 106 #define AR7100_PLL_PLL_FB __BITS(7,3) 107 #define AR7100_CPU_PLL_PLL_BYPASS __BIT(1) 108 #define AR7100_PLL_PLL_POWER_DOWN __BIT(0) 109 110 #define AR9344_DDR_PLL_CONFIG_UPDATING __BIT(31) 111 #define AR9344_DDR_PLL_CONFIG_PLLPWD __BIT(30) 112 #define AR9344_DDR_PLL_CONFIG_OUTDIV __BITS(23,25) 113 #define AR9344_DDR_PLL_CONFIG_RANGE __BITS(21,22) 114 #define AR9344_DDR_PLL_CONFIG_REFDIV __BITS(16,20) 115 #define AR9344_DDR_PLL_CONFIG_NINT __BITS(10,15) 116 #define AR9344_DDR_PLL_CONFIG_NFRAC __BITS(0,9) 117 118 #define AR9344_CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL __BIT(24) 119 #define AR9344_CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASRT __BIT(23) 120 #define AR9344_CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT __BIT(22) 121 #define AR9344_CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL __BIT(21) 122 #define AR9344_CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL __BIT(20) 123 #define AR9344_CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV __BITS(15,19) 124 #define AR9344_CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV __BITS(10,14) 125 #define AR9344_CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV __BITS(5,9) 126 #define AR9344_CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS __BIT(4) 127 #define AR9344_CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS __BIT(3) 128 #define AR9344_CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS __BIT(2) 129 #define AR9344_CPU_DDR_CLOCK_CONTROL_RESET_SWITCH __BIT(1) 130 131 /* 132 * RESET registers -- offset relative to ARCHIP_RESET_BASE 133 */ 134 #define ARCHIP_RESET_TIMER 0x0000 135 #define ARCHIP_RESET_TIMER_RELOAD 0x0004 136 #define ARCHIP_RESET_WDOG_CTL 0x0008 137 #define ARCHIP_RESET_WDOG_TIMER 0x000c 138 #define ARCHIP_RESET_MISC_INTSTAT 0x0010 139 #define ARCHIP_RESET_MISC_INTMASK 0x0014 140 #define AR9344_RESET_INTSTAT 0x0018 141 #define AR7100_RESET_PCI_INTSTAT 0x0018 142 #define AR9344_RESET_RESETCTL 0x001c 143 #define AR7100_RESET_PCI_INTMASK 0x001c 144 #define AR7100_RESET_INTSTAT 0x0020 145 #define AR7100_RESET_RESETCTL 0x0024 146 #define ARCHIP_RESET_REVISION 0x0090 147 #define AR9344_RESET_WMAC_INTSTAT 0x00AC 148 #define AR9344_RESET_BOOTSTRAP 0x00B0 149 #define AR9344_RESET_MISC2 0x00BC 150 151 /* WDOG_CTL watchdog control bits */ 152 #define ARCHIP_WDOG_CTL_LAST __BIT(31) 153 #define ARCHIP_WDOG_CTL_IGNORE 0x00000000 154 #define ARCHIP_WDOG_CTL_INT 0x00000001 155 #define ARCHIP_WDOG_CTL_NMI 0x00000002 156 #define ARCHIP_WDOG_CTL_RESET 0x00000003 157 158 /* Resets */ 159 #define AR9344_RESETCTL_I2S_RESET __BIT(0) 160 #define AR7100_RESETCTL_PCI_CORE_RESET __BIT(0) 161 #define AR9344_RESETCTL_MBOX_RESET __BIT(1) 162 #define AR7100_RESETCTL_PCI_BUS_RESET __BIT(1) 163 #define AR9344_RESETCTL_LUT_RESET __BIT(2) 164 #define AR9344_RESETCTL_USB_PHY_SUSPEND_OVERRIDE __BIT(3) 165 #define ARCHIP_RESETCTL_USB_PHY_RESET __BIT(4) 166 #define ARCHIP_RESETCTL_USB_HOST_RESET __BIT(5) 167 #define AR9344_RESETCTL_PCIE_RESET __BIT(6) 168 #define AR7100_RESETCTL_USB_OHCI_DLL_RESET __BIT(6) 169 #define AR9344_RESETCTL_PCIE_PHY_RESET __BIT(7) 170 #define AR9344_RESETCTL_ETH_SWITCH_RESET __BIT(8) 171 #define AR7100_RESETCTL_GMAC0_PHY_RESET __BIT(8) 172 #define ARCHIP_RESETCTL_GMAC0_MAC_RESET __BIT(9) 173 #define AR9344_RESETCTL_HOST_DMA_INT __BIT(10) 174 #define AR9344_RESETCTL_USB_PHY_ARESET __BIT(11) 175 #define AR9344_RESETCTL_ETH_SWITCH_ARESET __BIT(12) 176 #define AR7100_RESETCTL_GMAC1_PHY_RESET __BIT(12) 177 #define ARCHIP_RESETCTL_GMAC1_MAC_RESET __BIT(13) 178 #define AR9344_RESETCTL_NANDF_RESET __BIT(14) 179 #define AR9344_RESETCTL_USB_PHY_PLL_PWD_EXT __BIT(15) 180 #define ARCHIP_RESETCTL_DDR_RESET __BIT(16) 181 #define AR9344_RESETCTL_UART1_RESET __BIT(17) 182 #define AR7100_RESETCTL_I2S_RESET __BIT(17) 183 #define AR9344_RESETCTL_PCIEEP_RESET __BIT(18) 184 #define AR7100_RESETCTL_SLIC_RESET __BIT(18) 185 #define AR9344_RESETCTL_HOST_RESET_INT __BIT(19) 186 #define AR7100_RESETCTL_DMA_RESET __BIT(19) 187 #define ARCHIP_RESETCTL_CPU_COLD_RESET __BIT(20) 188 #define ARCHIP_RESETCTL_CPU_NMI __BIT(21) 189 #define AR9344_RESETCTL_RESET_GMAC0_MDIO __BIT(22) 190 #define AR9344_RESETCTL_RESET_GMAC1_MDIO __BIT(23) 191 #define ARCHIP_RESETCTL_FULL_CHIP_RESET __BIT(24) 192 #define AR9344_RESETCTL_CHKSUM_ACC_RESET __BIT(25) 193 #define AR9344_RESETCTL_PCIEEP_RST_INT __BIT(26) 194 #define AR9344_RESETCTL_RTC_RESET __BIT(27) 195 #define ARCHIP_RESETCTL_EXTERNAL_RESET __BIT(28) 196 #define AR9344_RESETCTL_HDMA_RESET __BIT(29) 197 #define AR9344_RESETCTL_SLIC_RESET __BIT(30) 198 #define AR9344_RESETCTL_HOST_RESET __BIT(31) 199 200 /* Revision ids */ 201 #define AR9344_REVISION_WMAC_MAJOR(x) (((x) >> 12) & 0xf) 202 #define AR9344_REVISION_WMAC_MINOR(x) (((x) >> 8) & 0xf) 203 #define AR9344_REVISION_WMAC(x) (((x) >> 8) & 0xff) 204 #define AR9344_REVISION_MAJOR(x) (((x) >> 4) & 0xf) 205 #define AR9344_REVISION_MINOR(x) (((x) >> 0) & 0xf) 206 #define AR9344_REVISION_CHIPID(x) (((x) >> 0) & 0xff) 207 208 #define AR5311_REVISION_MAJ 0x1 209 #define AR7240_REVISION_MAJ 0x4 210 #define AR2313_REVISION_MAJ 0x5 211 #define AR7100_REVISION_MAJ 0xA 212 #define AR5315_REVISION_MAJ 0xB 213 #define AR9344_REVISION_MAJ 0xC 214 215 #define ARCHIP_AR5312 0x42 216 #define ARCHIP_AR7130 0xA0 217 #define ARCHIP_AR7141 0xA1 218 #define ARCHIP_AR7161 0xA2 219 #define ARCHIP_AR9344 0xC0 220 #define ARCHIP_AR9103 0xB0 221 #define ARCHIP_AR5315 0xB0 222 223 #define ARWMAC_AR5312 0x52 224 #define ARWMAC_AR5312_2 0x57 225 #define ARWMAC_AR2313 0x58 226 #define ARWMAC_AR2315LITE 0x86 227 #define ARWMAC_AR2315 0x87 228 #define ARWMAC_AR2317 0x91 229 230 #define AR9344_BOOTSTRAP_SOFTWARE_OPTION_8 __BIT(31) 231 #define AR9344_BOOTSTRAP_SOFTWARE_OPTION_7 __BIT(30) 232 #define AR9344_BOOTSTRAP_DDR_WIDTH __BIT(29) 233 #define AR9344_BOOTSTRAP_SOFTWARE_OPTION_5 __BIT(28) 234 #define AR9344_BOOTSTRAP_SOFTWARE_OPTION_4 __BIT(27) 235 #define AR9344_BOOTSTRAP_SOFTWARE_OPTION_3 __BIT(26) 236 #define AR9344_BOOTSTRAP_SOFTWARE_OPTION_2 __BIT(25) 237 #define AR9344_BOOTSTRAP_SOFTWARE_OPTION_1 __BIT(24) 238 #define AR9344_BOOTSTRAP_USB_MODE __BIT(7) 239 #define AR9344_BOOTSTRAP_EJTAG_MODE __BIT(5) 240 #define AR9344_BOOTSTRAP_REF_CLK_40 __BIT(4) 241 #define AR9344_BOOTSTRAP_BOOT_SELECT __BIT(2) 242 #define AR9344_BOOTSTRAP_SDRAM_DISABLE __BIT(1) 243 #define AR9344_BOOTSTRAP_DDR_SELECT __BIT(0) 244 245 /* 246 * DDR registers -- offset relative to ARCHIP_DDR_BASE 247 */ 248 #define AR9344_DDR_CONFIG 0x0000 249 #define AR9344_DDR_CONFIG2 0x0004 250 #define AR9344_DDR_MODE_REGISTER 0x0008 251 #define AR9344_DDR_EXTENDED_MOD_REGISTER 0x000c 252 #define AR9344_DDR_CONTROL 0x0010 253 #define AR9344_DDR_REFRESH 0x0014 254 #define AR9344_DDR_RD_DATA_THIS_CYCLE 0x0018 255 #define AR9344_DDR_TAP_CONTROL_0 0x001c 256 #define AR9344_DDR_TAP_CONTROL_1 0x0020 257 #define AR9344_DDR_TAP_CONTROL_2 0x0024 258 #define AR9344_DDR_TAP_CONTROL_3 0x0028 259 #define AR9344_DDR_WB_FLUSH_GMAC0 0x009c 260 #define AR9344_DDR_WB_FLUSH_GMAC1 0x00a0 261 #define AR9344_DDR_WB_FLUSH_USB 0x00a4 262 #define AR9344_DDR_WB_FLUSH_PCIE 0x00a8 263 #define AR9344_DDR_WB_FLUSH_WMAC 0x00ac 264 #define AR9344_DDR_WB_FLUSH_SRC1 0x00b0 265 #define AR9344_DDR_WB_FLUSH_SRC2 0x00b4 266 #define AR9344_DDR_DDR2_CONFIG 0x00b8 267 #define AR9344_DDR_EMR2 0x00bc 268 #define AR9344_DDR_EMR3 0x00c0 269 #define AR9344_AHB_MASTER_TIMEOUT_MAX 0x00cc 270 #define AR9344_AHB_MASTER_TIMEOUT_CURRENT 0x00d0 271 #define AR9344_AHB_MASTER_TIMEOUT_SLAVE_ADDR 0x00d4 272 #define AR9344_DDR_CTL_CONFIG 0x0108 273 #define AR9344_DDR_SF_CTL 0x0110 274 #define AR9344_SF_TIMER 0x0114 275 #define AR9344_WMAC_FLUSH 0x0128 276 277 /* memory config 1 bits */ 278 #define AR9344_MEM_CFG1_BANK0 __BITS(8,10) 279 #define AR9344_MEM_CFG1_BANK1 __BITS(12,14) 280 281 #define ARCHIP_REG_DDR_WB_FLUSH_GMAC0 0x009c 282 #define ARCHIP_REG_DDR_WB_FLUSH_GMAC1 0x00a0 283 #define ARCHIP_REG_DDR_WB_FLUSH_USB 0x00a4 284 #define AR9344_REG_DDR_WB_FLUSH_PCIERC 0x00a8 285 #define AR7100_REG_DDR_WB_FLUSH_PCI 0x00a8 286 #define AR9344_REG_DDR_WB_FLUSH_WMAC 0x00ac 287 #define AR9344_REG_DDR_WB_FLUSH_PCIEEP 0x00b0 288 #define AR9344_REG_DDR_WB_FLUSH_CSUM 0x00b4 289 290 #define AR7100_PCI_WINDOW_0 0x7c 291 #define AR7100_PCI_WINDOW_1 0x80 292 #define AR7100_PCI_WINDOW_2 0x84 293 #define AR7100_PCI_WINDOW_3 0x88 294 #define AR7100_PCI_WINDOW_4 0x8c 295 #define AR7100_PCI_WINDOW_5 0x90 296 #define AR7100_PCI_WINDOW_6 0x94 297 #define AR7100_PCI_WINDOW_7 0x98 298 299 #define AR7100_PCI_LCL_CFG_CMD 0x00 300 #define AR7100_PCI_LCL_CFG_CMD_BE __BITS(20,23) 301 #define AR7100_PCI_LCL_CFG_CMD_CMD __BITS(16,19) 302 #define AR7100_PCI_LCL_CFG_CMD_READ __SHIFTIN(0, AR7100_PCI_LCL_CFG_CMD_CMD) 303 #define AR7100_PCI_LCL_CFG_CMD_WRITE __SHIFTIN(1, AR7100_PCI_LCL_CFG_CMD_CMD) 304 #define AR7100_PCI_LCL_CFG_CMD_ADDRESS __BITS(0,11) 305 #define AR7100_PCI_LCL_CFG_WDATA 0x04 306 #define AR7100_PCI_LCL_CFG_RDATA 0x08 307 #define AR7100_PCI_CFG_ADDR 0x0c 308 #define AR7100_PCI_CFG_CMD 0x10 309 #define AR7100_PCI_CFG_CMD_BE __BITS(4,7) 310 #define AR7100_PCI_CFG_CMD_CMD __BITS(0,3) 311 #define AR7100_PCI_CFG_WDATA 0x14 312 #define AR7100_PCI_CFG_RDATA 0x18 313 #define AR7100_PCI_ERROR 0x1c 314 #define AR7100_PCI_ERROR_PARITY __BIT(0) 315 #define AR7100_PCI_ERROR_FATAL __BIT(1) 316 #define AR7100_PCI_ERROR_ADDR 0x20 317 #define AR7100_AHB_ERROR 0x24 318 #define AR7100_AHB_ERROR_ADDR 0x28 319 320 #define AR9344_SPI_FUNCTION_SELECT 0x0000 321 #define AR9344_SPI_FUNCTION_SLEECT_FUNCTION_SELECT __BIT(0) 322 #define AR9344_SPI_CONTROL 0x0004 323 #define AR9344_SPI_CONTROL_TSHSL_CNT __BITS(8,13) 324 #define AR9344_SPI_CONTROL_SPI_RELOCATE __BIT(7) 325 #define AR9344_SPI_CONTROL_REMAP_DISABLE __BIT(6) 326 #define AR9344_SPI_CONTROL_CLOCK_DIVIDER __BITS(0,5) 327 #define AR9344_SPI_IO_CONTROL 0x0008 328 #define AR9344_SPI_IO_CONTROL_IO_CS2_DISABLE __BIT(18) 329 #define AR9344_SPI_IO_CONTROL_IO_CS1_DISABLE __BIT(17) 330 #define AR9344_SPI_IO_CONTROL_IO_CS0_DISABLE __BIT(16) 331 #define AR9344_SPI_IO_CONTROL_IO_CLK __BIT(8) 332 #define AR9344_SPI_IO_CONTROL_IO_DO __BIT(0) 333 #define AR9344_SPI_READ_DATA 0x000c 334 #define AR9344_SPI_SHIFT_DATAOUT 0x0010 335 #define AR9344_SPI_SHIFT_CNT 0x0014 336 #define AR9344_SPI_SHIFT_CNT_SHIFT_EN __BIT(31) 337 #define AR9344_SPI_SHIFT_CNT_SHIFT_CHNL_2 __BIT(30) 338 #define AR9344_SPI_SHIFT_CNT_SHIFT_CHNL_1 __BIT(29) 339 #define AR9344_SPI_SHIFT_CNT_SHIFT_CHNL_0 __BIT(28) 340 #define AR9344_SPI_SHIFT_CNT_SHIFT_CLKOUT __BIT(27) 341 #define AR9344_SPI_SHIFT_CNT_TERMINATE __BIT(26) 342 #define AR9344_SPI_SHIFT_CNT_SHIFT_COUNT __BITS(0,6) 343 #define AR9344_SPI_SHIFT_DATAIN 0x0018 344 345 /* helper macro for accessing system registers without bus space */ 346 #define REGVAL(x) *((volatile uint32_t *)(MIPS_PHYS_TO_KSEG1((x)))) 347 #define GETRESETREG(x) REGVAL((x) + ARCHIP_RESET_BASE) 348 #define PUTRESETREG(x,v) (REGVAL((x) + ARCHIP_RESET_BASE)) = (v) 349 #define GETPLLREG(x) REGVAL((x) + ARCHIP_PLL_BASE) 350 #define PUTPLLREG(x,v) (REGVAL((x) + ARCHIP_PLL_BASE)) = (v) 351 #define GETDDRREG(x) REGVAL((x) + ARCHIP_DDR_BASE) 352 #define PUTDDRREG(x,v) (REGVAL((x) + ARCHIP_DDR_BASE)) = (v) 353 354 /* 355 * Interrupts. 356 */ 357 #define AR9344_CPU_IRQ_PCIERC 0 358 #define AR7100_CPU_IRQ_PCI 0 359 #define ARCHIP_CPU_IRQ_USB 1 360 #define ARCHIP_CPU_IRQ_GMAC0 2 361 #define ARCHIP_CPU_IRQ_GMAC1 3 362 #define ARCHIP_CPU_IRQ_MISC 4 363 #define ARCHIP_CPU_IRQ_TIMER 5 364 #define AR9344_CPU_IRQ_PCIEEP_HSTDMA 6 365 366 #define AR9344_MISC_IRQ_TIMER 0 367 #define AR9344_MISC_IRQ_ERROR 1 368 #define AR9344_MISC_IRQ_GPIO 2 369 #define AR9344_MISC_IRQ_UART0 3 370 #define AR9344_MISC_IRQ_WDOG 4 371 #define AR9344_MISC_IRQ_PC 5 372 #define AR9344_MISC_IRQ_UART1 6 373 #define AR9344_MISC_IRQ_MBOX 7 374 #define AR9344_MISC_IRQ_TIMER2 8 375 #define AR9344_MISC_IRQ_TIMER3 9 376 #define AR9344_MISC_IRQ_TIMER4 10 377 #define AR9344_MISC_IRQ_DDR_PERF 11 378 #define AR9344_MISC_IRQ_SW_MAC 12 379 #define AR9344_MISC_IRQ_LUTS_AGER 13 380 #define AR9344_MISC_IRQ_RES14 14 381 #define AR9344_MISC_IRQ_CHKSUM_ACC 15 382 #define AR9344_MISC_IRQ_DDR_SF_ENTRY 16 383 #define AR9344_MISC_IRQ_DDR_SF_EXIT 17 384 #define AR9344_MISC_IRQ_DDR_ACT_IN_SF 18 385 #define AR9344_MISC_IRQ_SLIC 19 386 #define AR9344_MISC_IRQ_WOW 20 387 #define AR9344_MISC_IRQ_NANDF 21 388 389 #define AR7100_MISC_IRQ_TIMER 0 390 #define AR7100_MISC_IRQ_ERROR 1 391 #define AR7100_MISC_IRQ_GPIO 2 392 #define AR7100_MISC_IRQ_UART0 3 393 #define AR7100_MISC_IRQ_WDOG 4 394 #define AR7100_MISC_IRQ_PC 5 395 #define AR7100_MISC_IRQ_OHCI 6 396 #define AR7100_MISC_IRQ_DMA 7 397 398 #define AR9344_WMAC_IRQ_WMAC_MISC_INT 0 399 #define AR9344_WMAC_IRQ_WMAC_TX_INT 1 400 #define AR9344_WMAC_IRQ_WMAC_RXLP_INT 2 401 #define AR9344_WMAC_IRQ_WMAC_RXHP_INT 3 402 #define AR9344_WMAC_IRQ_PCIE_RC_INT 4 403 #define AR9344_WMAC_IRQ_PCIE_RC_INT0 5 404 #define AR9344_WMAC_IRQ_PCIE_RC_INT1 6 405 #define AR9344_WMAC_IRQ_PCIE_RC_INT2 7 406 #define AR9344_WMAC_IRQ_PCIE_RC_INT3 8 407 408 #endif /* _MIPS_ATHEROS_AR9344REG_H_ */ 409
Indexes created Sun Sep 21 18:09:52 GMT 2025