1 /* $NetBSD: vr4181giureg.h,v 1.2 2003/05/01 07:02:05 igy Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 SATO Kazumi. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of the project nor the names of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 32 /* 33 * VR4181 GIU (General Purpose I/O Unit) Registers. 34 */ 35 #define VR4181GIU_NO_REG_W 0xffffffff /* no register */ 36 37 #define VR4181GIU_MODE0_REG 0x00 38 #define VR4181GIU_MODE0_REG_W 0x00 39 #define VR4181GIU_MODE1_REG_W 0x02 40 #define VR4181GIU_MODE2_REG_W 0x04 41 #define VR4181GIU_MODE3_REG_W 0x06 42 43 #define VR4181GIU_MODE_GPIO 0x0 44 #define VR4181GIU_MODE_ALT 0x1 45 /* VR4181GIU_MODE_GPIO */ 46 #define VR4181GIU_MODE_IN 0x0 47 #define VR4181GIU_MODE_OUT 0x2 48 /* VR4181GIU_MODE_ALT */ 49 #define VR4181GIU_MODE_ALT1 0x0 50 #define VR4181GIU_MODE_ALT2 0x2 51 52 #define GP0_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 0) 53 #define GP0_CSISI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_ALT ) << 0) 54 #define GP0_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 0) 55 #define GP1_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 2) 56 #define GP1_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 2) 57 #define GP1_CSISO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_ALT ) << 2) 58 #define GP2_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 4) 59 #define GP2_CSICK ((VR4181GIU_MODE_IN | VR4181GIU_MODE_ALT ) << 4) 60 #define GP2_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 4) 61 #define GP3_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 6) 62 #define GP3_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 6) 63 #define GP3_PCS0 ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_ALT ) << 6) 64 #define GP4_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 8) 65 #define GP4_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 8) 66 #define GP5_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 10) 67 #define GP5_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 10) 68 #define GP5_DCD2 ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_ALT ) << 10) 69 #define GP6_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 12) 70 #define GP6_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 12) 71 #define GP6_RTS2 ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_ALT ) << 12) 72 #define GP7_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 14) 73 #define GP7_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 14) 74 #define GP7_DTR2 ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_ALT ) << 14) 75 #define GP8_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 0) 76 #define GP8_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 0) 77 #define GP8_DSR2 ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_ALT ) << 0) 78 #define GP9_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 2) 79 #define GP9_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 2) 80 #define GP9_CTS2 ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_ALT ) << 2) 81 #define GP10_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 4) 82 #define GP10_CSIFRM ((VR4181GIU_MODE_IN | VR4181GIU_MODE_ALT ) << 4) 83 #define GP10_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 4) 84 #define GP10_SYSCLK ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_ALT ) << 4) 85 #define GP11_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 6) 86 #define GP11_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 6) 87 #define GP11_PCS1 ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_ALT ) << 6) 88 #define GP12_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 8) 89 #define GP12_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 8) 90 #define GP12_LCDFPD4 ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_ALT ) << 8) 91 #define GP13_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 10) 92 #define GP13_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 10) 93 #define GP13_LCDPFD5 ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_ALT ) << 10) 94 #define GP14_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 12) 95 #define GP14_CD1 ((VR4181GIU_MODE_IN | VR4181GIU_MODE_ALT ) << 12) 96 #define GP14_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 12) 97 #define GP14_LCDPFD6 ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_ALT ) << 12) 98 #define GP15_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 14) 99 #define GP15_CD2 ((VR4181GIU_MODE_IN | VR4181GIU_MODE_ALT ) << 14) 100 #define GP15_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 14) 101 #define GP15_LCDFPD7 ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_ALT ) << 14) 102 #define GP16_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 0) 103 #define GP16_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 0) 104 #define GP16_IORD ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_ALT ) << 0) 105 #define GP17_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 2) 106 #define GP17_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 2) 107 #define GP17_IOWR ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_ALT ) << 2) 108 #define GP18_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 4) 109 #define GP18_IORDY ((VR4181GIU_MODE_IN | VR4181GIU_MODE_ALT ) << 4) 110 #define GP18_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 4) 111 #define GP19_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 6) 112 #define GP19_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 6) 113 #define GP19_IOCS16 ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_ALT ) << 6) 114 #define GP20_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 8) 115 #define GP20_LCDM ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 8) 116 #define GP20_UBE ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_ALT ) << 8) 117 #define GP21_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 10) 118 #define GP21_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 10) 119 #define GP21_RESET ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_ALT ) << 10) 120 #define GP22_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 12) 121 #define GP22_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 12) 122 #define GP22_ROMCS0 ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_ALT ) << 12) 123 #define GP23_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 14) 124 #define GP23_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 14) 125 #define GP23_ROMCS1 ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_ALT ) << 14) 126 #define GP24_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 0) 127 #define GP24_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 0) 128 #define GP24_ROMCS2 ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_ALT ) << 0) 129 #define GP25_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 2) 130 #define GP25_RxD1 ((VR4181GIU_MODE_IN | VR4181GIU_MODE_ALT ) << 2) 131 #define GP25_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 2) 132 #define GP26_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 4) 133 #define GP26_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 4) 134 #define GP26_TxD1 ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_ALT ) << 4) 135 #define GP27_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 6) 136 #define GP27_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 6) 137 #define GP27_RTS1 ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_ALT ) << 6) 138 #define GP28_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 8) 139 #define GP28_CTS1 ((VR4181GIU_MODE_IN | VR4181GIU_MODE_ALT ) << 8) 140 #define GP28_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 8) 141 #define GP29_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 10) 142 #define GP29_DCD1 ((VR4181GIU_MODE_IN | VR4181GIU_MODE_ALT ) << 10) 143 #define GP29_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 10) 144 #define GP30_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 12) 145 #define GP30_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 12) 146 #define GP30_DTR1 ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_ALT ) << 12) 147 #define GP31_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 14) 148 #define GP31_DSR1 ((VR4181GIU_MODE_IN | VR4181GIU_MODE_ALT ) << 14) 149 #define GP31_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 14) 150 151 152 #define VR4181GIU_PIOD_REG 0x08 153 #define VR4181GIU_PIOD_H_REG_W 0x08 154 #define VR4181GIU_PIOD_L_REG_W 0x0a 155 156 #define VR4181GIU_INTEN_REG_W 0x0c 157 #define GIEN0 (1U << 0) 158 #define GIEN1 (1U << 1) 159 #define GIEN2 (1U << 2) 160 #define GIEN3 (1U << 3) 161 #define GIEN4 (1U << 4) 162 #define GIEN5 (1U << 5) 163 #define GIEN6 (1U << 6) 164 #define GIEN7 (1U << 7) 165 #define GIEN8 (1U << 8) 166 #define GIEN9 (1U << 9) 167 #define GIEN10 (1U << 10) 168 #define GIEN11 (1U << 11) 169 #define GIEN12 (1U << 12) 170 #define GIEN13 (1U << 13) 171 #define GIEN14 (1U << 14) 172 #define GIEN15 (1U << 15) 173 174 #define VR4181GIU_INTMASK_REG_W 0x0e 175 #define GIMSK0 (1U << 0) 176 #define GIMSK1 (1U << 1) 177 #define GIMSK2 (1U << 2) 178 #define GIMSK3 (1U << 3) 179 #define GIMSK4 (1U << 4) 180 #define GIMSK5 (1U << 5) 181 #define GIMSK6 (1U << 6) 182 #define GIMSK7 (1U << 7) 183 #define GIMSK8 (1U << 8) 184 #define GIMSK9 (1U << 9) 185 #define GIMSK10 (1U << 10) 186 #define GIMSK11 (1U << 11) 187 #define GIMSK12 (1U << 12) 188 #define GIMSK13 (1U << 13) 189 #define GIMSK14 (1U << 14) 190 #define GIMSK15 (1U << 15) 191 192 #define VR4181GIU_INTTYP_REG 0x10 193 #define VR4181GIU_INTTYP_H_REG_W 0x10 194 #define VR4181GIU_INTTYP_L_REG_W 0x12 195 196 #define VR4181GIU_INTTYP_HIGH_LEVEL 0x3 197 #define VR4181GIU_INTTYP_LOW_LEVEL 0x2 198 #define VR4181GIU_INTTYP_RISING_EDGE 0x1 199 #define VR4181GIU_INTTYP_FALLING_EDGE 0x0 200 #define VR4181GIU_INTTYP_INVALID (-1) /* for validation check */ 201 202 #define I0TYP_HIGH_LEVEL (VR4181GIU_INTTYP_HIGH_LEVEL << 0) 203 #define I0TYP_LOW_LEVEL (VR4181GIU_INTTYP_LOW_LEVEL << 0) 204 #define I0TYP_RISING_EDGE (VR4181GIU_INTTYP_RISING_EDGE << 0) 205 #define I0TYP_FALLING_EDGE (VR4181GIU_INTTYP_FALLING_EDGE << 0) 206 207 #define I1TYP_HIGH_LEVEL (VR4181GIU_INTTYP_HIGH_LEVEL << 2) 208 #define I1TYP_LOW_LEVEL (VR4181GIU_INTTYP_LOW_LEVEL << 2) 209 #define I1TYP_RISING_EDGE (VR4181GIU_INTTYP_RISING_EDGE << 2) 210 #define I1TYP_FALLING_EDGE (VR4181GIU_INTTYP_FALLING_EDGE << 2) 211 212 #define I2TYP_HIGH_LEVEL (VR4181GIU_INTTYP_HIGH_LEVEL << 4) 213 #define I2TYP_LOW_LEVEL (VR4181GIU_INTTYP_LOW_LEVEL << 4) 214 #define I2TYP_RISING_EDGE (VR4181GIU_INTTYP_RISING_EDGE << 4) 215 #define I2TYP_FALLING_EDGE (VR4181GIU_INTTYP_FALLING_EDGE << 4) 216 217 #define I3TYP_HIGH_LEVEL (VR4181GIU_INTTYP_HIGH_LEVEL << 6) 218 #define I3TYP_LOW_LEVEL (VR4181GIU_INTTYP_LOW_LEVEL << 6) 219 #define I3TYP_RISING_EDGE (VR4181GIU_INTTYP_RISING_EDGE << 6) 220 #define I3TYP_FALLING_EDGE (VR4181GIU_INTTYP_FALLING_EDGE << 6) 221 222 #define I4TYP_HIGH_LEVEL (VR4181GIU_INTTYP_HIGH_LEVEL << 8) 223 #define I4TYP_LOW_LEVEL (VR4181GIU_INTTYP_LOW_LEVEL << 8) 224 #define I4TYP_RISING_EDGE (VR4181GIU_INTTYP_RISING_EDGE << 8) 225 #define I4TYP_FALLING_EDGE (VR4181GIU_INTTYP_FALLING_EDGE << 8) 226 227 #define I5TYP_HIGH_LEVEL (VR4181GIU_INTTYP_HIGH_LEVEL << 10) 228 #define I5TYP_LOW_LEVEL (VR4181GIU_INTTYP_LOW_LEVEL << 10) 229 #define I5TYP_RISING_EDGE (VR4181GIU_INTTYP_RISING_EDGE << 10) 230 #define I5TYP_FALLING_EDGE (VR4181GIU_INTTYP_FALLING_EDGE << 10) 231 232 #define I6TYP_HIGH_LEVEL (VR4181GIU_INTTYP_HIGH_LEVEL << 12) 233 #define I6TYP_LOW_LEVEL (VR4181GIU_INTTYP_LOW_LEVEL << 12) 234 #define I6TYP_RISING_EDGE (VR4181GIU_INTTYP_RISING_EDGE << 12) 235 #define I6TYP_FALLING_EDGE (VR4181GIU_INTTYP_FALLING_EDGE << 12) 236 237 #define I7TYP_HIGH_LEVEL (VR4181GIU_INTTYP_HIGH_LEVEL << 14) 238 #define I7TYP_LOW_LEVEL (VR4181GIU_INTTYP_LOW_LEVEL << 14) 239 #define I7TYP_RISING_EDGE (VR4181GIU_INTTYP_RISING_EDGE << 14) 240 #define I7TYP_FALLING_EDGE (VR4181GIU_INTTYP_FALLING_EDGE << 14) 241 242 #define I8TYP_HIGH_LEVEL (VR4181GIU_INTTYP_HIGH_LEVEL << 0) 243 #define I8TYP_LOW_LEVEL (VR4181GIU_INTTYP_LOW_LEVEL << 0) 244 #define I8TYP_RISING_EDGE (VR4181GIU_INTTYP_RISING_EDGE << 0) 245 #define I8TYP_FALLING_EDGE (VR4181GIU_INTTYP_FALLING_EDGE << 0) 246 247 #define I9TYP_HIGH_LEVEL (VR4181GIU_INTTYP_HIGH_LEVEL << 2) 248 #define I9TYP_LOW_LEVEL (VR4181GIU_INTTYP_LOW_LEVEL << 2) 249 #define I9TYP_RISING_EDGE (VR4181GIU_INTTYP_RISING_EDGE << 2) 250 #define I9TYP_FALLING_EDGE (VR4181GIU_INTTYP_FALLING_EDGE << 2) 251 252 #define I10TYP_HIGH_LEVEL (VR4181GIU_INTTYP_HIGH_LEVEL << 4) 253 #define I10TYP_LOW_LEVEL (VR4181GIU_INTTYP_LOW_LEVEL << 4) 254 #define I10TYP_RISING_EDGE (VR4181GIU_INTTYP_RISING_EDGE << 4) 255 #define I10TYP_FALLING_EDGE (VR4181GIU_INTTYP_FALLING_EDGE << 4) 256 257 #define I11TYP_HIGH_LEVEL (VR4181GIU_INTTYP_HIGH_LEVEL << 6) 258 #define I11TYP_LOW_LEVEL (VR4181GIU_INTTYP_LOW_LEVEL << 6) 259 #define I11TYP_RISING_EDGE (VR4181GIU_INTTYP_RISING_EDGE << 6) 260 #define I11TYP_FALLING_EDGE (VR4181GIU_INTTYP_FALLING_EDGE << 6) 261 262 #define I12TYP_HIGH_LEVEL (VR4181GIU_INTTYP_HIGH_LEVEL << 8) 263 #define I12TYP_LOW_LEVEL (VR4181GIU_INTTYP_LOW_LEVEL << 8) 264 #define I12TYP_RISING_EDGE (VR4181GIU_INTTYP_RISING_EDGE << 8) 265 #define I12TYP_FALLING_EDGE (VR4181GIU_INTTYP_FALLING_EDGE << 8) 266 267 #define I13TYP_HIGH_LEVEL (VR4181GIU_INTTYP_HIGH_LEVEL << 10) 268 #define I13TYP_LOW_LEVEL (VR4181GIU_INTTYP_LOW_LEVEL << 10) 269 #define I13TYP_RISING_EDGE (VR4181GIU_INTTYP_RISING_EDGE << 10) 270 #define I13TYP_FALLING_EDGE (VR4181GIU_INTTYP_FALLING_EDGE << 10) 271 272 #define I14TYP_HIGH_LEVEL (VR4181GIU_INTTYP_HIGH_LEVEL << 12) 273 #define I14TYP_LOW_LEVEL (VR4181GIU_INTTYP_LOW_LEVEL << 12) 274 #define I14TYP_RISING_EDGE (VR4181GIU_INTTYP_RISING_EDGE << 12) 275 #define I14TYP_FALLING_EDGE (VR4181GIU_INTTYP_FALLING_EDGE << 12) 276 277 #define I15TYP_HIGH_LEVEL (VR4181GIU_INTTYP_HIGH_LEVEL << 14) 278 #define I15TYP_LOW_LEVEL (VR4181GIU_INTTYP_LOW_LEVEL << 14) 279 #define I15TYP_RISING_EDGE (VR4181GIU_INTTYP_RISING_EDGE << 14) 280 #define I15TYP_FALLING_EDGE (VR4181GIU_INTTYP_FALLING_EDGE << 14) 281 282 #define VR4181GIU_INTSTAT_REG_W 0x14 283 284 #define VR4181GIU_HIBST_REG 0x16 285 #define VR4181GIU_HIBST_L_REG_W 0x16 286 #define VR4181GIU_HIBST_H_REG_W 0x18 287 288 #define VR4181GIU_SICTL_REG_W 0x1a 289 290 #define VR4181GIU_KEYEN_REG_W 0x1c 291 292 #define VR4181GIU_PCS0STRA_REG_W 0x20 293 #define VR4181GIU_PCS0STPA_REG_W 0x22 294 #define VR4181GIU_PCS0HIA_REG_W 0x24 295 #define VR4181GIU_PCS1STRA_REG_W 0x26 296 #define VR4181GIU_PCS1STPA_REG_W 0x28 297 #define VR4181GIU_PCS1HIA_REG_W 0x2a 298 299 #define VR4181GIU_PCSMODE_REG_W 0x2c 300 301 #define PCS0MD_DISABLE (0x0 << 0) 302 #define PCS0MD_READ (0x1 << 0) 303 #define PCS0MD_WRITE (0x2 << 0) 304 #define PCS0MD_READWRITE (0x3 << 0) 305 #define PCS0DSIZE_8BIT (0x0 << 2) 306 #define PCS0DSIZE_16BIT (0x1 << 2) 307 #define PCS0MIOB_IO (0x0 << 3) 308 #define PCS0MIOB_MEM (0x1 << 3) 309 #define PCS1MD_DISABLE (0x0 << 4) 310 #define PCS1MD_READ (0x1 << 4) 311 #define PCS1MD_WRITE (0x2 << 4) 312 #define PCS1MD_READWRITE (0x3 << 4) 313 #define PCS1DSIZE_8BIT (0x0 << 6) 314 #define PCS1DSIZE_16BIT (0x1 << 6) 315 #define PCS1MIOB_IO (0x0 << 7) 316 #define PCS1MIOB_MEM (0x1 << 7) 317 318 319 /* END vr4181giu.h */ 320
Indexes created Sun Sep 21 20:09:37 GMT 2025