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      1 /*-
      2  * Copyright (c) 2007 The NetBSD Foundation, Inc.
      3  * All rights reserved.
      4  *
      5  * This code is derived from software contributed to The NetBSD Foundation
      6  * by Matt Thomas.
      7  *
      8  * Redistribution and use in source and binary forms, with or without
      9  * modification, are permitted provided that the following conditions
     10  * are met:
     11  * 1. Redistributions of source code must retain the above copyright
     12  *    notice, this list of conditions and the following disclaimer.
     13  * 2. Redistributions in binary form must reproduce the above copyright
     14  *    notice, this list of conditions and the following disclaimer in the
     15  *    documentation and/or other materials provided with the distribution.
     16  *
     17  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     18  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     19  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     20  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     21  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     22  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     23  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     24  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     25  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     26  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     27  * POSSIBILITY OF SUCH DAMAGE.
     28  */
     29 #ifndef _ARM_IMX_IMXGPIOREG_H
     30 #define	_ARM_IMX_IMXGPIOREG_H
     31 
     32 #define	GPIO_SIZE	0x0020	/* Size of GPIO registers */
     33 
     34 #define	GPIO_DR		0x0000	/* GPIO Data (RW) */
     35 #define	GPIO_DIR	0x0004	/* GPIO Direction (RW), 1=Output */
     36 #define	GPIO_PSR	0x0008	/* GPIO Pad Status (R) */
     37 #define	GPIO_ICR1	0x000c	/* GPIO Interrupt Configuration 1 (RW) */
     38 #define	GPIO_ICR2	0x0010	/* GPIO Interrupt Configuration 2 (RW) */
     39 #define	GPIO_IMR	0x0014	/* GPIO Interrupt Mask (RW) */
     40 #define	GPIO_ISR	0x0018	/* GPIO Interrupt Status (RW, W1C) */
     41 #define	GPIO_EDGE_SEL	0x001c	/* GPIO Edge Select Register  (i.MX51 only) */
     42 
     43 #define	GPIO_ICR_LEVEL_LOW	0
     44 #define	GPIO_ICR_LEVEL_HIGH	1
     45 #define	GPIO_ICR_EDGE_RISING	2
     46 #define	GPIO_ICR_EDGE_FALLING	3
     47 
     48 #define	GPIO_NPINS		32
     49 
     50 #endif	/* _ARM_IMX_IMXGPIOREG_H */
     51