1 /* $NetBSD: gtidmacreg.h,v 1.5 2021/11/10 17:19:30 msaitoh Exp $ */ 2 /* 3 * Copyright (c) 2008, 2009 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #ifndef _GTIDMACREG_H_ 29 #define _GTIDMACREG_H_ 30 31 /* 32 * IDMA Controller Interface Registers / XOR Engine Control Registers 33 */ 34 35 #define GTIDMAC_SIZE 0x1000 36 37 38 #define GTIDMAC_NWINDOW 8 39 #define GTIDMAC_NREMAP 4 40 #define GTIDMAC_NACCPROT 4 /* Num Access Protect */ 41 #define GTIDMAC_NINTRRUPT 4 42 #define GTIDMAC_MAXXFER (16 * 1024 * 1024 - 1) /* 16M - 1 Byte */ 43 44 #define MVXORE_NWINDOW 8 45 #define MVXORE_NREMAP 4 46 #define MVXORE_MAXXFER (16 * 1024 * 1024 - 1) /* 16M - 1 Byte */ 47 #define MVXORE_NSRC 8 48 49 50 #define GTIDMAC_CHAN2BASE(c) ((((c) & 0x4) << 6) + (((c) & 0x3) << 2)) 51 #define MVXORE_PORT2BASE(sc, p) \ 52 (((sc)->sc_gtidmac_nchan == 0 && (p) == 0) ? -0x100 : 0x000) 53 #define MVXORE_CHAN2BASE(sc, c) \ 54 (MVXORE_PORT2BASE(sc, (c) & 0xe) + (((c) & 0x1) << 2)) 55 56 57 /* IDMA Descriptor Register Map */ 58 #define GTIDMAC_CIDMABCR(c) /* Chan IDMA Byte Count */ \ 59 (GTIDMAC_CHAN2BASE(c) + 0x0800) 60 #define GTIDMAC_CIDMABCR_BYTECNT_MASK 0x00ffffff 61 #define GTIDMAC_CIDMABCR_BCLEFT (1 << 30) /* Left Byte Count */ 62 #define GTIDMAC_CIDMABCR_OWN (1 << 31) /* Ownership Bit */ 63 #define GTIDMAC_CIDMASAR(c) /* Chan IDMA Source Address */ \ 64 (GTIDMAC_CHAN2BASE(c) + 0x0810) 65 #define GTIDMAC_CIDMADAR(c) /* Chan IDMA Destination Address */ \ 66 (GTIDMAC_CHAN2BASE(c) + 0x0820) 67 #define GTIDMAC_CNDPR(c) /* Chan Next Descriptor Pointer */ \ 68 (GTIDMAC_CHAN2BASE(c) + 0x0830) 69 #define GTIDMAC_CCDPR(c) /* Chan Current Descriptor Pointer */ \ 70 (GTIDMAC_CHAN2BASE(c) + 0x0870) 71 /* IDMA Control Register Map */ 72 #define GTIDMAC_CCLR(c) /* Chan Control Low */ \ 73 (GTIDMAC_CHAN2BASE(c) + 0x0840) 74 #define GTIDMAC_CCLR_DBL_MASK (7 << 0) /* DstBurstLimit */ 75 #define GTIDMAC_CCLR_DBL_8B (0 << 0) 76 #define GTIDMAC_CCLR_DBL_16B (1 << 0) 77 #define GTIDMAC_CCLR_DBL_32B (3 << 0) 78 #define GTIDMAC_CCLR_DBL_64B (7 << 0) 79 #define GTIDMAC_CCLR_DBL_128B (4 << 0) 80 #define GTIDMAC_CCLR_SRCHOLD (1 << 3) /* Source Hold */ 81 #define GTIDMAC_CCLR_DESTHOLD (1 << 5) /* Destination Hold */ 82 #define GTIDMAC_CCLR_SBL_MASK (7 << 6) /* SrcBurstLimit */ 83 #define GTIDMAC_CCLR_SBL_8B (0 << 6) 84 #define GTIDMAC_CCLR_SBL_16B (1 << 6) 85 #define GTIDMAC_CCLR_SBL_32B (3 << 6) 86 #define GTIDMAC_CCLR_SBL_64B (7 << 6) 87 #define GTIDMAC_CCLR_SBL_128B (4 << 6) 88 #define GTIDMAC_CCLR_CHAINMODE_C (0 << 9) /* Chained Mode */ 89 #define GTIDMAC_CCLR_CHAINMODE_NC (1 << 9) /* Non-Chained Mode */ 90 #define GTIDMAC_CCLR_INTMODE (1 << 10) /* Interrupt Mode */ 91 #define GTIDMAC_CCLR_INTMODE_NULL (1 << 10) /* Next Desc NULL */ 92 #define GTIDMAC_CCLR_TRANSFERMODE_D (0 << 11) /* Transfer Mode */ 93 #define GTIDMAC_CCLR_TRANSFERMODE_B (1 << 11) /* Demand/Block */ 94 #define GTIDMAC_CCLR_CHANEN (1 << 12) /* Channel Enable */ 95 #define GTIDMAC_CCLR_FETCHND (1 << 13) /* Fetch Next Desc */ 96 #define GTIDMAC_CCLR_CHANACT (1 << 14) /* IDMA Chan Active */ 97 #define GTIDMAC_CCLR_CDEN (1 << 17) /* Close Desc Enable */ 98 #define GTIDMAC_CCLR_ABR (1 << 20) /* Channel Abort */ 99 #define GTIDMAC_CCLR_SADDROVR_MASK (3 << 21) /* Override Src Addr */ 100 #define GTIDMAC_CCLR_SADDROVR_NO (0 << 21) 101 #define GTIDMAC_CCLR_SADDROVR_BAR1 (1 << 21) 102 #define GTIDMAC_CCLR_SADDROVR_BAR2 (2 << 21) 103 #define GTIDMAC_CCLR_SADDROVR_BAR3 (3 << 21) 104 #define GTIDMAC_CCLR_NADDROVR_MASK (3 << 21) /* Override Next Addr */ 105 #define GTIDMAC_CCLR_NADDROVR_NO (0 << 21) 106 #define GTIDMAC_CCLR_NADDROVR_BAR1 (1 << 21) 107 #define GTIDMAC_CCLR_NADDROVR_BAR2 (2 << 21) 108 #define GTIDMAC_CCLR_NADDROVR_BAR3 (3 << 21) 109 #define GTIDMAC_CCLR_DESCMODE_64K (0 << 31) 110 #define GTIDMAC_CCLR_DESCMODE_16M (1 << 31) 111 #define GTIDMAC_CCHR(c) /* Chan Control High */ \ 112 (GTIDMAC_CHAN2BASE(c) + 0x0880) 113 #define GTIDMAC_CCHR_ENDIAN_BE (0 << 0) /* big endian */ 114 #define GTIDMAC_CCHR_ENDIAN_LE (1 << 0) /* little endian */ 115 #define GTIDMAC_CCHR_DESCBYTESWAP (1 << 1) /* Desc Byte Swap */ 116 #define GTIDMAC_ARBR(c) (0x0860 + (((c) & 0x04) << 6)) /* Arbitrate ??*/ 117 #define GTIDMAC_XTOR(c) (0x08d0 + (((c) & 0x04) << 6)) /* x-bar t/o?? */ 118 /* IDMA Interrupt Register Map */ 119 #define GTIDMAC_ICR(c) (0x08c0 + (((c) & 0x04) << 6)) /* Intr Cause */ 120 #define GTIDMAC_IMR(c) (0x08c4 + (((c) & 0x04) << 6)) /* Intr Mask */ 121 #define GTIDMAC_I_BITS 8 122 #define GTIDMAC_I(c, b) ((b) << (GTIDMAC_I_BITS * ((c) & 0x3))) 123 #define GTIDMAC_I_COMP (1 << 0) /* Completion */ 124 #define GTIDMAC_I_ADDRMISS (1 << 1) /* Address Miss */ 125 #define GTIDMAC_I_ACCPROT (1 << 2) /* Acc Prot Violation */ 126 #define GTIDMAC_I_WRPROT (1 << 3) /* Write Protect */ 127 #define GTIDMAC_I_OWN (1 << 4) /* Ownership Violation*/ 128 #define GTIDMAC_EAR(c) (0x08c8 + (((c) & 0x04) << 6)) /* Err Address */ 129 #define GTIDMAC_ESR(c) (0x08cc + (((c) & 0x04) << 6)) /* Err Select */ 130 #define GTIDMAC_ESR_SEL 0x1f 131 132 /* XOR Engine Control Registers */ 133 #define MVXORE_XECHAR(sc, p) /* Channel Arbiter */ \ 134 (MVXORE_PORT2BASE((sc), (p)) + 0x0900) 135 #define MVXORE_XECHAR_SLICEOWN(s, c) ((c) << (s)) 136 #define MVXORE_XEXCR(sc, x) /* Configuration */ \ 137 (MVXORE_CHAN2BASE((sc), (x)) + 0x0910) 138 #define MVXORE_XEXCR_OM_MASK (7 << 0) /* Operation Mode */ 139 #define MVXORE_XEXCR_OM_XOR (0 << 0) 140 #define MVXORE_XEXCR_OM_CRC32 (1 << 0) 141 #define MVXORE_XEXCR_OM_DMA (2 << 0) 142 #define MVXORE_XEXCR_OM_ECC (3 << 0) /* ECC cleanup ope */ 143 #define MVXORE_XEXCR_OM_MEMINIT (4 << 0) 144 #define MVXORE_XEXCR_SBL_MASK (7 << 4) /* SrcBurstLimit */ 145 #define MVXORE_XEXCR_SBL_32B (2 << 4) 146 #define MVXORE_XEXCR_SBL_64B (3 << 4) 147 #define MVXORE_XEXCR_SBL_128B (4 << 4) 148 #define MVXORE_XEXCR_DBL_MASK (7 << 8) /* SrcBurstLimit */ 149 #define MVXORE_XEXCR_DBL_32B (2 << 8) 150 #define MVXORE_XEXCR_DBL_64B (3 << 8) 151 #define MVXORE_XEXCR_DBL_128B (4 << 8) 152 #define MVXORE_XEXCR_DRDRESSWP (1 << 12) /* Endianness Swap */ 153 #define MVXORE_XEXCR_DWRREQSWP (1 << 13) /* ReadReq/WriteRes */ 154 #define MVXORE_XEXCR_DESSWP (1 << 14) /* Desc read/write */ 155 #define MVXORE_XEXCR_REGACCPROTECT (1 << 15) /* Reg Access protect */ 156 #define MVXORE_XEXACTR(sc, x) /* Activation */ \ 157 (MVXORE_CHAN2BASE((sc), (x)) + 0x0920) 158 #define MVXORE_XEXACTR_XESTART (1 << 0) 159 #define MVXORE_XEXACTR_XESTOP (1 << 1) 160 #define MVXORE_XEXACTR_XEPAUSE (1 << 2) 161 #define MVXORE_XEXACTR_XERESTART (1 << 3) 162 #define MVXORE_XEXACTR_XESTATUS_MASK (3 << 4) 163 #define MVXORE_XEXACTR_XESTATUS_NA (0 << 4) /* not active */ 164 #define MVXORE_XEXACTR_XESTATUS_ACT (1 << 4) /* active */ 165 #define MVXORE_XEXACTR_XESTATUS_P (2 << 4) /* paused */ 166 /* XOR Engine Interrupt Registers */ 167 #define MVXORE_XEICR(sc, p) /* Interrupt Cause */ \ 168 (MVXORE_PORT2BASE((sc), (p)) + 0x0930) 169 #define MVXORE_XEIMR(sc, p) /* Interrupt Mask */ \ 170 (MVXORE_PORT2BASE((sc), (p)) + 0x0940) 171 #define MVXORE_I_BITS 16 172 #define MVXORE_I(c, b) ((b) << (MVXORE_I_BITS * (c))) 173 #define MVXORE_I_EOD (1 << 0) /* End of Descriptor */ 174 #define MVXORE_I_EOC (1 << 1) /* End of Chain */ 175 #define MVXORE_I_STOPPED (1 << 2) 176 #define MVXORE_I_PAUSED (1 << 3) 177 #define MVXORE_I_ADDRDECODE (1 << 4) 178 #define MVXORE_I_ACCPROT (1 << 5) /* Access Protect */ 179 #define MVXORE_I_WRPROT (1 << 6) /* Write Protect */ 180 #define MVXORE_I_OWN (1 << 7) /* Ownership */ 181 #define MVXORE_I_INTPARITY (1 << 8) /* Parity error */ 182 #define MVXORE_I_XBAR (1 << 9) /* Crossbar Parity E */ 183 #define MVXORE_XEECR(sc, p) /* Error Cause */ \ 184 (MVXORE_PORT2BASE((sc), (p)) + 0x0950) 185 #define MVXORE_XEECR_ERRORTYPE_MASK 0x0000001f 186 #define MVXORE_XEEAR(sc, p) /* Error Address */ \ 187 (MVXORE_PORT2BASE((sc), (p)) + 0x0960) 188 189 /* IDMA Address Decoding Registers Map */ 190 #define GTIDMAC_BARX(r) (0x0a00 + ((r) << 3)) /* Base Address x */ 191 #define GTIDMAC_BARX_TARGET(t) ((t) & 0xf) 192 #define GTIDMAC_BARX_ATTR(a) (((a) & 0xff) << 8) 193 #define GTIDMAC_BARX_BASE(b) ((b) & 0xffff0000) 194 #define GTIDMAC_SRX(r) (0x0a04 + ((r) << 3)) /* Size x */ 195 #define GTIDMAC_SRX_SIZE(s) (((s) - 1) & 0xffff0000) 196 #define GTIDMAC_HARXR(x) (0x0a60 + ((x) << 2)) /* High Addr Remap x */ 197 #define GTIDMAC_BAER 0x0a80 /* Base Addr Enable */ 198 #define GTIDMAC_BAER_EN(w) (1 << (w)) 199 #define GTIDMAC_CXAPR(x) (0x0a70 + ((x) << 2)) /* Chan x Acs Protect */ 200 #define GTIDMAC_CXAPR_WINACC(w, ac) ((ac) << ((w) << 1)) 201 #define GTIDMAC_CXAPR_WINACC_NOAA 0x0 /* No access allowed */ 202 #define GTIDMAC_CXAPR_WINACC_RO 0x1 /* Read Only */ 203 #define GTIDMAC_CXAPR_WINACC_RESV 0x2 /* Reserved */ 204 #define GTIDMAC_CXAPR_WINACC_FA 0x3 /* Full access */ 205 206 /* XOR Engine Descriptor Registers */ 207 #define MVXORE_XEXNDPR(sc, x) /* Next Desc Pointer */ \ 208 (MVXORE_CHAN2BASE((sc), (x)) + 0x0b00) 209 #define MVXORE_XEXCDPR(sc, x) /* Current Desc Ptr */ \ 210 (MVXORE_CHAN2BASE((sc), (x)) + 0x0b10) 211 #define MVXORE_XEXBCR(sc, x) /* Byte Count */ \ 212 (MVXORE_CHAN2BASE((sc), (x)) + 0x0b20) 213 /* XOR Engine Address Decording Registers */ 214 #define MVXORE_XEXWCR(sc, x) /* Window Control */ \ 215 (MVXORE_CHAN2BASE((sc), (x)) + 0x0b40) 216 #define MVXORE_XEXWCR_WINEN(w) (1 << (w)) 217 #define MVXORE_XEXWCR_WINACC(w, ac) ((ac) << (((w) << 1) + 16)) 218 #define MVXORE_XEXWCR_WINACC_NOAA 0x0 /* No access allowed */ 219 #define MVXORE_XEXWCR_WINACC_RO 0x1 /* Read Only */ 220 #define MVXORE_XEXWCR_WINACC_RESV 0x2 /* Reserved */ 221 #define MVXORE_XEXWCR_WINACC_FA 0x3 /* Full access */ 222 #define MVXORE_XEBARX(sc, p, w) /* Base Address */ \ 223 (MVXORE_PORT2BASE((sc), (p)) + 0x0b50 + ((w) << 2)) 224 #define MVXORE_XEBARX_TARGET(t) ((t) & 0xf) 225 #define MVXORE_XEBARX_ATTR(a) (((a) & 0xff) << 8) 226 #define MVXORE_XEBARX_BASE(b) ((b) & 0xffff0000) 227 #define MVXORE_XESMRX(sc, p, w) /* Size Mask */ \ 228 (MVXORE_PORT2BASE((sc), (p)) + 0x0b70 + ((w) << 2)) 229 #define MVXORE_XESMRX_SIZE(s) (((s) - 1) & 0xffff0000) 230 #define MVXORE_XEHARRX(sc, p, w)/* High Address Remap */ \ 231 (MVXORE_PORT2BASE((sc), (p)) + 0x0b90 + ((w) << 2)) 232 #define MVXORE_XEXAOCR(sc, x) /* Addr Override Ctrl */ \ 233 (MVXORE_CHAN2BASE((sc), (x)) + 0x0ba0) 234 /* XOR Engine ECC/MemInit Registers */ 235 #define MVXORE_XEXDPR(sc, x) /* Destination Ptr */ \ 236 (MVXORE_CHAN2BASE((sc), (x)) + 0x0bb0) 237 #define MVXORE_XEXBSR(sc, x) /* Block Size */ \ 238 (MVXORE_CHAN2BASE((sc), (x)) + 0x0bc0) 239 #define MVXORE_XETMCR(sc, p) /* Timer Mode Control */ \ 240 (MVXORE_PORT2BASE((sc), (p)) + 0x0bd0) 241 #define MVXORE_XETMCR_TIMEREN (1 << 0) 242 #define MVXORE_XETMCR_SECTIONSIZECTRL_MASK 0x1f 243 #define MVXORE_XETMCR_SECTIONSIZECTRL_SHIFT 8 244 #define MVXORE_XETMIVR(sc, p) /* Tmr Mode Init Val */ \ 245 (MVXORE_PORT2BASE((sc), (p)) + 0x0bd4) 246 #define MVXORE_XETMCVR(sc, p) /* Tmr Mode Curr Val */ \ 247 (MVXORE_PORT2BASE((sc), (p)) + 0x0bd8) 248 #define MVXORE_XEIVRL(sc, p) /* Initial Value Low */ \ 249 (MVXORE_PORT2BASE((sc), (p)) + 0x0be0) 250 #define MVXORE_XEIVRH(sc, p) /* Initial Value High */ \ 251 (MVXORE_PORT2BASE((sc), (p)) + 0x0be4) 252 253 254 struct gtidmac_desc { 255 #if BYTE_ORDER == LITTLE_ENDIAN 256 union { 257 struct { 258 uint16_t rbc; /* Remind BC */ 259 uint16_t bcnt; 260 } mode64k; 261 struct { 262 uint32_t bcnt; 263 } mode16m; 264 } bc; /* Byte Count */ 265 uint32_t srcaddr; /* Source Address */ 266 uint32_t dstaddr; /* Destination Address */ 267 uint32_t nextdp; /* Next Descriptor Pointer */ 268 #else 269 uint32_t srcaddr; /* Source Address */ 270 union { 271 struct { 272 uint16_t rbc; /* Remind BC */ 273 uint16_t bcnt; 274 } mode64k; 275 struct { 276 uint32_t bcnt; 277 } mode16m; 278 } bc; /* Byte Count */ 279 uint32_t nextdp; /* Next Descriptor Pointer */ 280 uint32_t dstaddr; /* Destination Address */ 281 #endif 282 } __packed; 283 284 #define GTIDMAC_DESC_BYTECOUNT_MASK 0x00ffffff 285 286 struct mvxore_desc { 287 uint32_t stat; /* Status */ 288 uint32_t result; /* CRC-32 Result */ 289 uint32_t cmd; /* Command */ 290 uint32_t nextda; /* Next Descriptor Address */ 291 uint32_t bcnt; /* Byte Count */ 292 uint32_t dstaddr; /* Destination Address */ 293 uint32_t srcaddr[MVXORE_NSRC]; /* Source Address #0-7 */ 294 uint32_t reserved[2]; 295 } __packed; 296 297 #define MVXORE_DESC_STAT_SUCCESS (1 << 30) 298 #define MVXORE_DESC_STAT_OWN (1 << 31) 299 300 #define MVXORE_DESC_CMD_SRCCMD(s) (1 << (s)) 301 #define MVXORE_DESC_CMD_CRCLAST (1 << 30) /* Indicate last desc CRC32 */ 302 #define MVXORE_DESC_CMD_EODINTEN (1 << 31) /* End of Desc Intr Enable */ 303 304 #define MVXORE_DESC_BCNT_MASK 0x00ffffff 305 306 #endif /* _GTIDMACREG_H_ */ 307
Indexes created Sat Sep 20 22:09:52 GMT 2025