1 /* $NetBSD: intel_pch.h,v 1.2 2021/12/18 23:45:28 riastradh Exp $ */ 2 3 /* SPDX-License-Identifier: MIT */ 4 /* 5 * Copyright 2019 Intel Corporation. 6 */ 7 8 #ifndef __INTEL_PCH__ 9 #define __INTEL_PCH__ 10 11 struct drm_i915_private; 12 13 /* 14 * Sorted by south display engine compatibility. 15 * If the new PCH comes with a south display engine that is not 16 * inherited from the latest item, please do not add it to the 17 * end. Instead, add it right after its "parent" PCH. 18 */ 19 enum intel_pch { 20 PCH_NOP = -1, /* PCH without south display */ 21 PCH_NONE = 0, /* No PCH present */ 22 PCH_IBX, /* Ibexpeak PCH */ 23 PCH_CPT, /* Cougarpoint/Pantherpoint PCH */ 24 PCH_LPT, /* Lynxpoint/Wildcatpoint PCH */ 25 PCH_SPT, /* Sunrisepoint/Kaby Lake PCH */ 26 PCH_CNP, /* Cannon/Comet Lake PCH */ 27 PCH_ICP, /* Ice Lake PCH */ 28 PCH_JSP, /* Jasper Lake PCH */ 29 PCH_MCC, /* Mule Creek Canyon PCH */ 30 PCH_TGP, /* Tiger Lake PCH */ 31 }; 32 33 #define INTEL_PCH_DEVICE_ID_MASK 0xff80 34 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 35 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 36 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 37 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 38 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 39 #define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80 40 #define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80 41 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100 42 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00 43 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280 44 #define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300 45 #define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80 46 #define INTEL_PCH_CMP_DEVICE_ID_TYPE 0x0280 47 #define INTEL_PCH_CMP2_DEVICE_ID_TYPE 0x0680 48 #define INTEL_PCH_CMP_V_DEVICE_ID_TYPE 0xA380 49 #define INTEL_PCH_ICP_DEVICE_ID_TYPE 0x3480 50 #define INTEL_PCH_MCC_DEVICE_ID_TYPE 0x4B00 51 #define INTEL_PCH_TGP_DEVICE_ID_TYPE 0xA080 52 #define INTEL_PCH_TGP2_DEVICE_ID_TYPE 0x4380 53 #define INTEL_PCH_JSP_DEVICE_ID_TYPE 0x4D80 54 #define INTEL_PCH_JSP2_DEVICE_ID_TYPE 0x3880 55 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100 56 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000 57 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */ 58 59 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type) 60 #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id) 61 #define HAS_PCH_JSP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_JSP) 62 #define HAS_PCH_MCC(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MCC) 63 #define HAS_PCH_TGP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_TGP) 64 #define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP) 65 #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP) 66 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT) 67 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT) 68 #define HAS_PCH_LPT_LP(dev_priv) \ 69 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \ 70 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE) 71 #define HAS_PCH_LPT_H(dev_priv) \ 72 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_DEVICE_ID_TYPE || \ 73 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_DEVICE_ID_TYPE) 74 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT) 75 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX) 76 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP) 77 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE) 78 79 void intel_detect_pch(struct drm_i915_private *dev_priv); 80 81 #endif /* __INTEL_PCH__ */ 82
Indexes created Sat Sep 20 22:09:52 GMT 2025