1 /* $NetBSD: igsfbreg.h,v 1.9 2023/07/31 20:48:04 andvar Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Valeriy E. Ushakov 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * Integraphics Systems IGA 168x and CyberPro series. 32 * Only tested on IGA 1682 in Krups JavaStation-NC. 33 */ 34 #ifndef _DEV_IC_IGSFBREG_H_ 35 #define _DEV_IC_IGSFBREG_H_ 36 37 /* 38 * Magic address decoding for memory space accesses in CyberPro. 39 */ 40 #define IGS_MEM_MMIO_SELECT 0x00800000 /* memory mapped i/o */ 41 #define IGS_MEM_BE_SELECT 0x00400000 /* endian select */ 42 43 /* 44 * Cursor sprite data in linear memory at IGS_EXT_SPRITE_DATA_{LO,HI}. 45 * 64x64 pixels, 2bpp = 1Kb 46 */ 47 #define IGS_CURSOR_DATA_SIZE 1024 48 49 50 /* 51 * Starting up the chip. 52 */ 53 54 /* Video Enable/Setup */ 55 #define IGS_VDO 0x46e8 56 #define IGS_VDO_ENABLE 0x08 57 #define IGS_VDO_SETUP 0x10 58 59 /* Video Enable */ 60 #define IGS_VSE 0x102 61 #define IGS_VSE_ENABLE 0x01 62 63 64 /* 65 * We map only 32 bytes of actual IGS registers at 0x3c0..0x3df. 66 * This macro helps to define register names using their "absolute" 67 * locations - it makes matching defines against docs easier. 68 */ 69 #define IGS_REG_BASE 0x3c0 70 #define IGS_REG_SIZE 0x020 71 #define IGS_REG_(x) ((x) - IGS_REG_BASE) 72 73 74 /* 75 * Attribute controller. Flip-flop reset by IGS_INPUT_STATUS1 at 0x3da. 76 * We don't bother defining actual registers, we only use them once 77 * during video initialization. 78 */ 79 #define IGS_ATTR_IDX IGS_REG_(0x3c0) 80 #define IGS_ATTR_PORT IGS_REG_(0x3c1) 81 82 83 /* 84 * Misc output register. We only use the _W register during video 85 * initialization. 86 */ 87 #define IGS_MISC_OUTPUT_W IGS_REG_(0x3c2) 88 #define IGS_MISC_OUTPUT_R IGS_REG_(0x3cc) 89 90 91 /* 92 * SEQUENCER. 93 */ 94 #define IGS_SEQ_IDX IGS_REG_(0x3c4) 95 #define IGS_SEQ_PORT IGS_REG_(0x3c5) 96 97 #define IGS_SEQ_RESET 0x0 98 #define IGS_SEQ_RESET_ASYNC 0x01 99 #define IGS_SEQ_RESET_SYNC 0x02 100 101 102 /* IGS_EXT_SPRITE_CTL/IGS_EXT_SPRITE_DAC_PEL (3cf/56[2]) == 0 */ 103 #define IGS_PEL_MASK IGS_REG_(0x3c6) 104 105 /* IGS_EXT_SPRITE_CTL/IGS_EXT_SPRITE_DAC_PEL 3cf/56[2] == 1 */ 106 #define IGS_DAC_CMD IGS_REG_(0x3c6) 107 108 109 /* 110 * Palette Read/Write: write palette index to the index port. 111 * Read/write R/G/B in three consecutive accesses to data port. 112 * After third access to data the index is autoincremented and you can 113 * proceed with reading/writing data port for the next entry. 114 * 115 * When IGS_EXT_SPRITE_DAC_PEL bit in sprite control is set, these 116 * registers are used to access sprite (i.e. cursor) 2-color palette. 117 * (NB: apparently, in this mode index autoincrement doesn't work). 118 */ 119 #define IGS_DAC_PEL_READ_IDX IGS_REG_(0x3c7) 120 #define IGS_DAC_PEL_WRITE_IDX IGS_REG_(0x3c8) 121 #define IGS_DAC_PEL_DATA IGS_REG_(0x3c9) 122 123 124 /* 125 * GRAPHICS CONTROLLER registers. 126 */ 127 #define IGS_GRFX_IDX IGS_REG_(0x3ce) 128 #define IGS_GRFX_PORT IGS_REG_(0x3cf) 129 130 131 /* 132 * EXTENDED registers. 133 */ 134 #define IGS_EXT_IDX IGS_REG_(0x3ce) 135 #define IGS_EXT_PORT IGS_REG_(0x3cf) 136 137 /* [3..0] -> [19..16] of start addr if IGS_EXT_START_ADDR_ON is set */ 138 #define IGS_EXT_START_ADDR 0x10 139 #define IGS_EXT_START_ADDR_ON 0x10 140 141 /* overflow 10th bits for severl crtc registers; interlaced mode select */ 142 #define IGS_EXT_VOVFL 0x11 143 #define IGS_EXT_VOVFL_INTERLACED 0x20 144 145 #define IGS_EXT_IRQ_CTL 0x12 146 #define IGS_EXT_IRQ_ENABLE 0x01 147 148 149 150 /* 151 * Sync Control. 152 * Two-bit combinations for h/v: 153 * 00 - normal, 01 - force 0, 1x - force 1 154 */ 155 #define IGS_EXT_SYNC_CTL 0x16 156 #define IGS_EXT_SYNC_H0 0x01 157 #define IGS_EXT_SYNC_H1 0x02 158 #define IGS_EXT_SYNC_V0 0x04 159 #define IGS_EXT_SYNC_V1 0x08 160 161 /* 162 * For PCI just use normal BAR config. 163 */ 164 #define IGS_EXT_BUS_CTL 0x30 165 #define IGS_EXT_BUS_CTL_LINSIZE_SHIFT 0 166 #define IGS_EXT_BUS_CTL_LINSIZE_MASK 0x03 167 #define IGS_EXT_BUS_CTL_LINSIZE(x) \ 168 (((x) >> IGS_EXT_BUS_CTL_LINSIZE_SHIFT) & IGS_EXT_BUS_CTL_LINSIZE_MASK) 169 170 /* 171 * COPREN - enable direct access to coprocessor registers 172 * COPASELB - select IGS_COP_BASE_B for COP address 173 */ 174 #define IGS_EXT_BIU_MISC_CTL 0x33 175 #define IGS_EXT_BIU_LINEAREN 0x01 176 #define IGS_EXT_BIU_LIN2MEM 0x02 177 #define IGS_EXT_BIU_COPREN 0x04 178 #define IGS_EXT_BIU_COPASELB 0x08 179 #define IGS_EXT_BIU_SEGON 0x10 180 #define IGS_EXT_BIU_SEG2MEM 0x20 181 182 /* 183 * Linear Address registers 184 * PCI: don't write directly, just use normal PCI configuration 185 * ISA: only bits [23..20] are programmable, the rest MBZ 186 */ 187 #define IGS_EXT_LINA_LO 0x34 /* [3..0] -> [23..20] */ 188 #define IGS_EXT_LINA_HI 0x35 /* [7..0] -> [31..24] */ 189 190 /* Hardware cursor on-screen location and hot spot */ 191 #define IGS_EXT_SPRITE_HSTART_LO 0x50 192 #define IGS_EXT_SPRITE_HSTART_HI 0x51 /* bits [2..0] */ 193 #define IGS_EXT_SPRITE_HPRESET 0x52 /* bits [5..0] */ 194 195 #define IGS_EXT_SPRITE_VSTART_LO 0x53 196 #define IGS_EXT_SPRITE_VSTART_HI 0x54 /* bits [2..0] */ 197 #define IGS_EXT_SPRITE_VPRESET 0x55 /* bits [5..0] */ 198 199 /* Hardware cursor control */ 200 #define IGS_EXT_SPRITE_CTL 0x56 201 #define IGS_EXT_SPRITE_VISIBLE 0x01 202 #define IGS_EXT_SPRITE_64x64 0x02 203 #define IGS_EXT_SPRITE_DAC_PEL 0x04 204 /* bits unrelated to sprite control */ 205 #define IGS_EXT_COP_RESET 0x08 206 207 /* Extended graphics mode */ 208 #define IGS_EXT_GRFX_MODE 0x57 209 #define IGS_EXT_GRFX_MODE_EXT 0x01 210 211 /* Overscan R/G/B registers */ 212 #define IGS_EXT_OVERSCAN_RED 0x58 213 #define IGS_EXT_OVERSCAN_GREEN 0x59 214 #define IGS_EXT_OVERSCAN_BLUE 0x5a 215 216 /* Memory controller */ 217 #define IGS_EXT_MEM_CTL0 0x70 218 #define IGS_EXT_MEM_CTL1 0x71 219 #define IGS_EXT_MEM_CTL2 0x72 220 221 /* 222 * SEQ miscellaneous: number of SL between CCLK - controls visual depth. 223 * These values are for MODE256 == 1, SRMODE = 1 in GRFX/5 mode register. 224 */ 225 #define IGS_EXT_SEQ_MISC 0x77 226 #define IGS_EXT_SEQ_IBM_STD 0 227 #define IGS_EXT_SEQ_8BPP 1 /* 256 indexed */ 228 #define IGS_EXT_SEQ_16BPP 2 /* HiColor 16bpp, 5-6-5 */ 229 #define IGS_EXT_SEQ_32BPP 3 /* TrueColor 32bpp */ 230 #define IGS_EXT_SEQ_24BPP 4 /* TrueColor 24bpp */ 231 #define IGS_EXT_SEQ_15BPP 6 /* HiColor 16bpp, 5-5-5 */ 232 233 /* Hardware cursor data location in linear memory */ 234 #define IGS_EXT_SPRITE_DATA_LO 0x7e 235 #define IGS_EXT_SPRITE_DATA_HI 0x7f /* bits [3..0] */ 236 237 238 #define IGS_EXT_VCLK0 0xb0 /* mult */ 239 #define IGS_EXT_VCLK1 0xb1 /* div */ 240 #define IGS_EXT_MCLK0 0xb2 /* mult */ 241 #define IGS_EXT_MCLK1 0xb3 /* div */ 242 243 244 /* ----8<---- end of IGS_EXT registers ----8<---- */ 245 246 247 248 /* 249 * CRTC can be at 0x3b4/0x3b5 (mono) or 0x3d4/0x3d5 (color) 250 * controlled by bit 0 in misc output register (r=0x3cc/w=0x3c2). 251 * We forcibly init it to color. 252 */ 253 #define IGS_CRTC_IDX IGS_REG_(0x3d4) 254 #define IGS_CRTC_PORT IGS_REG_(0x3d5) 255 256 /* 257 * Reading this register resets flip-flop at 0x3c0 (attribute 258 * controller) to address register. 259 */ 260 #define IGS_INPUT_STATUS1 IGS_REG_(0x3da) 261 262 263 264 /********************************************************************* 265 * IGS Graphic Coprocessor 266 */ 267 268 /* 269 * Coprocessor registers location in I/O space. 270 * Controlled by COPASELB bit in IGS_EXT_BIU_MISC_CTL. 271 */ 272 #define IGS_COP_BASE_A 0xaf000 /* COPASELB == 0 */ 273 #define IGS_COP_BASE_B 0xbf000 /* COPASELB == 1 */ 274 #define IGS_COP_SIZE 0x00400 275 276 277 /* 278 * NB: Loaded width values should be 1 less than the actual width! 279 */ 280 281 /* 282 * Coprocessor control. 283 */ 284 #define IGS_COP_CTL_REG 0x011 285 #define IGS_COP_CTL_HBRDYZ 0x01 286 #define IGS_COP_CTL_HFEMPTZ 0x02 287 #define IGS_COP_CTL_CMDFF 0x04 288 #define IGS_COP_CTL_SOP 0x08 /* rw */ 289 #define IGS_COP_CTL_OPS 0x10 290 #define IGS_COP_CTL_TER 0x20 /* rw */ 291 #define IGS_COP_CTL_HBACKZ 0x40 292 #define IGS_COP_CTL_BUSY 0x80 293 294 295 /* 296 * Source(s) and destination widths. 297 * 16 bit registers. Only bits [11..0] are used. 298 */ 299 #define IGS_COP_SRC_MAP_WIDTH_REG 0x018 300 #define IGS_COP_SRC2_MAP_WIDTH_REG 0x118 301 #define IGS_COP_DST_MAP_WIDTH_REG 0x218 302 303 304 /* 305 * Bitmap depth. 306 */ 307 #define IGS_COP_MAP_FMT_REG 0x01c 308 #define IGS_COP_MAP_8BPP 0x00 309 #define IGS_COP_MAP_16BPP 0x01 310 #define IGS_COP_MAP_24BPP 0x02 311 #define IGS_COP_MAP_32BPP 0x03 312 313 314 /* 315 * Binary operations are defined below. S - source, D - destination, 316 * N - not; a - and, o - or, x - xor. 317 * 318 * For ternary operations, foreground mix function is one of 256 319 * ternary raster operations defined by Win32 API; background mix is 320 * ignored. 321 */ 322 #define IGS_COP_FG_MIX_REG 0x048 323 #define IGS_COP_BG_MIX_REG 0x049 324 325 #define IGS_COP_MIX_0 0x0 326 #define IGS_COP_MIX_SaD 0x1 327 #define IGS_COP_MIX_SaND 0x2 328 #define IGS_COP_MIX_S 0x3 329 #define IGS_COP_MIX_NSaD 0x4 330 #define IGS_COP_MIX_D 0x5 331 #define IGS_COP_MIX_SxD 0x6 332 #define IGS_COP_MIX_SoD 0x7 333 #define IGS_COP_MIX_NSaND 0x8 334 #define IGS_COP_MIX_SxND 0x9 335 #define IGS_COP_MIX_ND 0xa 336 #define IGS_COP_MIX_SoND 0xb 337 #define IGS_COP_MIX_NS 0xc 338 #define IGS_COP_MIX_NSoD 0xd 339 #define IGS_COP_MIX_NSoND 0xe 340 #define IGS_COP_MIX_1 0xf 341 342 343 /* 344 * Foreground/background colours (24 bit). 345 * Selected by bits in IGS_COP_PIXEL_OP_3_REG. 346 */ 347 #define IGS_COP_FG_REG 0x058 348 #define IGS_COP_BG_REG 0x05C 349 350 351 /* 352 * Horizontal/vertical dimensions of pixel blit function. 353 * 16 bit registers. Only [11..0] are used. 354 */ 355 #define IGS_COP_WIDTH_REG 0x060 356 #define IGS_COP_HEIGHT_REG 0x062 357 358 359 /* 360 * Only bits [21..0] are used. 361 */ 362 #define IGS_COP_SRC_BASE_REG 0x070 /* only for 24bpp Src Color Tiling */ 363 #define IGS_COP_SRC_START_REG 0x170 364 #define IGS_COP_SRC2_START_REG 0x174 365 #define IGS_COP_DST_START_REG 0x178 366 367 /* 368 * Destination phase angle for 24bpp. 369 */ 370 #define IGS_COP_DST_X_PHASE_REG 0x078 371 #define IGS_COP_DST_X_PHASE_MASK 0x07 372 373 374 /* 375 * Pixel operation: Direction and draw mode. 376 * When an octant bit is set, that axis is traversed backwards. 377 */ 378 #define IGS_COP_PIXEL_OP_0_REG 0x07c 379 380 #define IGS_COP_OCTANT_Y_NEG 0x02 /* 0: top down, 1: bottom up */ 381 #define IGS_COP_OCTANT_X_NEG 0x04 /* 0: l2r, 1: r2l */ 382 383 #define IGS_COP_DRAW_ALL 0x00 384 #define IGS_COP_DRAW_FIRST_NULL 0x10 385 #define IGS_COP_DRAW_LAST_NULL 0x20 386 387 388 /* 389 * Pixel operation: Pattern operation. 390 */ 391 #define IGS_COP_PIXEL_OP_1_REG 0x07d 392 393 #define IGS_COP_PPM_TEXT 0x10 394 #define IGS_COP_PPM_TILE 0x20 395 #define IGS_COP_PPM_LINE 0x30 396 #define IGS_COP_PPM_TRANSPARENT 0x40 /* "or" with one of the above */ 397 398 #define IGS_COP_PPM_FIXED_FG 0x80 399 #define IGS_COP_PPM_SRC_COLOR_TILE 0x90 400 401 402 /* 403 * Pixel operation: Host CPU access (host blit) to graphics engine. 404 */ 405 #define IGS_COP_PIXEL_OP_2_REG 0x07e 406 #define IGS_COP_HBLTR 0x01 /* enable read from engine */ 407 #define IGS_COP_HBLTW 0x02 /* enable write to engine */ 408 409 410 /* 411 * Pixel operation: Operation function of graphic engine. 412 */ 413 #define IGS_COP_PIXEL_OP_3_REG 0x07f 414 #define IGS_COP_OP_STROKE 0x04 /* short stroke */ 415 #define IGS_COP_OP_LINE 0x05 /* bresenham line draw */ 416 #define IGS_COP_OP_PXBLT 0x08 /* pixel blit */ 417 #define IGS_COP_OP_PXBLT_INV 0x09 /* invert pixel blit */ 418 #define IGS_COP_OP_PXBLT_3 0x0a /* ternary pixel blit */ 419 420 /* select fg/bg source: 0 - fg/bg color reg, 1 - src1 map */ 421 #define IGS_COP_OP_FG_FROM_SRC 0x20 422 #define IGS_COP_OP_BG_FROM_SRC 0x80 423 424 #define IGS_CLOCK_REF 14318 /*24576*/ /* KHz */ 425 426 #define IGS_SCALE(p) ((p) ? (2 * (p)) : 1) 427 428 #define IGS_CLOCK(m,n,p) \ 429 ((IGS_CLOCK_REF * ((m) + 1)) / (((n) + 1) * IGS_SCALE(p))) 430 431 #define IGS_MAX_CLOCK 260000 432 433 #define IGS_MIN_VCO 115000 434 435 #endif /* _DEV_IC_IGSFBREG_H_ */ 436
Indexes created Sat Sep 20 22:09:52 GMT 2025