1 /* $NetBSD: armreg.h,v 1.136 2022/12/03 20:24:21 ryo Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001 Ben Harris 5 * Copyright (c) 1994-1996 Mark Brinicombe. 6 * Copyright (c) 1994 Brini. 7 * All rights reserved. 8 * 9 * This code is derived from software written for Brini by Mark Brinicombe 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by Brini. 22 * 4. The name of the company nor the name of the author may be used to 23 * endorse or promote products derived from this software without specific 24 * prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 28 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 31 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 32 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 */ 38 39 #ifndef _ARM_ARMREG_H 40 #define _ARM_ARMREG_H 41 42 #include <arm/cputypes.h> 43 44 #ifdef __arm__ 45 46 /* 47 * ARM Process Status Register 48 * 49 * The picture in the ARM manuals looks like this: 50 * 3 3 2 2 2 2 51 * 1 0 9 8 7 6 8 7 6 5 4 0 52 * +-+-+-+-+-+-------------------------------------+-+-+-+---------+ 53 * |N|Z|C|V|Q| reserved |I|F|T|M M M M M| 54 * | | | | | | | | | |4 3 2 1 0| 55 * +-+-+-+-+-+-------------------------------------+-+-+-+---------+ 56 */ 57 58 #define PSR_FLAGS 0xf0000000 /* flags */ 59 #define PSR_N_bit (1 << 31) /* negative */ 60 #define PSR_Z_bit (1 << 30) /* zero */ 61 #define PSR_C_bit (1 << 29) /* carry */ 62 #define PSR_V_bit (1 << 28) /* overflow */ 63 64 #define PSR_Q_bit (1 << 27) /* saturation */ 65 #define PSR_IT1_bit (1 << 26) 66 #define PSR_IT0_bit (1 << 25) 67 #define PSR_J_bit (1 << 24) /* Jazelle mode */ 68 #define PSR_GE_bits (15 << 16) /* SIMD GE bits */ 69 #define PSR_IT7_bit (1 << 15) 70 #define PSR_IT6_bit (1 << 14) 71 #define PSR_IT5_bit (1 << 13) 72 #define PSR_IT4_bit (1 << 12) 73 #define PSR_IT3_bit (1 << 11) 74 #define PSR_IT2_bit (1 << 10) 75 #define PSR_E_BIT (1 << 9) /* Endian state */ 76 #define PSR_A_BIT (1 << 8) /* Async abort disable */ 77 78 #define I32_bit (1 << 7) /* IRQ disable */ 79 #define F32_bit (1 << 6) /* FIQ disable */ 80 #define IF32_bits (3 << 6) /* IRQ/FIQ disable */ 81 82 #define PSR_T_bit (1 << 5) /* Thumb state */ 83 84 #define PSR_MODE 0x0000001f /* mode mask */ 85 #define PSR_USR32_MODE 0x00000010 86 #define PSR_FIQ32_MODE 0x00000011 87 #define PSR_IRQ32_MODE 0x00000012 88 #define PSR_SVC32_MODE 0x00000013 89 #define PSR_MON32_MODE 0x00000016 90 #define PSR_ABT32_MODE 0x00000017 91 #define PSR_HYP32_MODE 0x0000001a 92 #define PSR_UND32_MODE 0x0000001b 93 #define PSR_SYS32_MODE 0x0000001f 94 #define PSR_32_MODE 0x00000010 95 96 #define R15_FLAGS 0xf0000000 97 #define R15_FLAG_N 0x80000000 98 #define R15_FLAG_Z 0x40000000 99 #define R15_FLAG_C 0x20000000 100 #define R15_FLAG_V 0x10000000 101 102 /* 103 * Co-processor 15: The system control co-processor. 104 */ 105 106 #define ARM_CP15_CPU_ID 0 107 108 /* CPUID registers */ 109 #define ARM_ISA3_SYNCHPRIM_MASK 0x0000f000 110 #define ARM_ISA4_SYNCHPRIM_MASK 0x00f00000 111 #define ARM_ISA3_SYNCHPRIM_LDREX 0x10 // LDREX 112 #define ARM_ISA3_SYNCHPRIM_LDREXPLUS 0x13 // +CLREX/LDREXB/LDREXH 113 #define ARM_ISA3_SYNCHPRIM_LDREXD 0x20 // +LDREXD 114 #define ARM_PFR0_THUMBEE_MASK 0x0000f000 115 #define ARM_PFR1_GTIMER_MASK 0x000f0000 116 #define ARM_PFR1_VIRT_MASK 0x0000f000 117 #define ARM_PFR1_SEC_MASK 0x000000f0 118 119 /* Media and VFP Feature registers */ 120 #define ARM_MVFR0_ROUNDING_MASK 0xf0000000 121 #define ARM_MVFR0_SHORTVEC_MASK 0x0f000000 122 #define ARM_MVFR0_SQRT_MASK 0x00f00000 123 #define ARM_MVFR0_DIVIDE_MASK 0x000f0000 124 #define ARM_MVFR0_EXCEPT_MASK 0x0000f000 125 #define ARM_MVFR0_DFLOAT_MASK 0x00000f00 126 #define ARM_MVFR0_SFLOAT_MASK 0x000000f0 127 #define ARM_MVFR0_ASIMD_MASK 0x0000000f 128 #define ARM_MVFR1_ASIMD_FMACS_MASK 0xf0000000 129 #define ARM_MVFR1_VFP_HPFP_MASK 0x0f000000 130 #define ARM_MVFR1_ASIMD_HPFP_MASK 0x00f00000 131 #define ARM_MVFR1_ASIMD_SPFP_MASK 0x000f0000 132 #define ARM_MVFR1_ASIMD_INT_MASK 0x0000f000 133 #define ARM_MVFR1_ASIMD_LDST_MASK 0x00000f00 134 #define ARM_MVFR1_D_NAN_MASK 0x000000f0 135 #define ARM_MVFR1_FTZ_MASK 0x0000000f 136 137 /* ARM3-specific coprocessor 15 registers */ 138 #define ARM3_CP15_FLUSH 1 139 #define ARM3_CP15_CONTROL 2 140 #define ARM3_CP15_CACHEABLE 3 141 #define ARM3_CP15_UPDATEABLE 4 142 #define ARM3_CP15_DISRUPTIVE 5 143 144 /* ARM3 Control register bits */ 145 #define ARM3_CTL_CACHE_ON 0x00000001 146 #define ARM3_CTL_SHARED 0x00000002 147 #define ARM3_CTL_MONITOR 0x00000004 148 149 /* 150 * Post-ARM3 CP15 registers: 151 * 152 * 1 Control register 153 * 154 * 2 Translation Table Base 155 * 156 * 3 Domain Access Control 157 * 158 * 4 Reserved 159 * 160 * 5 Fault Status 161 * 162 * 6 Fault Address 163 * 164 * 7 Cache/write-buffer Control 165 * 166 * 8 TLB Control 167 * 168 * 9 Cache Lockdown 169 * 170 * 10 TLB Lockdown 171 * 172 * 11 Reserved 173 * 174 * 12 Reserved 175 * 176 * 13 Process ID (for FCSE) 177 * 178 * 14 Reserved 179 * 180 * 15 Implementation Dependent 181 */ 182 183 /* Some of the definitions below need cleaning up for V3/V4 architectures */ 184 185 /* CPU control register (CP15 register 1) */ 186 #define CPU_CONTROL_MMU_ENABLE 0x00000001 /* M: MMU/Protection unit enable */ 187 #define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */ 188 #define CPU_CONTROL_DC_ENABLE 0x00000004 /* C: IDC/DC enable */ 189 #define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */ 190 #define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */ 191 #define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */ 192 #define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */ 193 #define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */ 194 #define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */ 195 #define CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */ 196 #define CPU_CONTROL_CPCLK 0x00000400 /* F: Implementation defined */ 197 #define CPU_CONTROL_SWP_ENABLE 0x00000400 /* SW: SWP{B} perform normally. */ 198 #define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */ 199 #define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */ 200 #define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */ 201 #define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */ 202 #define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */ 203 #define CPU_CONTROL_HA_ENABLE 0x00020000 /* HA: Hardware Access flag enable */ 204 #define CPU_CONTROL_WXN_ENABLE 0x00080000 /* WXN: Write Execute Never */ 205 #define CPU_CONTROL_UWXN_ENABLE 0x00100000 /* UWXN: User Write eXecute Never */ 206 #define CPU_CONTROL_FI_ENABLE 0x00200000 /* FI: Low interrupt latency */ 207 #define CPU_CONTROL_UNAL_ENABLE 0x00400000 /* U: unaligned data access */ 208 #define CPU_CONTROL_XP_ENABLE 0x00800000 /* XP: extended page table */ 209 #define CPU_CONTROL_V_ENABLE 0x01000000 /* VE: Interrupt vectors enable */ 210 #define CPU_CONTROL_EX_BEND 0x02000000 /* EE: exception endianness */ 211 #define CPU_CONTROL_NMFI 0x08000000 /* NMFI: Non maskable FIQ */ 212 #define CPU_CONTROL_TR_ENABLE 0x10000000 /* TRE: */ 213 #define CPU_CONTROL_AF_ENABLE 0x20000000 /* AFE: Access flag enable */ 214 #define CPU_CONTROL_TE_ENABLE 0x40000000 /* TE: Thumb Exception enable */ 215 216 #define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE 217 218 /* ARMv6/ARMv7 Co-Processor Access Control Register (CP15, 0, c1, c0, 2) */ 219 #define CPACR_V7_ASEDIS 0x80000000 /* Disable Advanced SIMD Ext. */ 220 #define CPACR_V7_D32DIS 0x40000000 /* Disable VFP regs 15-31 */ 221 #define CPACR_CPn(n) (3 << (2*n)) 222 #define CPACR_NOACCESS 0 /* reset value */ 223 #define CPACR_PRIVED 1 /* Privileged mode access */ 224 #define CPACR_RESERVED 2 225 #define CPACR_ALL 3 /* Privileged and User mode access */ 226 227 /* ARMv6/ARMv7 Non-Secure Access Control Register (CP15, 0, c1, c1, 2) */ 228 #define NSACR_SMP 0x00040000 /* ACTRL.SMP is writeable (!A8) */ 229 #define NSACR_L2ERR 0x00020000 /* L2ECTRL is writeable (!A8) */ 230 #define NSACR_ASEDIS 0x00008000 /* Deny Advanced SIMD Ext. */ 231 #define NSACR_D32DIS 0x00004000 /* Deny VFP regs 15-31 */ 232 #define NSACR_CPn(n) (1 << (n)) /* NonSecure access allowed */ 233 234 /* ARM11x6 Auxiliary Control Register (CP15 register 1, opcode2 1) */ 235 #define ARM11X6_AUXCTL_RS 0x00000001 /* return stack */ 236 #define ARM11X6_AUXCTL_DB 0x00000002 /* dynamic branch prediction */ 237 #define ARM11X6_AUXCTL_SB 0x00000004 /* static branch prediction */ 238 #define ARM11X6_AUXCTL_TR 0x00000008 /* MicroTLB replacement strat. */ 239 #define ARM11X6_AUXCTL_EX 0x00000010 /* exclusive L1/L2 cache */ 240 #define ARM11X6_AUXCTL_RA 0x00000020 /* clean entire cache disable */ 241 #define ARM11X6_AUXCTL_RV 0x00000040 /* block transfer cache disable */ 242 #define ARM11X6_AUXCTL_CZ 0x00000080 /* restrict cache size */ 243 244 /* ARM1136 Auxiliary Control Register (CP15 register 1, opcode2 1) */ 245 #define ARM1136_AUXCTL_PFI 0x80000000 /* PFI: partial FI mode. */ 246 /* This is an undocumented flag 247 * used to work around a cache bug 248 * in r0 steppings. See errata 249 * 364296. 250 */ 251 /* ARM1176 Auxiliary Control Register (CP15 register 1, opcode2 1) */ 252 #define ARM1176_AUXCTL_PHD 0x10000000 /* inst. prefetch halting disable */ 253 #define ARM1176_AUXCTL_BFD 0x20000000 /* branch folding disable */ 254 #define ARM1176_AUXCTL_FSD 0x40000000 /* force speculative ops disable */ 255 #define ARM1176_AUXCTL_FIO 0x80000000 /* low intr latency override */ 256 257 /* XScale Auxiliary Control Register (CP15 register 1, opcode2 1) */ 258 #define XSCALE_AUXCTL_K 0x00000001 /* dis. write buffer coalescing */ 259 #define XSCALE_AUXCTL_P 0x00000002 /* ECC protect page table access */ 260 #define XSCALE_AUXCTL_MD_WB_RA 0x00000000 /* mini-D$ wb, read-allocate */ 261 #define XSCALE_AUXCTL_MD_WB_RWA 0x00000010 /* mini-D$ wb, read/write-allocate */ 262 #define XSCALE_AUXCTL_MD_WT 0x00000020 /* mini-D$ wt, read-allocate */ 263 #define XSCALE_AUXCTL_MD_MASK 0x00000030 264 265 /* ARM11 MPCore Auxiliary Control Register (CP15 register 1, opcode2 1) */ 266 #define MPCORE_AUXCTL_RS 0x00000001 /* return stack */ 267 #define MPCORE_AUXCTL_DB 0x00000002 /* dynamic branch prediction */ 268 #define MPCORE_AUXCTL_SB 0x00000004 /* static branch prediction */ 269 #define MPCORE_AUXCTL_F 0x00000008 /* instruction folding enable */ 270 #define MPCORE_AUXCTL_EX 0x00000010 /* exclusive L1/L2 cache */ 271 #define MPCORE_AUXCTL_SA 0x00000020 /* SMP/AMP */ 272 273 /* Marvell PJ4B Auxiliary Control Register (CP15.0.R1.c0.1) */ 274 #define PJ4B_AUXCTL_FW __BIT(0) /* Cache and TLB updates broadcast */ 275 #define PJ4B_AUXCTL_SMPNAMP __BIT(6) /* 0 = AMP, 1 = SMP */ 276 #define PJ4B_AUXCTL_L1PARITY __BIT(9) /* L1 parity checking */ 277 278 /* Marvell PJ4B Auxialiary Function Modes Control 0 (CP15.1.R15.c2.0) */ 279 #define PJ4B_AUXFMC0_L2EN __BIT(0) /* Tightly-Coupled L2 cache enable */ 280 #define PJ4B_AUXFMC0_SMPNAMP __BIT(1) /* 0 = AMP, 1 = SMP */ 281 #define PJ4B_AUXFMC0_L1PARITY __BIT(2) /* alias of PJ4B_AUXCTL_L1PARITY */ 282 #define PJ4B_AUXFMC0_DCSLFD __BIT(2) /* Disable DC Speculative linefill */ 283 #define PJ4B_AUXFMC0_FW __BIT(8) /* alias of PJ4B_AUXCTL_FW*/ 284 285 /* Cortex-A5 Auxiliary Control Register (CP15 register 1, opcode 1) */ 286 #define CORTEXA5_ACTLR_FW __BIT(0) 287 #define CORTEXA5_ACTLR_SMP __BIT(6) /* Inner Cache Shared is cacheable */ 288 #define CORTEXA5_ACTLR_EXCL __BIT(7) /* Exclusive L1/L2 cache control */ 289 290 /* Cortex-A7 Auxiliary Control Register (CP15 register 1, opcode 1) */ 291 #define CORTEXA7_ACTLR_L1ALIAS __BIT(0) /* Enables L1 cache alias checks */ 292 #define CORTEXA7_ACTLR_L2EN __BIT(1) /* Enables L2 cache */ 293 #define CORTEXA7_ACTLR_SMP __BIT(6) /* SMP */ 294 295 /* Cortex-A8 Auxiliary Control Register (CP15 register 1, opcode 1) */ 296 #define CORTEXA8_ACTLR_L1ALIAS __BIT(0) /* Enables L1 cache alias checks */ 297 #define CORTEXA8_ACTLR_L2EN __BIT(1) /* Enables L2 cache */ 298 299 /* Cortex-A9 Auxiliary Control Register (CP15 register 1, opcode 1) */ 300 #define CORTEXA9_AUXCTL_FW 0x00000001 /* Cache and TLB updates broadcast */ 301 #define CORTEXA9_AUXCTL_L2PE 0x00000002 /* Prefetch hint enable */ 302 #define CORTEXA9_AUXCTL_L1PE 0x00000004 /* Data prefetch hint enable */ 303 #define CORTEXA9_AUXCTL_WR_ZERO 0x00000008 /* Ena. write full line of 0s mode */ 304 #define CORTEXA9_AUXCTL_SMP 0x00000040 /* Coherency is active */ 305 #define CORTEXA9_AUXCTL_EXCL 0x00000080 /* Exclusive cache bit */ 306 #define CORTEXA9_AUXCTL_ONEWAY 0x00000100 /* Allocate in on cache way only */ 307 #define CORTEXA9_AUXCTL_PARITY 0x00000200 /* Support parity checking */ 308 309 /* Cortex-A15 Auxiliary Control Register (CP15 register 1, opcode 1) */ 310 #define CORTEXA15_ACTLR_BTB __BIT(0) /* Cache and TLB updates broadcast */ 311 #define CORTEXA15_ACTLR_SMP __BIT(6) /* SMP */ 312 #define CORTEXA15_ACTLR_IOBEU __BIT(15) /* In order issue in Branch Exec Unit */ 313 #define CORTEXA15_ACTLR_SDEH __BIT(31) /* snoop-delayed exclusive handling */ 314 315 /* Cortex-A17 Auxiliary Control Register (CP15 register 1, opcode 1) */ 316 #define CORTEXA17_ACTLR_SMP __BIT(6) /* SMP */ 317 #define CORTEXA17_ACTLR_ASSE __BIT(3) /* ACE STREX Signaling Enable */ 318 #define CORTEXA17_ACTLR_L2PF __BIT(2) /* Enable L2 prefetch */ 319 #define CORTEXA17_ACTLR_L1PF __BIT(1) /* Enable L1 prefetch */ 320 321 /* Marvell Feroceon Extra Features Register (CP15 register 1, opcode2 0) */ 322 #define FC_DCACHE_REPL_LOCK 0x80000000 /* Replace DCache Lock */ 323 #define FC_DCACHE_STREAM_EN 0x20000000 /* DCache Streaming Switch */ 324 #define FC_WR_ALLOC_EN 0x10000000 /* Enable Write Allocate */ 325 #define FC_L2_PREF_DIS 0x01000000 /* L2 Cache Prefetch Disable */ 326 #define FC_L2_INV_EVICT_LINE 0x00800000 /* L2 Invalidates Uncorrectable Error Line Eviction */ 327 #define FC_L2CACHE_EN 0x00400000 /* L2 enable */ 328 #define FC_ICACHE_REPL_LOCK 0x00080000 /* Replace ICache Lock */ 329 #define FC_GLOB_HIST_REG_EN 0x00040000 /* Branch Global History Register Enable */ 330 #define FC_BRANCH_TARG_BUF_DIS 0x00020000 /* Branch Target Buffer Disable */ 331 #define FC_L1_PAR_ERR_EN 0x00010000 /* L1 Parity Error Enable */ 332 333 /* Cache type register definitions 0 */ 334 #define CPU_CT_FORMAT(x) (((x) >> 29) & 0x7) /* reg format */ 335 #define CPU_CT_ISIZE(x) ((x) & 0xfff) /* I$ info */ 336 #define CPU_CT_DSIZE(x) (((x) >> 12) & 0xfff) /* D$ info */ 337 #define CPU_CT_S (1U << 24) /* split cache */ 338 #define CPU_CT_CTYPE(x) (((x) >> 25) & 0xf) /* cache type */ 339 340 #define CPU_CT_CTYPE_WT 0 /* write-through */ 341 #define CPU_CT_CTYPE_WB1 1 /* write-back, clean w/ read */ 342 #define CPU_CT_CTYPE_WB2 2 /* w/b, clean w/ cp15,7 */ 343 #define CPU_CT_CTYPE_WB6 6 /* w/b, cp15,7, lockdown fmt A */ 344 #define CPU_CT_CTYPE_WB7 7 /* w/b, cp15,7, lockdown fmt B */ 345 #define CPU_CT_CTYPE_WB14 14 /* w/b, cp15,7, lockdown fmt C */ 346 347 #define CPU_CT_xSIZE_LEN(x) ((x) & 0x3) /* line size */ 348 #define CPU_CT_xSIZE_M (1U << 2) /* multiplier */ 349 #define CPU_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x7) /* associativity */ 350 #define CPU_CT_xSIZE_SIZE(x) (((x) >> 6) & 0x7) /* size */ 351 #define CPU_CT_xSIZE_P (1U << 11) /* need to page-color */ 352 353 /* format 4 definitions */ 354 #define CPU_CT4_ILINE(x) ((x) & 0xf) /* I$ line size */ 355 #define CPU_CT4_DLINE(x) (((x) >> 16) & 0xf) /* D$ line size */ 356 #define CPU_CT4_L1IPOLICY(x) (((x) >> 14) & 0x3) /* I$ policy */ 357 #define CPU_CT4_L1_AIVIVT 1 /* ASID tagged VIVT */ 358 #define CPU_CT4_L1_VIPT 2 /* VIPT */ 359 #define CPU_CT4_L1_PIPT 3 /* PIPT */ 360 #define CPU_CT4_ERG(x) (((x) >> 20) & 0xf) /* Cache WriteBack Granule */ 361 #define CPU_CT4_CWG(x) (((x) >> 24) & 0xf) /* Exclusive Resv. Granule */ 362 363 /* Cache size identifaction register definitions 1, Rd, c0, c0, 0 */ 364 #define CPU_CSID_CTYPE_WT 0x80000000 /* write-through avail */ 365 #define CPU_CSID_CTYPE_WB 0x40000000 /* write-back avail */ 366 #define CPU_CSID_CTYPE_RA 0x20000000 /* read-allocation avail */ 367 #define CPU_CSID_CTYPE_WA 0x10000000 /* write-allocation avail */ 368 #define CPU_CSID_NUMSETS(x) (((x) >> 13) & 0x7fff) 369 #define CPU_CSID_ASSOC(x) (((x) >> 3) & 0x1ff) 370 #define CPU_CSID_LEN(x) ((x) & 0x07) 371 372 /* Cache size selection register definitions 2, Rd, c0, c0, 0 */ 373 #define CPU_CSSR_L2 0x00000002 374 #define CPU_CSSR_L1 0x00000000 375 #define CPU_CSSR_InD 0x00000001 376 377 /* Fault status register definitions */ 378 379 #define FAULT_TYPE_MASK 0x0f 380 #define FAULT_USER 0x10 381 382 #define FAULT_WRTBUF_0 0x00 /* Vector Exception */ 383 #define FAULT_WRTBUF_1 0x02 /* Terminal Exception */ 384 #define FAULT_BUSERR_0 0x04 /* External Abort on Linefetch -- Section */ 385 #define FAULT_BUSERR_1 0x06 /* External Abort on Linefetch -- Page */ 386 #define FAULT_BUSERR_2 0x08 /* External Abort on Non-linefetch -- Section */ 387 #define FAULT_BUSERR_3 0x0a /* External Abort on Non-linefetch -- Page */ 388 #define FAULT_BUSTRNL1 0x0c /* External abort on Translation -- Level 1 */ 389 #define FAULT_BUSTRNL2 0x0e /* External abort on Translation -- Level 2 */ 390 #define FAULT_ALIGN_0 0x01 /* Alignment */ 391 #define FAULT_ALIGN_1 0x03 /* Alignment */ 392 #define FAULT_TRANS_S 0x05 /* Translation -- Section */ 393 #define FAULT_TRANS_P 0x07 /* Translation -- Page */ 394 #define FAULT_DOMAIN_S 0x09 /* Domain -- Section */ 395 #define FAULT_DOMAIN_P 0x0b /* Domain -- Page */ 396 #define FAULT_PERM_S 0x0d /* Permission -- Section */ 397 #define FAULT_PERM_P 0x0f /* Permission -- Page */ 398 399 #define FAULT_LPAE 0x0200 /* (SW) used long descriptors */ 400 #define FAULT_IMPRECISE 0x0400 /* Imprecise exception (XSCALE) */ 401 #define FAULT_WRITE 0x0800 /* fault was due to write (ARMv6+) */ 402 #define FAULT_EXT 0x1000 /* fault was due to external abort (ARMv6+) */ 403 #define FAULT_CM 0x2000 /* fault was due to cache maintenance (ARMv7+) */ 404 405 /* 406 * Address of the vector page, low and high versions. 407 */ 408 #define ARM_VECTORS_LOW 0x00000000U 409 #define ARM_VECTORS_HIGH 0xffff0000U 410 411 /* 412 * ARM Instructions 413 * 414 * 3 3 2 2 2 415 * 1 0 9 8 7 0 416 * +-------+-------------------------------------------------------+ 417 * | cond | instruction dependent | 418 * |c c c c| | 419 * +-------+-------------------------------------------------------+ 420 */ 421 422 #define INSN_SIZE 4 /* Always 4 bytes */ 423 #define INSN_COND_MASK 0xf0000000 /* Condition mask */ 424 #define INSN_COND_EQ 0 /* Z == 1 */ 425 #define INSN_COND_NE 1 /* Z == 0 */ 426 #define INSN_COND_CS 2 /* C == 1 */ 427 #define INSN_COND_CC 3 /* C == 0 */ 428 #define INSN_COND_MI 4 /* N == 1 */ 429 #define INSN_COND_PL 5 /* N == 0 */ 430 #define INSN_COND_VS 6 /* V == 1 */ 431 #define INSN_COND_VC 7 /* V == 0 */ 432 #define INSN_COND_HI 8 /* C == 1 && Z == 0 */ 433 #define INSN_COND_LS 9 /* C == 0 || Z == 1 */ 434 #define INSN_COND_GE 10 /* N == V */ 435 #define INSN_COND_LT 11 /* N != V */ 436 #define INSN_COND_GT 12 /* Z == 0 && N == V */ 437 #define INSN_COND_LE 13 /* Z == 1 || N != V */ 438 #define INSN_COND_AL 14 /* Always condition */ 439 440 #define THUMB_INSN_SIZE 2 /* Some are 4 bytes. */ 441 442 /* 443 * Defines and such for arm11 Performance Monitor Counters (p15, c15, c12, 0) 444 */ 445 #define ARM11_PMCCTL_E __BIT(0) /* enable all three counters */ 446 #define ARM11_PMCCTL_P __BIT(1) /* reset both Count Registers to zero */ 447 #define ARM11_PMCCTL_C __BIT(2) /* reset the Cycle Counter Register to zero */ 448 #define ARM11_PMCCTL_D __BIT(3) /* cycle count divide by 64 */ 449 #define ARM11_PMCCTL_EC0 __BIT(4) /* Enable Counter Register 0 interrupt */ 450 #define ARM11_PMCCTL_EC1 __BIT(5) /* Enable Counter Register 1 interrupt */ 451 #define ARM11_PMCCTL_ECC __BIT(6) /* Enable Cycle Counter interrupt */ 452 #define ARM11_PMCCTL_SBZa __BIT(7) /* UNP/SBZ */ 453 #define ARM11_PMCCTL_CR0 __BIT(8) /* Count Register 0 overflow flag */ 454 #define ARM11_PMCCTL_CR1 __BIT(9) /* Count Register 1 overflow flag */ 455 #define ARM11_PMCCTL_CCR __BIT(10) /* Cycle Count Register overflow flag */ 456 #define ARM11_PMCCTL_X __BIT(11) /* Enable Export of the events to the event bus */ 457 #define ARM11_PMCCTL_EVT1 __BITS(19,12) /* source of events for Count Register 1 */ 458 #define ARM11_PMCCTL_EVT0 __BITS(27,20) /* source of events for Count Register 0 */ 459 #define ARM11_PMCCTL_SBZb __BITS(31,28) /* UNP/SBZ */ 460 #define ARM11_PMCCTL_SBZ \ 461 (ARM11_PMCCTL_SBZa | ARM11_PMCCTL_SBZb) 462 463 #define ARM11_PMCEVT_ICACHE_MISS 0 /* Instruction Cache Miss */ 464 #define ARM11_PMCEVT_ISTREAM_STALL 1 /* Instruction Stream Stall */ 465 #define ARM11_PMCEVT_IUTLB_MISS 2 /* Instruction uTLB Miss */ 466 #define ARM11_PMCEVT_DUTLB_MISS 3 /* Data uTLB Miss */ 467 #define ARM11_PMCEVT_BRANCH 4 /* Branch Inst. Executed */ 468 #define ARM11_PMCEVT_BRANCH_MISS 6 /* Branch mispredicted */ 469 #define ARM11_PMCEVT_INST_EXEC 7 /* Instruction Executed */ 470 #define ARM11_PMCEVT_DCACHE_ACCESS0 9 /* Data Cache Access */ 471 #define ARM11_PMCEVT_DCACHE_ACCESS1 10 /* Data Cache Access */ 472 #define ARM11_PMCEVT_DCACHE_MISS 11 /* Data Cache Miss */ 473 #define ARM11_PMCEVT_DCACHE_WRITEBACK 12 /* Data Cache Writeback */ 474 #define ARM11_PMCEVT_PC_CHANGE 13 /* Software PC change */ 475 #define ARM11_PMCEVT_TLB_MISS 15 /* Main TLB Miss */ 476 #define ARM11_PMCEVT_DATA_ACCESS 16 /* non-cached data access */ 477 #define ARM11_PMCEVT_LSU_STALL 17 /* Load/Store Unit stall */ 478 #define ARM11_PMCEVT_WBUF_DRAIN 18 /* Write buffer drained */ 479 #define ARM11_PMCEVT_ETMEXTOUT0 32 /* ETMEXTOUT[0] asserted */ 480 #define ARM11_PMCEVT_ETMEXTOUT1 33 /* ETMEXTOUT[1] asserted */ 481 #define ARM11_PMCEVT_ETMEXTOUT 34 /* ETMEXTOUT[0 & 1] */ 482 #define ARM11_PMCEVT_CALL_EXEC 35 /* Procedure call executed */ 483 #define ARM11_PMCEVT_RETURN_EXEC 36 /* Return executed */ 484 #define ARM11_PMCEVT_RETURN_HIT 37 /* return address predicted */ 485 #define ARM11_PMCEVT_RETURN_MISS 38 /* return addr. mispredicted */ 486 #define ARM11_PMCEVT_CYCLE 255 /* Increment each cycle */ 487 488 /* ARMv7 PMCR, Performance Monitor Control Register */ 489 #define PMCR_N __BITS(15,11) 490 #define PMCR_D __BIT(3) 491 #define PMCR_E __BIT(0) 492 493 /* ARMv7 INTEN{SET,CLR}, Performance Monitors Interrupt Enable Set register */ 494 #define PMINTEN_C __BIT(31) 495 #define PMINTEN_P __BITS(30,0) 496 #define PMCNTEN_C __BIT(31) 497 #define PMCNTEN_P __BITS(30,0) 498 499 /* ARMv7 PMOVSR, Performance Monitors Overflow Flag Status Register */ 500 #define PMOVS_C __BIT(31) 501 #define PMOVS_P __BITS(30,0) 502 503 /* ARMv7 PMXEVTYPER, Performance Monitors Event Type Select Register */ 504 #define PMEVTYPER_P __BIT(31) 505 #define PMEVTYPER_U __BIT(30) 506 #define PMEVTYPER_EVTCOUNT __BITS(7,0) 507 508 /* Defines for ARM CORTEX performance counters */ 509 #define CORTEX_CNTENS_C __BIT(31) /* Enables the cycle counter */ 510 #define CORTEX_CNTENC_C __BIT(31) /* Disables the cycle counter */ 511 #define CORTEX_CNTOFL_C __BIT(31) /* Cycle counter overflow flag */ 512 513 /* Defines for ARM Cortex A7/A15 L2CTRL */ 514 #define L2CTRL_NUMCPU __BITS(25,24) // numcpus - 1 515 #define L2CTRL_ICPRES __BIT(23) // Interrupt Controller is present 516 517 /* Translation Table Base Register */ 518 #define TTBR_C __BIT(0) /* without MPE */ 519 #define TTBR_S __BIT(1) 520 #define TTBR_IMP __BIT(2) 521 #define TTBR_RGN_MASK __BITS(4,3) 522 #define TTBR_RGN_NC __SHIFTIN(0, TTBR_RGN_MASK) 523 #define TTBR_RGN_WBWA __SHIFTIN(1, TTBR_RGN_MASK) 524 #define TTBR_RGN_WT __SHIFTIN(2, TTBR_RGN_MASK) 525 #define TTBR_RGN_WBNWA __SHIFTIN(3, TTBR_RGN_MASK) 526 #define TTBR_NOS __BIT(5) 527 #define TTBR_IRGN_MASK (__BIT(6) | __BIT(0)) 528 #define TTBR_IRGN_NC 0 529 #define TTBR_IRGN_WBWA __BIT(6) 530 #define TTBR_IRGN_WT __BIT(0) 531 #define TTBR_IRGN_WBNWA (__BIT(0) | __BIT(6)) 532 533 /* Translate Table Base Control Register */ 534 #define TTBCR_S_EAE __BIT(31) // Extended Address Extension 535 #define TTBCR_S_PD1 __BIT(5) // Don't use TTBR1 536 #define TTBCR_S_PD0 __BIT(4) // Don't use TTBR0 537 #define TTBCR_S_N __BITS(2,0) // Width of base address in TTB0 538 539 #define TTBCR_L_EAE __BIT(31) // Extended Address Extension 540 #define TTBCR_L_SH1 __BITS(29,28) // TTBR1 Shareability 541 #define TTBCR_L_ORGN1 __BITS(27,26) // TTBR1 Outer cacheability 542 #define TTBCR_L_IRGN1 __BITS(25,24) // TTBR1 inner cacheability 543 #define TTBCR_L_EPD1 __BIT(23) // Don't use TTBR1 544 #define TTBCR_L_A1 __BIT(22) // ASID is in TTBR1 545 #define TTBCR_L_T1SZ __BITS(18,16) // TTBR1 size offset 546 #define TTBCR_L_SH0 __BITS(13,12) // TTBR0 Shareability 547 #define TTBCR_L_ORGN0 __BITS(11,10) // TTBR0 Outer cacheability 548 #define TTBCR_L_IRGN0 __BITS(9,8) // TTBR0 inner cacheability 549 #define TTBCR_L_EPD0 __BIT(7) // Don't use TTBR0 550 #define TTBCR_L_T0SZ __BITS(2,0) // TTBR0 size offset 551 552 #define NMRR_ORn(n) __BITS(17+2*(n),16+2*(n)) // Outer Cacheable mappings 553 #define NMRR_IRn(n) __BITS(1+2*(n),0+2*(n)) // Inner Cacheable mappings 554 #define NMRR_NC 0 // non-cacheable 555 #define NMRR_WBWA 1 // write-back write-allocate 556 #define NMRR_WT 2 // write-through 557 #define NMRR_WB 3 // write-back 558 #define PRRR_NOSn(n) __BITS(24+(n)) // Memory region is Inner Shareable only 559 #define PRRR_NS1 __BIT(19) // Normal Shareable S=1 is Shareable 560 #define PRRR_NS0 __BIT(18) // Normal Shareable S=0 is Shareable 561 #define PRRR_DS1 __BIT(17) // Device Shareable S=1 is Shareable 562 #define PRRR_DS0 __BIT(16) // Device Shareable S=0 is Shareable 563 #define PRRR_TRn(n) __BITS(1+2*(n),0+2*(n)) 564 #define PRRR_TR_STRONG 0 // Strongly Ordered 565 #define PRRR_TR_DEVICE 1 // Device 566 #define PRRR_TR_NORMAL 2 // Normal Memory 567 // 3 is reserved 568 569 /* ARMv7 MPIDR, Multiprocessor Affinity Register generic format */ 570 #define MPIDR_MP __BIT(31) /* 1 = Have MP Extension */ 571 #define MPIDR_U __BIT(30) /* 1 = Uni-Processor System */ 572 #define MPIDR_MT __BIT(24) /* 1 = SMT(AFF0 is logical) */ 573 #define MPIDR_AFF2 __BITS(23,16) /* Affinity Level 2 */ 574 #define MPIDR_AFF1 __BITS(15,8) /* Affinity Level 1 */ 575 #define MPIDR_AFF0 __BITS(7,0) /* Affinity Level 0 */ 576 577 /* MPIDR implementation of ARM Cortex A9: SMT and AFF2 is not used */ 578 #define CORTEXA9_MPIDR_MP MPIDR_MP 579 #define CORTEXA9_MPIDR_U MPIDR_U 580 #define CORTEXA9_MPIDR_CLID __BITS(11,8) /* AFF1 = cluster id */ 581 #define CORTEXA9_MPIDR_CPUID __BITS(0,1) /* AFF0 = physical core id */ 582 583 /* MPIDR implementation of Marvell PJ4B-MP: AFF2 is not used */ 584 #define PJ4B_MPIDR_MP MPIDR_MP 585 #define PJ4B_MPIDR_U MPIDR_U 586 #define PJ4B_MPIDR_MT MPIDR_MT /* 1 = SMT(AFF0 is logical) */ 587 #define PJ4B_MPIDR_CLID __BITS(11,8) /* AFF1 = cluster id */ 588 #define PJ4B_MPIDR_CPUID __BITS(0,3) /* AFF0 = core id */ 589 590 /* Defines for ARM Generic Timer */ 591 #define CNTCTL_ISTATUS __BIT(2) // Interrupt is pending 592 #define CNTCTL_IMASK __BIT(1) // Mask Interrupt 593 #define CNTCTL_ENABLE __BIT(0) // Timer Enabled 594 595 #define CNTKCTL_PL0PTEN __BIT(9) /* PL0 Physical Timer Enable */ 596 #define CNTKCTL_PL0VTEN __BIT(8) /* PL0 Virtual Timer Enable */ 597 #define CNTKCTL_EVNTI __BITS(7,4) /* CNTVCT Event Bit Select */ 598 #define CNTKCTL_EVNTDIR __BIT(3) /* CNTVCT Event Dir (1->0) */ 599 #define CNTKCTL_EVNTEN __BIT(2) /* CNTVCT Event Enable */ 600 #define CNTKCTL_PL0VCTEN __BIT(1) /* PL0 Virtual Counter Enable */ 601 #define CNTKCTL_PL0PCTEN __BIT(0) /* PL0 Physical Counter Enable */ 602 603 /* CNCHCTL, Timer PL2 Control register, Virtualization Extensions */ 604 #define CNTHCTL_EVNTI __BITS(7,4) 605 #define CNTHCTL_EVNTDIR __BIT(3) 606 #define CNTHCTL_EVNTEN __BIT(2) 607 #define CNTHCTL_PL1PCEN __BIT(1) 608 #define CNTHCTL_PL1PCTEN __BIT(0) 609 610 #define ARM_A5_TLBDATA_DOM __BITS(62,59) 611 #define ARM_A5_TLBDATA_AP __BITS(58,56) 612 #define ARM_A5_TLBDATA_NS_WALK __BIT(55) 613 #define ARM_A5_TLBDATA_NS_PAGE __BIT(54) 614 #define ARM_A5_TLBDATA_XN __BIT(53) 615 #define ARM_A5_TLBDATA_TEX __BITS(52,50) 616 #define ARM_A5_TLBDATA_B __BIT(49) 617 #define ARM_A5_TLBDATA_C __BIT(48) 618 #define ARM_A5_TLBDATA_S __BIT(47) 619 #define ARM_A5_TLBDATA_ASID __BITS(46,39) 620 #define ARM_A5_TLBDATA_SIZE __BITS(38,37) 621 #define ARM_A5_TLBDATA_SIZE_4KB 0 622 #define ARM_A5_TLBDATA_SIZE_16KB 1 623 #define ARM_A5_TLBDATA_SIZE_1MB 2 624 #define ARM_A5_TLBDATA_SIZE_16MB 3 625 #define ARM_A5_TLBDATA_VA __BITS(36,22) 626 #define ARM_A5_TLBDATA_PA __BITS(21,2) 627 #define ARM_A5_TLBDATA_nG __BIT(1) 628 #define ARM_A5_TLBDATA_VALID __BIT(0) 629 630 #define ARM_A7_TLBDATA2_S2_LEVEL __BITS(85-64,84-64) 631 #define ARM_A7_TLBDATA2_S1_SIZE __BITS(83-64,82-64) 632 #define ARM_A7_TLBDATA2_S1_SIZE_4KB 0 633 #define ARM_A7_TLBDATA2_S1_SIZE_64KB 1 634 #define ARM_A7_TLBDATA2_S1_SIZE_1MB 2 635 #define ARM_A7_TLBDATA2_S1_SIZE_16MB 3 636 #define ARM_A7_TLBDATA2_DOM __BITS(81-64,78-64) 637 #define ARM_A7_TLBDATA2_IS __BITS(77-64,76-64) 638 #define ARM_A7_TLBDATA2_IS_NC 0 639 #define ARM_A7_TLBDATA2_IS_WB_WA 1 640 #define ARM_A7_TLBDATA2_IS_WT 2 641 #define ARM_A7_TLBDATA2_IS_DSO 3 642 #define ARM_A7_TLBDATA2_S2OVR __BIT(75-64) 643 #define ARM_A7_TLBDATA2_SDO_MT __BITS(74-64,72-64) 644 #define ARM_A7_TLBDATA2_SDO_MT_D 2 645 #define ARM_A7_TLBDATA2_SDO_MT_SO 6 646 #define ARM_A7_TLBDATA2_OS __BITS(75-64,74-64) 647 #define ARM_A7_TLBDATA2_OS_NC 0 648 #define ARM_A7_TLBDATA2_OS_WB_WA 1 649 #define ARM_A7_TLBDATA2_OS_WT 2 650 #define ARM_A7_TLBDATA2_OS_WB 3 651 #define ARM_A7_TLBDATA2_SH __BITS(73-64,72-64) 652 #define ARM_A7_TLBDATA2_SH_NONE 0 653 #define ARM_A7_TLBDATA2_SH_UNUSED 1 654 #define ARM_A7_TLBDATA2_SH_OS 2 655 #define ARM_A7_TLBDATA2_SH_IS 3 656 #define ARM_A7_TLBDATA2_XN2 __BIT(71-64) 657 #define ARM_A7_TLBDATA2_XN1 __BIT(70-64) 658 #define ARM_A7_TLBDATA2_PXN __BIT(69-64) 659 660 #define ARM_A7_TLBDATA12_PA __BITS(68-32,41-32) 661 662 #define ARM_A7_TLBDATA1_NS __BIT(40-32) 663 #define ARM_A7_TLBDATA1_HAP __BITS(39-32,38-32) 664 #define ARM_A7_TLBDATA1_AP __BITS(37-32,35-32) 665 #define ARM_A7_TLBDATA1_nG __BIT(34-32) 666 667 #define ARM_A7_TLBDATA01_ASID __BITS(33,26) 668 669 #define ARM_A7_TLBDATA0_VMID __BITS(25,18) 670 #define ARM_A7_TLBDATA0_VA __BITS(17,5) 671 #define ARM_A7_TLBDATA0_NS_WALK __BIT(4) 672 #define ARM_A7_TLBDATA0_SIZE __BITS(3,1) 673 #define ARM_A7_TLBDATA0_SIZE_V7_4KB 0 674 #define ARM_A7_TLBDATA0_SIZE_LPAE_4KB 1 675 #define ARM_A7_TLBDATA0_SIZE_V7_64KB 2 676 #define ARM_A7_TLBDATA0_SIZE_LPAE_64KB 3 677 #define ARM_A7_TLBDATA0_SIZE_V7_1MB 4 678 #define ARM_A7_TLBDATA0_SIZE_LPAE_2MB 5 679 #define ARM_A7_TLBDATA0_SIZE_V7_16MB 6 680 #define ARM_A7_TLBDATA0_SIZE_LPAE_1GB 7 681 682 #define ARM_TLBDATA_VALID __BIT(0) 683 684 #define ARM_TLBDATAOP_WAY __BIT(31) 685 #define ARM_A5_TLBDATAOP_INDEX __BITS(5,0) 686 #define ARM_A7_TLBDATAOP_INDEX __BITS(6,0) 687 688 #if !defined(__ASSEMBLER__) && defined(_KERNEL) 689 static inline bool 690 arm_cond_ok_p(uint32_t insn, uint32_t psr) 691 { 692 const uint32_t __cond = __SHIFTOUT(insn, INSN_COND_MASK); 693 694 bool __ok; 695 const bool __z = (psr & PSR_Z_bit); 696 const bool __n = (psr & PSR_N_bit); 697 const bool __c = (psr & PSR_C_bit); 698 const bool __v = (psr & PSR_V_bit); 699 switch (__cond & ~1) { 700 case INSN_COND_EQ: // Z == 1 701 __ok = __z; 702 break; 703 case INSN_COND_CS: // C == 1 704 __ok = __c; 705 break; 706 case INSN_COND_MI: // N == 1 707 __ok = __n; 708 break; 709 case INSN_COND_VS: // V == 1 710 __ok = __v; 711 break; 712 case INSN_COND_HI: // C == 1 && Z == 0 713 __ok = __c && !__z; 714 break; 715 case INSN_COND_GE: // N == V 716 __ok = __n == __v; 717 break; 718 case INSN_COND_GT: // N == V && Z == 0 719 __ok = __n == __v && !__z; 720 break; 721 default: /* INSN_COND_AL or unconditional */ 722 return true; 723 } 724 725 return (__cond & 1) ? !__ok : __ok; 726 } 727 #endif /* !__ASSEMBLER && _KERNEL */ 728 729 #if !defined(__ASSEMBLER__) && !defined(_RUMPKERNEL) 730 #define ARMREG_READ_INLINE(name, __insnstring) \ 731 static inline uint32_t armreg_##name##_read(void) \ 732 { \ 733 uint32_t __rv; \ 734 __asm __volatile("mrc " __insnstring : "=r"(__rv)); \ 735 return __rv; \ 736 } 737 738 #define ARMREG_WRITE_INLINE(name, __insnstring) \ 739 static inline void armreg_##name##_write(uint32_t __val) \ 740 { \ 741 __asm __volatile("mcr " __insnstring :: "r"(__val)); \ 742 } 743 744 #define ARMREG_READ_INLINE2(name, __insnstring) \ 745 static inline uint32_t armreg_##name##_read(void) \ 746 { \ 747 uint32_t __rv; \ 748 __asm __volatile(".fpu vfp"); \ 749 __asm __volatile(__insnstring : "=r"(__rv)); \ 750 return __rv; \ 751 } 752 753 #define ARMREG_WRITE_INLINE2(name, __insnstring) \ 754 static inline void armreg_##name##_write(uint32_t __val) \ 755 { \ 756 __asm __volatile(".fpu vfp"); \ 757 __asm __volatile(__insnstring :: "r"(__val)); \ 758 } 759 760 #define ARMREG_READ64_INLINE(name, __insnstring) \ 761 static inline uint64_t armreg_##name##_read(void) \ 762 { \ 763 uint64_t __rv; \ 764 __asm __volatile("mrrc " __insnstring : "=r"(__rv)); \ 765 return __rv; \ 766 } 767 768 #define ARMREG_WRITE64_INLINE(name, __insnstring) \ 769 static inline void armreg_##name##_write(uint64_t __val) \ 770 { \ 771 __asm __volatile("mcrr " __insnstring :: "r"(__val)); \ 772 } 773 774 /* cp10 registers */ 775 ARMREG_READ_INLINE2(fpsid, ".fpu vfp\n vmrs\t%0, fpsid") /* VFP System ID */ 776 ARMREG_READ_INLINE2(fpscr, ".fpu vfp\n vmrs\t%0, fpscr") /* VFP Status/Control Register */ 777 ARMREG_WRITE_INLINE2(fpscr, ".fpu vfp\n vmsr\tfpscr, %0") /* VFP Status/Control Register */ 778 ARMREG_READ_INLINE2(mvfr1, ".fpu vfp\n vmrs\t%0, mvfr1") /* Media and VFP Feature Register 1 */ 779 ARMREG_READ_INLINE2(mvfr0, ".fpu vfp\n vmrs\t%0, mvfr0") /* Media and VFP Feature Register 0 */ 780 ARMREG_READ_INLINE2(fpexc, ".fpu vfp\n vmrs\t%0, fpexc") /* VFP Exception Register */ 781 ARMREG_WRITE_INLINE2(fpexc, ".fpu vfp\n vmsr\tfpexc, %0") /* VFP Exception Register */ 782 ARMREG_READ_INLINE2(fpinst, ".fpu vfp\n fmrx\t%0, fpinst") /* VFP Exception Instruction */ 783 ARMREG_WRITE_INLINE2(fpinst, ".fpu vfp\n vmsr\tfpinst, %0") /* VFP Exception Instruction */ 784 ARMREG_READ_INLINE2(fpinst2, ".fpu vfp\n fmrx\t%0, fpinst2") /* VFP Exception Instruction 2 */ 785 ARMREG_WRITE_INLINE2(fpinst2, ".fpu vfp\n fmxr\tfpinst2, %0") /* VFP Exception Instruction 2 */ 786 787 /* cp15 c0 registers */ 788 ARMREG_READ_INLINE(midr, "p15,0,%0,c0,c0,0") /* Main ID Register */ 789 ARMREG_READ_INLINE(ctr, "p15,0,%0,c0,c0,1") /* Cache Type Register */ 790 ARMREG_READ_INLINE(tlbtr, "p15,0,%0,c0,c0,3") /* TLB Type Register */ 791 ARMREG_READ_INLINE(mpidr, "p15,0,%0,c0,c0,5") /* Multiprocess Affinity Register */ 792 ARMREG_READ_INLINE(revidr, "p15,0,%0,c0,c0,6") /* Revision ID Register */ 793 ARMREG_READ_INLINE(pfr0, "p15,0,%0,c0,c1,0") /* Processor Feature Register 0 */ 794 ARMREG_READ_INLINE(pfr1, "p15,0,%0,c0,c1,1") /* Processor Feature Register 1 */ 795 ARMREG_READ_INLINE(mmfr0, "p15,0,%0,c0,c1,4") /* Memory Model Feature Register 0 */ 796 ARMREG_READ_INLINE(mmfr1, "p15,0,%0,c0,c1,5") /* Memory Model Feature Register 1 */ 797 ARMREG_READ_INLINE(mmfr2, "p15,0,%0,c0,c1,6") /* Memory Model Feature Register 2 */ 798 ARMREG_READ_INLINE(mmfr3, "p15,0,%0,c0,c1,7") /* Memory Model Feature Register 3 */ 799 ARMREG_READ_INLINE(isar0, "p15,0,%0,c0,c2,0") /* Instruction Set Attribute Register 0 */ 800 ARMREG_READ_INLINE(isar1, "p15,0,%0,c0,c2,1") /* Instruction Set Attribute Register 1 */ 801 ARMREG_READ_INLINE(isar2, "p15,0,%0,c0,c2,2") /* Instruction Set Attribute Register 2 */ 802 ARMREG_READ_INLINE(isar3, "p15,0,%0,c0,c2,3") /* Instruction Set Attribute Register 3 */ 803 ARMREG_READ_INLINE(isar4, "p15,0,%0,c0,c2,4") /* Instruction Set Attribute Register 4 */ 804 ARMREG_READ_INLINE(isar5, "p15,0,%0,c0,c2,5") /* Instruction Set Attribute Register 5 */ 805 ARMREG_READ_INLINE(ccsidr, "p15,1,%0,c0,c0,0") /* Cache Size ID Register */ 806 ARMREG_READ_INLINE(clidr, "p15,1,%0,c0,c0,1") /* Cache Level ID Register */ 807 ARMREG_READ_INLINE(csselr, "p15,2,%0,c0,c0,0") /* Cache Size Selection Register */ 808 ARMREG_WRITE_INLINE(csselr, "p15,2,%0,c0,c0,0") /* Cache Size Selection Register */ 809 /* cp15 c1 registers */ 810 ARMREG_READ_INLINE(sctlr, "p15,0,%0,c1,c0,0") /* System Control Register */ 811 ARMREG_WRITE_INLINE(sctlr, "p15,0,%0,c1,c0,0") /* System Control Register */ 812 ARMREG_READ_INLINE(auxctl, "p15,0,%0,c1,c0,1") /* Auxiliary Control Register */ 813 ARMREG_WRITE_INLINE(auxctl, "p15,0,%0,c1,c0,1") /* Auxiliary Control Register */ 814 ARMREG_READ_INLINE(cpacr, "p15,0,%0,c1,c0,2") /* Co-Processor Access Control Register */ 815 ARMREG_WRITE_INLINE(cpacr, "p15,0,%0,c1,c0,2") /* Co-Processor Access Control Register */ 816 ARMREG_READ_INLINE(scr, "p15,0,%0,c1,c1,0") /* Secure Configuration Register */ 817 ARMREG_READ_INLINE(nsacr, "p15,0,%0,c1,c1,2") /* Non-Secure Access Control Register */ 818 /* cp15 c2 registers */ 819 ARMREG_READ_INLINE(ttbr, "p15,0,%0,c2,c0,0") /* Translation Table Base Register 0 */ 820 ARMREG_WRITE_INLINE(ttbr, "p15,0,%0,c2,c0,0") /* Translation Table Base Register 0 */ 821 ARMREG_READ_INLINE(ttbr1, "p15,0,%0,c2,c0,1") /* Translation Table Base Register 1 */ 822 ARMREG_WRITE_INLINE(ttbr1, "p15,0,%0,c2,c0,1") /* Translation Table Base Register 1 */ 823 ARMREG_READ_INLINE(ttbcr, "p15,0,%0,c2,c0,2") /* Translation Table Base Register */ 824 ARMREG_WRITE_INLINE(ttbcr, "p15,0,%0,c2,c0,2") /* Translation Table Base Register */ 825 /* cp15 c3 registers */ 826 ARMREG_READ_INLINE(dacr, "p15,0,%0,c3,c0,0") /* Domain Access Control Register */ 827 ARMREG_WRITE_INLINE(dacr, "p15,0,%0,c3,c0,0") /* Domain Access Control Register */ 828 /* cp15 c5 registers */ 829 ARMREG_READ_INLINE(dfsr, "p15,0,%0,c5,c0,0") /* Data Fault Status Register */ 830 ARMREG_READ_INLINE(ifsr, "p15,0,%0,c5,c0,1") /* Instruction Fault Status Register */ 831 /* cp15 c6 registers */ 832 ARMREG_READ_INLINE(dfar, "p15,0,%0,c6,c0,0") /* Data Fault Address Register */ 833 ARMREG_READ_INLINE(ifar, "p15,0,%0,c6,c0,2") /* Instruction Fault Address Register */ 834 /* cp15 c7 registers */ 835 ARMREG_WRITE_INLINE(icialluis, "p15,0,%0,c7,c1,0") /* Instruction Inv All (IS) */ 836 ARMREG_WRITE_INLINE(bpiallis, "p15,0,%0,c7,c1,6") /* Branch Predictor Invalidate All (IS) */ 837 ARMREG_READ_INLINE(par, "p15,0,%0,c7,c4,0") /* Physical Address Register */ 838 ARMREG_WRITE_INLINE(iciallu, "p15,0,%0,c7,c5,0") /* Instruction Invalidate All */ 839 ARMREG_WRITE_INLINE(icimvau, "p15,0,%0,c7,c5,1") /* Instruction Invalidate MVA */ 840 ARMREG_WRITE_INLINE(isb, "p15,0,%0,c7,c5,4") /* Instruction Synchronization Barrier */ 841 ARMREG_WRITE_INLINE(bpiall, "p15,0,%0,c7,c5,6") /* Branch Predictor Invalidate All */ 842 ARMREG_WRITE_INLINE(bpimva, "p15,0,%0,c7,c5,7") /* Branch Predictor invalidate by MVA */ 843 ARMREG_WRITE_INLINE(dcimvac, "p15,0,%0,c7,c6,1") /* Data Invalidate MVA to PoC */ 844 ARMREG_WRITE_INLINE(dcisw, "p15,0,%0,c7,c6,2") /* Data Invalidate Set/Way */ 845 ARMREG_WRITE_INLINE(ats1cpr, "p15,0,%0,c7,c8,0") /* AddrTrans CurState PL1 Read */ 846 ARMREG_WRITE_INLINE(ats1cpw, "p15,0,%0,c7,c8,1") /* AddrTrans CurState PL1 Write */ 847 ARMREG_WRITE_INLINE(ats1cur, "p15,0,%0,c7,c8,2") /* AddrTrans CurState PL0 Read */ 848 ARMREG_WRITE_INLINE(ats1cuw, "p15,0,%0,c7,c8,3") /* AddrTrans CurState PL0 Write */ 849 ARMREG_WRITE_INLINE(dccmvac, "p15,0,%0,c7,c10,1") /* Data Clean MVA to PoC */ 850 ARMREG_WRITE_INLINE(dccsw, "p15,0,%0,c7,c10,2") /* Data Clean Set/Way */ 851 ARMREG_WRITE_INLINE(dsb, "p15,0,%0,c7,c10,4") /* Data Synchronization Barrier */ 852 ARMREG_WRITE_INLINE(dmb, "p15,0,%0,c7,c10,5") /* Data Memory Barrier */ 853 ARMREG_WRITE_INLINE(dccmvau, "p15,0,%0,c7,c11,1") /* Data Clean MVA to PoU */ 854 ARMREG_WRITE_INLINE(dccimvac, "p15,0,%0,c7,c14,1") /* Data Clean&Inv MVA to PoC */ 855 ARMREG_WRITE_INLINE(dccisw, "p15,0,%0,c7,c14,2") /* Data Clean&Inv Set/Way */ 856 /* cp15 c8 registers */ 857 ARMREG_WRITE_INLINE(tlbiallis, "p15,0,%0,c8,c3,0") /* Invalidate entire unified TLB, inner shareable */ 858 ARMREG_WRITE_INLINE(tlbimvais, "p15,0,%0,c8,c3,1") /* Invalidate unified TLB by MVA, inner shareable */ 859 ARMREG_WRITE_INLINE(tlbiasidis, "p15,0,%0,c8,c3,2") /* Invalidate unified TLB by ASID, inner shareable */ 860 ARMREG_WRITE_INLINE(tlbimvaais, "p15,0,%0,c8,c3,3") /* Invalidate unified TLB by MVA, all ASID, inner shareable */ 861 ARMREG_WRITE_INLINE(itlbiall, "p15,0,%0,c8,c5,0") /* Invalidate entire instruction TLB */ 862 ARMREG_WRITE_INLINE(itlbimva, "p15,0,%0,c8,c5,1") /* Invalidate instruction TLB by MVA */ 863 ARMREG_WRITE_INLINE(itlbiasid, "p15,0,%0,c8,c5,2") /* Invalidate instruction TLB by ASID */ 864 ARMREG_WRITE_INLINE(dtlbiall, "p15,0,%0,c8,c6,0") /* Invalidate entire data TLB */ 865 ARMREG_WRITE_INLINE(dtlbimva, "p15,0,%0,c8,c6,1") /* Invalidate data TLB by MVA */ 866 ARMREG_WRITE_INLINE(dtlbiasid, "p15,0,%0,c8,c6,2") /* Invalidate data TLB by ASID */ 867 ARMREG_WRITE_INLINE(tlbiall, "p15,0,%0,c8,c7,0") /* Invalidate entire unified TLB */ 868 ARMREG_WRITE_INLINE(tlbimva, "p15,0,%0,c8,c7,1") /* Invalidate unified TLB by MVA */ 869 ARMREG_WRITE_INLINE(tlbiasid, "p15,0,%0,c8,c7,2") /* Invalidate unified TLB by ASID */ 870 ARMREG_WRITE_INLINE(tlbimvaa, "p15,0,%0,c8,c7,3") /* Invalidate unified TLB by MVA, all ASID */ 871 /* cp15 c9 registers */ 872 ARMREG_READ_INLINE(pmcr, "p15,0,%0,c9,c12,0") /* PMC Control Register */ 873 ARMREG_WRITE_INLINE(pmcr, "p15,0,%0,c9,c12,0") /* PMC Control Register */ 874 ARMREG_READ_INLINE(pmcntenset, "p15,0,%0,c9,c12,1") /* PMC Count Enable Set */ 875 ARMREG_WRITE_INLINE(pmcntenset, "p15,0,%0,c9,c12,1") /* PMC Count Enable Set */ 876 ARMREG_READ_INLINE(pmcntenclr, "p15,0,%0,c9,c12,2") /* PMC Count Enable Clear */ 877 ARMREG_WRITE_INLINE(pmcntenclr, "p15,0,%0,c9,c12,2") /* PMC Count Enable Clear */ 878 ARMREG_READ_INLINE(pmovsr, "p15,0,%0,c9,c12,3") /* PMC Overflow Flag Status */ 879 ARMREG_WRITE_INLINE(pmovsr, "p15,0,%0,c9,c12,3") /* PMC Overflow Flag Status */ 880 ARMREG_READ_INLINE(pmselr, "p15,0,%0,c9,c12,5") /* PMC Event Counter Selection */ 881 ARMREG_WRITE_INLINE(pmselr, "p15,0,%0,c9,c12,5") /* PMC Event Counter Selection */ 882 ARMREG_READ_INLINE(pmceid0, "p15,0,%0,c9,c12,6") /* PMC Event ID 0 */ 883 ARMREG_READ_INLINE(pmceid1, "p15,0,%0,c9,c12,7") /* PMC Event ID 1 */ 884 ARMREG_READ_INLINE(pmccntr, "p15,0,%0,c9,c13,0") /* PMC Cycle Counter */ 885 ARMREG_WRITE_INLINE(pmccntr, "p15,0,%0,c9,c13,0") /* PMC Cycle Counter */ 886 ARMREG_READ_INLINE(pmxevtyper, "p15,0,%0,c9,c13,1") /* PMC Event Type Select */ 887 ARMREG_WRITE_INLINE(pmxevtyper, "p15,0,%0,c9,c13,1") /* PMC Event Type Select */ 888 ARMREG_READ_INLINE(pmxevcntr, "p15,0,%0,c9,c13,2") /* PMC Event Count */ 889 ARMREG_WRITE_INLINE(pmxevcntr, "p15,0,%0,c9,c13,2") /* PMC Event Count */ 890 ARMREG_READ_INLINE(pmuserenr, "p15,0,%0,c9,c14,0") /* PMC User Enable */ 891 ARMREG_WRITE_INLINE(pmuserenr, "p15,0,%0,c9,c14,0") /* PMC User Enable */ 892 ARMREG_READ_INLINE(pmintenset, "p15,0,%0,c9,c14,1") /* PMC Interrupt Enable Set */ 893 ARMREG_WRITE_INLINE(pmintenset, "p15,0,%0,c9,c14,1") /* PMC Interrupt Enable Set */ 894 ARMREG_READ_INLINE(pmintenclr, "p15,0,%0,c9,c14,2") /* PMC Interrupt Enable Clear */ 895 ARMREG_WRITE_INLINE(pmintenclr, "p15,0,%0,c9,c14,2") /* PMC Interrupt Enable Clear */ 896 ARMREG_READ_INLINE(l2ctrl, "p15,1,%0,c9,c0,2") /* A7/A15 L2 Control Register */ 897 /* cp10 c10 registers */ 898 ARMREG_READ_INLINE(prrr, "p15,0,%0,c10,c2,0") /* Primary Region Remap Register */ 899 ARMREG_WRITE_INLINE(prrr, "p15,0,%0,c10,c2,0") /* Primary Region Remap Register */ 900 ARMREG_READ_INLINE(nmrr, "p15,0,%0,c10,c2,1") /* Normal Memory Remap Register */ 901 ARMREG_WRITE_INLINE(nmrr, "p15,0,%0,c10,c2,1") /* Normal Memory Remap Register */ 902 /* cp15 c13 registers */ 903 ARMREG_READ_INLINE(contextidr, "p15,0,%0,c13,c0,1") /* Context ID Register */ 904 ARMREG_WRITE_INLINE(contextidr, "p15,0,%0,c13,c0,1") /* Context ID Register */ 905 ARMREG_READ_INLINE(tpidrurw, "p15,0,%0,c13,c0,2") /* User read-write Thread ID Register */ 906 ARMREG_WRITE_INLINE(tpidrurw, "p15,0,%0,c13,c0,2") /* User read-write Thread ID Register */ 907 ARMREG_READ_INLINE(tpidruro, "p15,0,%0,c13,c0,3") /* User read-only Thread ID Register */ 908 ARMREG_WRITE_INLINE(tpidruro, "p15,0,%0,c13,c0,3") /* User read-only Thread ID Register */ 909 ARMREG_READ_INLINE(tpidrprw, "p15,0,%0,c13,c0,4") /* PL1 only Thread ID Register */ 910 ARMREG_WRITE_INLINE(tpidrprw, "p15,0,%0,c13,c0,4") /* PL1 only Thread ID Register */ 911 /* cp14 c12 registers */ 912 ARMREG_READ_INLINE(vbar, "p15,0,%0,c12,c0,0") /* Vector Base Address Register */ 913 ARMREG_WRITE_INLINE(vbar, "p15,0,%0,c12,c0,0") /* Vector Base Address Register */ 914 /* cp15 c14 registers */ 915 /* cp15 Global Timer Registers */ 916 ARMREG_READ_INLINE(cnt_frq, "p15,0,%0,c14,c0,0") /* Counter Frequency Register */ 917 ARMREG_WRITE_INLINE(cnt_frq, "p15,0,%0,c14,c0,0") /* Counter Frequency Register */ 918 ARMREG_READ_INLINE(cntk_ctl, "p15,0,%0,c14,c1,0") /* Timer PL1 Control Register */ 919 ARMREG_WRITE_INLINE(cntk_ctl, "p15,0,%0,c14,c1,0") /* Timer PL1 Control Register */ 920 ARMREG_READ_INLINE(cntp_tval, "p15,0,%0,c14,c2,0") /* PL1 Physical TimerValue Register */ 921 ARMREG_WRITE_INLINE(cntp_tval, "p15,0,%0,c14,c2,0") /* PL1 Physical TimerValue Register */ 922 ARMREG_READ_INLINE(cntp_ctl, "p15,0,%0,c14,c2,1") /* PL1 Physical Timer Control Register */ 923 ARMREG_WRITE_INLINE(cntp_ctl, "p15,0,%0,c14,c2,1") /* PL1 Physical Timer Control Register */ 924 ARMREG_READ_INLINE(cntv_tval, "p15,0,%0,c14,c3,0") /* Virtual TimerValue Register */ 925 ARMREG_WRITE_INLINE(cntv_tval, "p15,0,%0,c14,c3,0") /* Virtual TimerValue Register */ 926 ARMREG_READ_INLINE(cntv_ctl, "p15,0,%0,c14,c3,1") /* Virtual Timer Control Register */ 927 ARMREG_WRITE_INLINE(cntv_ctl, "p15,0,%0,c14,c3,1") /* Virtual Timer Control Register */ 928 ARMREG_READ64_INLINE(cntp_ct, "p15,0,%Q0,%R0,c14") /* Physical Count Register */ 929 ARMREG_WRITE64_INLINE(cntp_ct, "p15,0,%Q0,%R0,c14") /* Physical Count Register */ 930 ARMREG_READ64_INLINE(cntv_ct, "p15,1,%Q0,%R0,c14") /* Virtual Count Register */ 931 ARMREG_WRITE64_INLINE(cntv_ct, "p15,1,%Q0,%R0,c14") /* Virtual Count Register */ 932 ARMREG_READ64_INLINE(cntp_cval, "p15,2,%Q0,%R0,c14") /* PL1 Physical Timer CompareValue Register */ 933 ARMREG_WRITE64_INLINE(cntp_cval, "p15,2,%Q0,%R0,c14") /* PL1 Physical Timer CompareValue Register */ 934 ARMREG_READ64_INLINE(cntv_cval, "p15,3,%Q0,%R0,c14") /* PL1 Virtual Timer CompareValue Register */ 935 ARMREG_WRITE64_INLINE(cntv_cval, "p15,3,%Q0,%R0,c14") /* PL1 Virtual Timer CompareValue Register */ 936 ARMREG_READ64_INLINE(cntvoff, "p15,4,%Q0,%R0,c14") /* Virtual Offset Register */ 937 ARMREG_WRITE64_INLINE(cntvoff, "p15,4,%Q0,%R0,c14") /* Virtual Offset Register */ 938 /* cp15 c15 registers */ 939 /* Cortex A17 Diagnostic control registers */ 940 ARMREG_READ_INLINE(dgnctlr0, "p15,0,%0,c15,c0,0") /* DGNCTLR0 */ 941 ARMREG_WRITE_INLINE(dgnctlr0, "p15,0,%0,c15,c0,0") /* DGNCTLR0 */ 942 ARMREG_READ_INLINE(dgnctlr1, "p15,0,%0,c15,c0,1") /* DGNCTLR1 */ 943 ARMREG_WRITE_INLINE(dgnctlr1, "p15,0,%0,c15,c0,1") /* DGNCTLR1 */ 944 ARMREG_READ_INLINE(dgnctlr2, "p15,0,%0,c15,c0,2") /* DGNCTLR2 */ 945 ARMREG_WRITE_INLINE(dgnctlr2, "p15,0,%0,c15,c0,2") /* DGNCTLR2 */ 946 947 ARMREG_READ_INLINE(cbar, "p15,4,%0,c15,c0,0") /* Configuration Base Address Register */ 948 949 ARMREG_READ_INLINE(pmcrv6, "p15,0,%0,c15,c12,0") /* PMC Control Register (armv6) */ 950 ARMREG_WRITE_INLINE(pmcrv6, "p15,0,%0,c15,c12,0") /* PMC Control Register (armv6) */ 951 ARMREG_READ_INLINE(pmccntrv6, "p15,0,%0,c15,c12,1") /* PMC Cycle Counter (armv6) */ 952 ARMREG_WRITE_INLINE(pmccntrv6, "p15,0,%0,c15,c12,1") /* PMC Cycle Counter (armv6) */ 953 954 ARMREG_READ_INLINE(tlbdata0, "p15,3,%0,c15,c0,0") /* TLB Data Register 0 (cortex) */ 955 ARMREG_READ_INLINE(tlbdata1, "p15,3,%0,c15,c0,1") /* TLB Data Register 1 (cortex) */ 956 ARMREG_READ_INLINE(tlbdata2, "p15,3,%0,c15,c0,2") /* TLB Data Register 2 (cortex) */ 957 ARMREG_WRITE_INLINE(tlbdataop, "p15,3,%0,c15,c4,2") /* TLB Data Read Operation (cortex) */ 958 959 ARMREG_READ_INLINE(sheeva_xctrl, "p15,1,%0,c15,c1,0") /* Sheeva eXtra Control register */ 960 ARMREG_WRITE_INLINE(sheeva_xctrl, "p15,1,%0,c15,c1,0") /* Sheeva eXtra Control register */ 961 962 #if defined(_KERNEL) 963 964 static inline uint64_t 965 cpu_mpidr_aff_read(void) 966 { 967 968 return armreg_mpidr_read() & (MPIDR_AFF2|MPIDR_AFF1|MPIDR_AFF0); 969 } 970 971 /* 972 * GENERIC TIMER register access 973 */ 974 static inline uint32_t 975 gtmr_cntfrq_read(void) 976 { 977 978 return armreg_cnt_frq_read(); 979 } 980 981 static inline uint32_t 982 gtmr_cntk_ctl_read(void) 983 { 984 985 return armreg_cntk_ctl_read(); 986 } 987 988 static inline void 989 gtmr_cntk_ctl_write(uint32_t val) 990 { 991 992 armreg_cntk_ctl_write(val); 993 } 994 995 static inline uint64_t 996 gtmr_cntpct_read(void) 997 { 998 999 return armreg_cntp_ct_read(); 1000 } 1001 1002 /* 1003 * Counter-timer Virtual Count timer 1004 */ 1005 static inline uint64_t 1006 gtmr_cntvct_read(void) 1007 { 1008 1009 return armreg_cntv_ct_read(); 1010 } 1011 1012 /* 1013 * Counter-timer Virtual Timer Control register 1014 */ 1015 static inline uint32_t 1016 gtmr_cntv_ctl_read(void) 1017 { 1018 1019 return armreg_cntv_ctl_read(); 1020 } 1021 1022 static inline void 1023 gtmr_cntv_ctl_write(uint32_t val) 1024 { 1025 1026 armreg_cntv_ctl_write(val); 1027 } 1028 1029 1030 /* 1031 * Counter-timer Physical Timer Control register 1032 */ 1033 1034 static inline uint32_t 1035 gtmr_cntp_ctl_read(void) 1036 { 1037 1038 return armreg_cntp_ctl_read(); 1039 } 1040 1041 static inline void 1042 gtmr_cntp_ctl_write(uint32_t val) 1043 { 1044 1045 armreg_cntp_ctl_write(val); 1046 } 1047 1048 1049 /* 1050 * Counter-timer Physical Timer TimerValue register 1051 */ 1052 static inline uint32_t 1053 gtmr_cntp_tval_read(void) 1054 { 1055 1056 return armreg_cntp_tval_read(); 1057 } 1058 1059 static inline void 1060 gtmr_cntp_tval_write(uint32_t val) 1061 { 1062 1063 armreg_cntp_tval_write(val); 1064 } 1065 1066 1067 /* 1068 * Counter-timer Virtual Timer TimerValue register 1069 */ 1070 static inline uint32_t 1071 gtmr_cntv_tval_read(void) 1072 { 1073 1074 return armreg_cntv_tval_read(); 1075 } 1076 1077 static inline void 1078 gtmr_cntv_tval_write(uint32_t val) 1079 { 1080 1081 armreg_cntv_tval_write(val); 1082 } 1083 1084 1085 /* 1086 * Counter-timer Physical Timer CompareValue register 1087 */ 1088 static inline uint64_t 1089 gtmr_cntp_cval_read(void) 1090 { 1091 1092 return armreg_cntp_cval_read(); 1093 } 1094 1095 static inline void 1096 gtmr_cntp_cval_write(uint64_t val) 1097 { 1098 1099 armreg_cntp_cval_write(val); 1100 } 1101 1102 1103 /* 1104 * Counter-timer Virtual Timer CompareValue register 1105 */ 1106 static inline uint64_t 1107 gtmr_cntv_cval_read(void) 1108 { 1109 1110 return armreg_cntv_cval_read(); 1111 } 1112 1113 static inline void 1114 gtmr_cntv_cval_write(uint64_t val) 1115 { 1116 1117 armreg_cntv_cval_write(val); 1118 } 1119 1120 #endif /* _KERNEL */ 1121 #endif /* !__ASSEMBLER && !_RUMPKERNEL */ 1122 1123 #elif defined(__aarch64__) 1124 1125 #include <aarch64/armreg.h> 1126 1127 #endif /* __arm__/__aarch64__ */ 1128 1129 #endif /* _ARM_ARMREG_H */ 1130
Indexes created Sat Sep 20 22:09:52 GMT 2025