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History log of /src/sys/arch/arm/include/armreg.h
RevisionDateAuthorComments
 1.136  03-Dec-2022  ryo move ARMv7 PMC register definitions to armreg.h from tprof_armv7.c
 1.135  20-May-2022  andvar s/auxillary/auxiliary/ in comments.
 1.134  27-Nov-2021  skrll Add the Cortex A17 Diagnostic control registers
 1.133  13-Nov-2021  jmcneill Set ACTLR.SMP=1 on Cortex-A17
 1.132  10-Oct-2021  skrll Add a placeholder for PRRR
 1.131  03-Sep-2021  andvar fix typos in comments, mainly s/extention/extension/ and s/sufficent/sufficient/
 1.130  31-Jan-2021  skrll Fix (unused) PRRR_NOSn #define
 1.129  29-Oct-2019  joerg branches: 1.129.8;
Explicitly annotate FPU requirements for LLVM MC.

When using GCC, this annotations change the global state, but there is
no push/pop functionality for .fpu to avoid this problem. The state is
local to each inline assembler block with LLVM MC.
 1.128  12-Aug-2019  jmcneill Add support for physical timers and sprinkle isb where needed.
 1.127  02-May-2019  skrll branches: 1.127.2;
It's the Normal Memory Remap Register (not Normal Region Remap Register)
 1.126  02-May-2019  skrll Fix Normal Region Remap Register bitmask names
 1.125  30-Jan-2019  jmcneill add gtmr_cntv_cval_write
 1.124  15-Aug-2018  skrll Some CPU specific ACTLR bit definitions
 1.123  12-Aug-2018  skrll Provide and use cpu_mpidr_aff_read in psci_fdt_bootstrap
 1.122  15-Jul-2018  jmcneill Add some PMC event registers
 1.121  14-May-2018  joerg branches: 1.121.2;
Workaround A-008585 errata in GTMR.

Register reads and writes may provide unstable results if the counter
hardware is active at the same time. This results in non-monotonic
counters seen by both the gtmr interrupt and time counter.

The loops are currently applied unconditionally, restricting them to
appropiate FDT markers can be applied later.
 1.120  01-Apr-2018  ryo Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@)

- sys/arch/evbarm64 is gone and integrated into sys/arch/evbarm. (by skrll@)
- add support fdt. evbarm/conf/GENERIC64 fdt (bcm2837,sunxi,tegra) based generic 64bit kernel config. (by skrll@, jmcneill@)
 1.119  20-Mar-2018  ryo separate cputypes.h for CPU_ID_* from armreg.h,
and add some implementor IDs, CortexA55,73,75 IDs.

(preliminary changes for merging aarch64)
 1.118  02-Mar-2018  christos branches: 1.118.2;
insert a couple of .fpu directives when we access the vfp registers while
is softvpf fpu mode for gcc 6. XXX: there is no .fpu push/pop...
 1.117  24-Jan-2018  skrll Remove port-acorn26

OK core@
 1.116  20-Dec-2017  skrll One copy of the generic timer register defines is enough for anyone. The
ARM_ prefixed copies are prefered (at this point) and the comments from
the non-ARM_ prefixed versions are copied over.
 1.115  20-Dec-2017  skrll Correct ARM_CNTKCTL_PL0[VP]CTEN values. NFC as nothing uses them.
 1.114  17-Dec-2017  skrll Typo in comment
cvS: ----------------------------------------------------------------------
 1.113  24-Oct-2017  skrll Some more registers
 1.112  16-Sep-2017  matt Add Cortex-A35 CPU ID.
 1.111  17-May-2016  msaitoh branches: 1.111.14;
Fix CORTEXA9Rx definitions.
 1.110  03-Mar-2016  skrll Get the RPI3 working (in aarch32 mode) by recognising Cortex A53 CPUs.
While I'm here add some A57/A72 info as well.

My RPI3 works with FB console - the uart needs some help with its clocks.
 1.109  15-Oct-2015  skrll No need to shout
 1.108  15-Oct-2015  skrll Setting actlr.bit15=1 (Force in order issue in the branch execution unit)
makes my jetson tk1 stable. Apply this workaround until we figure out
what the real problem is.
 1.107  09-Jun-2015  skrll Use TTBR_[UM]PATTR in a9_mpsubr.S as well as cpufunc_asm_armv7

Prompted by matt@
 1.106  30-May-2015  skrll Add Revision ID register
 1.105  20-May-2015  hsuenaga move register accessor macros for MPIDR and AUXFMC0 to armreg.h
 1.104  27-Apr-2015  skrll Trailing whitespace
 1.103  27-Apr-2015  skrll ARM spells the System Control Register SCTLR
 1.102  27-Nov-2014  matt branches: 1.102.2;
Add Cortex-A17 ID
 1.101  15-Oct-2014  skrll Fix dccmvau. Add bpimva.
 1.100  15-Oct-2014  skrll Fix bpiall and the comment against bpiallis
 1.99  12-Oct-2014  skrll Minor amendment/corrections.
 1.98  16-Sep-2014  matt Remove redundant CORTEXA9_AUXCTL defines
 1.97  14-Apr-2014  matt branches: 1.97.2;
Support (untested) SHEEVA_L2_CACHE and SHEEVA_L2_CACHE_WT options.
Move prototypes out to <arm/cpufunc.h> to their own file.
Add sdcache routines to cpufunc_asm_sheeva.S
Add code sheeve_setup to init the sdcache and sdcache info.
 1.96  13-Apr-2014  matt Add tpidruro and tpidrurw inlines
 1.95  29-Mar-2014  matt branches: 1.95.2;
Add scr inline
 1.94  26-Mar-2014  matt Add NSACR
 1.93  07-Mar-2014  matt Restrict arm_cond_ok_p to when !__ASSEMBLER && _KERNEL is true.
 1.92  07-Mar-2014  matt Avoid a gcc4.8 bogon.
 1.91  05-Mar-2014  matt Define all the instruction conditions.
Use __SHIFTOUT to get the condition.
Add bool arm_cond_ok_p(uint32_t insn, uint32_t psr) inline
Add tlbtr inline
 1.90  03-Mar-2014  matt More control bits.
SYNCHPRIM defines.
 1.89  01-Mar-2014  matt Fix typos
 1.88  01-Mar-2014  matt defines/inlines for cortex a5/a7 tlbdata ops
 1.87  26-Feb-2014  matt Add more MMU registers
 1.86  24-Feb-2014  matt Add more inlines. Default FSR ARMv6+ bits. Add A7/A15 L2CTRL defs.
 1.85  10-Jan-2014  matt Flush out the PSR definitions.
 1.84  27-Dec-2013  matt Switch to using FP instructions instead of cp10/11 instructions.
 1.83  07-Sep-2013  matt fix CPU_ID_CORTEXA7R0
 1.82  02-Aug-2013  matt Add MVFR (Media & VFP Features) definitions.
 1.81  02-Jul-2013  matt Add TTBCR definitions
 1.80  16-Jun-2013  matt branches: 1.80.2;
Improve generic timer inlines to be cnt*_* consistently
 1.79  12-Jun-2013  matt Fix VBAR inlines
 1.78  12-Jun-2013  matt Fix ARM_PRF1_SEC_MASK value.
 1.77  12-Jun-2013  matt Add defines for ARM Generic Timer
Add defines for PFR1 GTIMER and SEC extensions.
Add VBAR inlines
 1.76  01-May-2013  rkujawa Add Armada XP specific IDs and registers.

Obtained from Marvell, Semihalf.
 1.75  28-Apr-2013  kiyohara Fix ID ARM710a for CL PS-711x.
 1.74  28-Feb-2013  matt Add c16 c8 (tlb) inlines.
Add CPUID of Cortex-A7 r0
 1.73  12-Feb-2013  matt Add inlines for cp10 (vfp) registers
 1.72  24-Jan-2013  matt Don't define CP15 inlines when compiling for a _RUMPKERNEL
 1.71  25-Dec-2012  matt Add CP15 Generic Timer definitions.
Add cortex PMUSERENR inlines
 1.70  29-Nov-2012  matt Add inlines for SCTRL
 1.69  27-Sep-2012  matt Add PSR_HYP32_MODE (hypervisor mode).
 1.68  22-Sep-2012  matt Only use CPACR register for ARM11 and CORTEX cores.
Add VFP ids for other CORTEX CPUs.
 1.67  22-Sep-2012  matt Before testing for VFP, make sure CP10 is enabled. (And CP11 for Neon too).
 1.66  22-Sep-2012  matt Don't use an asm in pmap_activate to update the TTBR, use cpu_setttb instead
but add a second argument to it to indicate whether the TLB/caches need to be
flushed. Default cortex to pmap_needs_fixup = 1. But check the MMFR3 field
to see if the fixed can be skipped.
Use a cf_flag bit 0 to indicate whether the A9 L2 cache should disable (bit 0 = 1)
or enabeld (bit = 0).

With these changes, the A9 MMU can use traverse caches to do MMU tablewalks
Also, make sure all memory has the shareable bit for the A9.
 1.65  11-Sep-2012  matt branches: 1.65.2;
Add more c7 register inlines. Add some more CT4 defintions
 1.64  07-Sep-2012  matt Switch cortex_a9 back to need_ptesync = 1
Add code to disable the L2 cache on cortex-a9 (for now).
Add evcnt for all the fault types.
Move cache info in a structure and have one for the pcache and one for scache.
Probe L1/L2 caches properly for ARMv7
 1.63  06-Sep-2012  matt Add ttbr/ttbr1/ttbcr registers
 1.62  31-Aug-2012  matt Use __ASSEMBLER__ to control inline definitions
 1.61  31-Aug-2012  matt Don't do inlines if _STANDALONE
 1.60  29-Aug-2012  matt Use new armv7 CP15 register to print out cache types.
If the cpu_cc_freq is set, report it.
Add macros to make inlines for reading/writing co-processor registers.
 1.59  15-Aug-2012  matt Add SWP enable bit to system control register (Cortex-A9).
 1.58  14-Aug-2012  matt Add __HAVE_CPU_COUNTER support for ARM11 and Cortex CPUs
 1.57  31-Jul-2012  matt Add MON32 mode (just for completeness).
 1.56  23-Jul-2012  skrll Make auxiliary register naming consistent for the 1136.
 1.55  17-Jul-2012  skrll Fix spelling mistake in comments.
 1.54  17-Jul-2012  skrll Add the documented ARM11[37]6 Auxiliary control register defines.
 1.53  14-Jul-2012  matt Fix CPU_ID_CORTEX_P and add CPU_ID_CORTEX_A8_P
 1.52  13-Jul-2012  matt Begin support for Cortex A5, A7, A15 and expand A8 and A9 definitions.
Instead of testing all possible CPUids for a cortex, we know what range
a cortex will be so mask out the insignificant parts and do a single test.
 1.51  20-May-2012  skrll Remove the ARM1156T2 bloat - it only has an MPU. Prompted by matt@
 1.50  20-May-2012  skrll Add the ARM1156T2-S
 1.49  20-May-2012  skrll Add the 'Z' to the 1176 cpu product name.

ok matt@
 1.48  30-Jun-2011  wiz branches: 1.48.2; 1.48.6; 1.48.8;
dependant -> dependent
 1.47  10-Mar-2011  bsh Preliminary ARM11 MPCore support.

I have confirmed this commit doesn't affect existing evbarm kernels by
comparing binaries.
 1.46  15-Dec-2010  bsh branches: 1.46.2;
fix XP bit and U bit definitions of CP15 control register.
These constants are not used in our source tree for now,
so this won't change any kernel bianries.
 1.45  02-Oct-2010  kiyohara Add support Marvell Sheeva Core and SoC. (Orion/Kirkwood)
Discovery Innovation not yet.
 1.44  19-Jun-2010  matt Fix cache probing on Cortex. Add missing CORTEX dependency in cpu.c
 1.43  19-Jun-2010  matt Cleanup the armv7 changes. Add ARM_ARCH_7. Use CPU_CORTEX instead of
CPU_CORTEXA8 everywhere since there more types of Cortex than just the A8.
CPU_CORTEXA8 still exists but causes CPU_CORTEX to be defined.
Add CPU_CORTEXA9 as well. Use .arch armv7a to get us the isb/dsb
instructions.

Test booted to root device prompt on a Beagleboard.
All ARM kernels successfully test built.
 1.42  16-Jun-2010  jmcneill PR port-arm/43299: Support added for igepv2/cortexa8/omap3530

Apply patch from PR, with build fixes. ok skrll, matt
 1.41  27-Aug-2008  matt branches: 1.41.12; 1.41.14; 1.41.16;
Add new CPU Cache register definitions for Cortex-A8.
 1.40  06-Aug-2008  matt Define IF32_bits as the union of I32_bit|F32_bit
 1.39  22-Jul-2008  matt Implement workaround for:
arm11 Errata 364296:Possible Cache Data Corruption with Hit-Under-Miss

Remove hack in userret which is redundant with workaround.

workaround code from <imre.deak@teleca.com>
 1.38  27-Apr-2008  matt branches: 1.38.2; 1.38.4; 1.38.6;
Merge kernel changes in matt-armv6 to HEAD.
 1.37  06-Jan-2007  christos branches: 1.37.26; 1.37.46; 1.37.48; 1.37.50;
Scott Allan in http://mail-index.netbsd.org/port-arm/2006/07/31/0000.html
Patch to add support for ARM9E
 1.36  26-Nov-2006  bjh21 branches: 1.36.2;
The ARM7500 ID is no longer a guess -- I've confirmed it on a real ARM7500.
 1.35  14-Apr-2006  nonaka branches: 1.35.8; 1.35.10;
Added FARADAY FA526 ID.
 1.34  11-Dec-2005  christos branches: 1.34.4; 1.34.6; 1.34.8; 1.34.10; 1.34.12;
merge ktrace-lwp.
 1.33  20-Jul-2005  nonaka Added i80219.
 1.32  03-Jun-2005  rearnsha branches: 1.32.2;
Add CPU_ID_ARCH_V5TEJ and CPU_ID_ARCH_V6.
Add CPU_IDs for ARM1136J-s and ARM1136J-S R1.
 1.31  10-May-2005  rearnsha Add CPU-id for arm1026ej-s.
 1.30  21-Aug-2004  rearnsha Define THUMB_INSN_SIZE.
 1.29  13-Apr-2004  bsh add CPU ID for Bulverde
 1.28  31-Oct-2003  scw Overhaul arm32's abort handlers:

- Assume a permission fault is always the result of an attempted
write, so no need to disassemble the opcode.
(as discussed with Richard Earnshaw/Jason Thorpe a week or two ago)

- Split out non-MMU data aborts into separate functions, and deal
correctly with XScale imprecise aborts. Specifically, the old code
made no attempt to handle the double abort faults which can occur
as a result of two consecutive external (imprecise) aborts. This
was easy to provoke by read(2)ing from a /dev/mem offset which caused
an external abort. With the old code, this would bring the system
down instantly, with little clue as to why. (hint: tf_spsr held
PSR_ABT32_MODE...)

- Re-write badaddr_read() to use pcb_onfault instead of adding extra
overhead to data_abort_handler(). A side effect of this is that it
now benefits from the XScale double abort recovery.

- Invoke the cpu-specific prefetch/data abort fixup routines only if
the host cpu actually needs it. On other cpus, the code is optimised
away.

- Sprinkle __predict_{false,true} in all the right places.

- G/C some excess debugging baggage.
 1.27  06-Sep-2003  rearnsha Add arm1020E cpu id
 1.26  03-Sep-2003  mycroft Recognize some TI processors -- not that you'd want to use them.
 1.25  13-May-2003  ichiro branches: 1.25.2;
add CPU types
IXP425 xscale-core NetworkProcessor

later, Ill commit codes for IXP425-evaluation board
 1.24  04-May-2003  thorpej Make the ARM_VECTORS_* unsigned.
 1.23  18-Mar-2003  bsh fix XScale core revision mask, and add masks for core generation and
product number.
 1.22  14-Feb-2003  rjs Add CPU IDs for PXA B2 and C0 steppings.
 1.21  22-Jul-2002  briggs Handle i80200 step D0 and i80321 step B0
 1.20  10-Jul-2002  ichiro add cpu id for "PXA250/210 3rd version CPUcore".

for using many PDA/xscale-core.
 1.19  07-Jun-2002  thorpej Add the CPU ID for the 600MHz i80321 part.
 1.18  27-Apr-2002  ichiro branches: 1.18.2; 1.18.4;
add CPU ID of IXP1200 network processor
 1.17  15-Apr-2002  thorpej Fix a typo and an omission in last.
 1.16  15-Apr-2002  thorpej Add bits for the XScale Auxillary Control Register.
 1.15  03-Apr-2002  thorpej Define the two possible addresses for the ARM vector page.
 1.14  03-Apr-2002  thorpej Add a comment summarizing the post-ARM3 CP15 registers.
 1.13  27-Mar-2002  thorpej The 80321 manual lies; it does have a CPU ID distinct from the 80200.
Add that CPU ID, and add a case for it.
 1.12  26-Mar-2002  thorpej Restructure a few things in order to support other XScale core
I/O processors:
* The i80200 and the i80321 have the same CPU ID, so split the
CPU_XSCALE option into CPU_XSCALE_80200 and CPU_XSCALE_80321
options, and don't let them both be defined at the same time.
XXX May want to revisit this in the future.
* Split some registers common between the i80200 and i80321 into
<arm/xscale/xscalereg.h>.
* Rename a few existing functions.
 1.11  16-Mar-2002  bjh21 Add CPU ID for the ARM1022ES.
Also add a CPU class for ARM10E processors in general.
 1.10  14-Feb-2002  rjs Add Cotulla CPU IDs.
 1.9  29-Nov-2001  thorpej Fetch cache info from the Cache Type register on ARM7TDMI and "greater"
processors. Report this when the processor is attached.
 1.8  18-Jul-2001  rjs branches: 1.8.6;
Add Jazelle mode flag.
 1.7  10-Mar-2001  bjh21 branches: 1.7.2;
Correct CPU_ID_ISOLD() and CPU_ID_IS7().
 1.6  04-Mar-2001  bjh21 branches: 1.6.2;
Add CPU ID for ARM7500FE (determined empirically from two I've got here).
 1.5  01-Mar-2001  bjh21 ARM7100 -> ARM710A, following information from reinoud.
 1.4  25-Feb-2001  bjh21 Guess a CPU ID for the ARM700 as well.
 1.3  25-Feb-2001  bjh21 Add possible CPU ID for ARM7500 (based on arm/cpu.h).
Add macros to distinguish the three formats of CPU ID.
 1.2  21-Feb-2001  bjh21 Add CPU_ID_CPU_MASK. Different, but (I hope) more useful definition than
arm32 currently uses.
 1.1  22-Jan-2001  bjh21 branches: 1.1.2;
Initial potentially sharable <arm/armreg.h>. Used by all arm26 code.
 1.1.2.3  12-Mar-2001  bouyer Sync with HEAD.
 1.1.2.2  11-Feb-2001  bouyer Sync with HEAD.
 1.1.2.1  22-Jan-2001  bouyer file armreg.h was added on branch thorpej_scsipi on 2001-02-11 19:08:51 +0000
 1.6.2.1  09-Apr-2001  nathanw Catch up with -current.
 1.7.2.5  06-Sep-2002  jdolecek sync kqueue branch with HEAD
 1.7.2.4  23-Jun-2002  jdolecek catch up with -current on kqueue branch
 1.7.2.3  16-Mar-2002  jdolecek Catch up with -current.
 1.7.2.2  10-Jan-2002  thorpej Sync kqueue branch with -current.
 1.7.2.1  03-Aug-2001  lukem update to -current
 1.8.6.7  01-Aug-2002  nathanw Catch up to -current.
 1.8.6.6  20-Jun-2002  nathanw Catch up to -current.
 1.8.6.5  17-Apr-2002  nathanw Catch up to -current.
 1.8.6.4  01-Apr-2002  nathanw Catch up to -current.
(CVS: It's not just a program. It's an adventure!)
 1.8.6.3  28-Feb-2002  nathanw Catch up to -current.
 1.8.6.2  08-Jan-2002  nathanw Catch up to -current.
 1.8.6.1  18-Jul-2001  nathanw file armreg.h was added on branch nathanw_sa on 2002-01-08 00:23:11 +0000
 1.18.4.2  29-Jul-2002  lukem Pull up revision 1.21 (requested by thorpej in ticket #549):
Handle i80200 step D0 and i80321 step B0
 1.18.4.1  07-Jun-2002  thorpej pullup-1-6 ticket #208:

syssrc/sys/arch/arm/arm/cpufunc.c 1.46
syssrc/sys/arch/arm/arm32/cpu.c 1.38
syssrc/sys/arch/arm/include/armreg.h 1.19

Original log message:

Add the CPU ID for the 600MHz i80321 part.
 1.18.2.3  30-Aug-2002  gehenna catch up with -current.
 1.18.2.2  16-Jul-2002  gehenna catch up with -current.
 1.18.2.1  14-Jul-2002  gehenna catch up with -current.
 1.25.2.5  10-Nov-2005  skrll Sync with HEAD. Here we go again...
 1.25.2.4  21-Sep-2004  skrll Fix the sync with head I botched.
 1.25.2.3  18-Sep-2004  skrll Sync with HEAD.
 1.25.2.2  25-Aug-2004  skrll Sync with HEAD.
 1.25.2.1  03-Aug-2004  skrll Sync with HEAD
 1.32.2.3  26-Feb-2007  yamt sync with head.
 1.32.2.2  30-Dec-2006  yamt sync with head.
 1.32.2.1  21-Jun-2006  yamt sync with head.
 1.34.12.1  24-May-2006  tron Merge 2006-05-24 NetBSD-current into the "peter-altq" branch.
 1.34.10.1  19-Apr-2006  elad sync with head - hopefully this will work
 1.34.8.1  24-May-2006  yamt sync with head.
 1.34.6.1  22-Apr-2006  simonb Sync with head.
 1.34.4.1  09-Sep-2006  rpaulo sync with head
 1.35.10.1  10-Dec-2006  yamt sync with head.
 1.35.8.1  12-Jan-2007  ad Sync with head.
 1.36.2.1  21-Feb-2007  snj branches: 1.36.2.1.4;
Pull up following revision(s) (requested by matt in ticket #457):
sys/arch/arm/include/cpufunc.h: revision 1.38
sys/arch/arm/arm/cpufunc.c: revision 1.78
sys/arch/arm/arm/cpufunc_asm_arm10.S: revision 1.6
sys/arch/arm/include/armreg.h: revision 1.37
sys/arch/arm/arm32/cpu.c: revision 1.64
sys/arch/arm/arm/cpufunc_asm_armv5.S: revision 1.3
sys/arch/arm/include/cpuconf.h: revision 1.13
sys/arch/arm/conf/files.arm: revision 1.82
sys/arch/arm/arm/cpufunc_asm_armv5_ec.S: revision 1.1
Scott Allan in http://mail-index.netbsd.org/port-arm/2006/07/31/0000.html
Patch to add support for ARM9E
 1.36.2.1.4.1  10-Nov-2007  matt Add AT91 support from Sami Kantoluoto
Add TI OMAP2430 support from Marty Fouts @ Danger Inc
 1.37.50.4  09-Oct-2010  yamt sync with head
 1.37.50.3  11-Aug-2010  yamt sync with head.
 1.37.50.2  04-May-2009  yamt sync with head.
 1.37.50.1  16-May-2008  yamt sync with head.
 1.37.48.1  18-May-2008  yamt sync with head.
 1.37.46.2  28-Sep-2008  mjf Sync with HEAD.
 1.37.46.1  02-Jun-2008  mjf Sync with HEAD.
 1.37.26.1  28-Aug-2007  matt Add ARM1176JS id. Add ARM11 PMC definition. Add cache P bit. Add cpuconf
armv6 XP and UNAL enable bits.
 1.38.6.1  19-Oct-2008  haad Sync with HEAD.
 1.38.4.1  28-Jul-2008  simonb Sync with head.
 1.38.2.1  18-Sep-2008  wrstuden Sync with wrstuden-revivesa-base-2.
 1.41.16.3  21-Apr-2011  rmind sync with head
 1.41.16.2  05-Mar-2011  rmind sync with head
 1.41.16.1  03-Jul-2010  rmind sync with head
 1.41.14.2  22-Oct-2010  uebayasi Sync with HEAD (-D20101022).
 1.41.14.1  17-Aug-2010  uebayasi Sync with HEAD.
 1.41.12.3  26-Mar-2014  matt sync with HEAD
 1.41.12.2  24-Mar-2014  matt merge l2ctrl from head
 1.41.12.1  15-Feb-2014  matt Merge armv7 support from HEAD, specifically support for the BCM5301X
and BCM56340 evbarm kernels.
 1.46.2.1  06-Jun-2011  jruoho Sync with HEAD.
 1.48.8.1  09-Aug-2012  jdc branches: 1.48.8.1.2;
Pull up revisions:
src/sys/arch/evbarm/dev/plcomreg.h revisions 1.2,1.3,1.4
src/sys/arch/evbarm/conf/INTEGRATOR revision 1.65
src/sys/arch/evbarm/dev/plcom.c revisions 1.34,1.35,1.36,1.37,1.38,1.39,1.40
src/sys/arch/evbarm/ifpga/plcom_ifpga.c revisions 1.12,1.13,1.14
src/sys/arch/evbarm/dev/plcomvar.h revisions 1.9,1.10,1.11
src/sys/arch/evbarm/ifpga/plcom_ifpgavar.h revision 1.2
src/sys/arch/arm/arm/cpufunc.c revisions 1.105,1.108
src/sys/arch/arm/arm32/cpu.c revision 1.79
src/sys/arch/arm/include/armreg.h revisions 1.49,1.54
src/sys/arch/arm/arm32/pmap.c revision 1.229
src/sys/arch/arm/arm32/arm32_machdep.c revision 1.77
src/sys/arch/arm/include/cpu.h revision 1.64
src/sys/arch/arm/arm/cpufunc_asm_arm1136.S revision 1.3
src/sys/arch/arm/arm/cpufunc_asm_arm11x6.S revision 1.1
src/sys/arch/arm/conf/files.arm revision 1.106
src/sys/arch/arm/include/cpufunc.h revision 1.57
src/sys/dev/sdmmc/sdhc.c revisions 1.14,1.24
src/sys/dev/sdmmc/sdhcvar.h revisions 1.7,1.8
src/sys/arch/evbarm/ifpga/ifpgareg.h revision 1.4
src/sys/arch/evbarm/integrator/integrator_machdep.c revision 1.69
src/sys/arch/arm/broadcom/bcm2835_dma.c revision 1.1
src/sys/arch/arm/broadcom/bcm2835_emmc.c revision 1.1
src/sys/arch/arm/broadcom/bcm2835_intr.c revision 1.1
src/sys/arch/arm/broadcom/bcm2835_intr.h revision 1.1
src/sys/arch/arm/broadcom/bcm2835_obio.c revision 1.1
src/sys/arch/arm/broadcom/bcm2835_plcom.c revision 1.1
src/sys/arch/arm/broadcom/bcm2835_pm.c revision 1.1
src/sys/arch/arm/broadcom/bcm2835_pmvar.h revision 1.1
src/sys/arch/arm/broadcom/bcm2835_space.c revision 1.1
src/sys/arch/arm/broadcom/bcm2835_tmr.c revision 1.1
src/sys/arch/arm/broadcom/bcm2835reg.h revision 1.1
src/sys/arch/arm/broadcom/bcm2835var.h revision 1.1
src/sys/arch/arm/broadcom/bcm_amba.h revision 1.1
src/sys/arch/arm/broadcom/files.bcm2835 revision 1.1
src/sys/arch/evbarm/Makefile revision 1.9
src/sys/arch/evbarm/conf/RPI revision 1.1
src/sys/arch/evbarm/conf/files.rpi revision 1.1
src/sys/arch/evbarm/conf/mk.rpi revision 1.1
src/sys/arch/evbarm/conf/std.rpi revision 1.1
src/sys/arch/evbarm/rpi/genassym.cf revision 1.1
src/sys/arch/evbarm/rpi/rpi.h revision 1.1
src/sys/arch/evbarm/rpi/rpi_machdep.c revision 1.1
src/sys/arch/evbarm/rpi/rpi_start.S revision 1.1,1.2
src/etc/etc.evbarm/Makefile.inc revision 1.28
(requested by skrll in ticket #454).

don't mix #define<TAB> and #define<SPACE> in a file.

avoid warning with options PLCOM_DEBUG for INTEGRATOR.

Rename register values. No functional change - same code before and after.

Existing names are prefixed with PL01X_ where they're common between the
PL010 and the PL011. The PL010_/PL011_ prefixes are added where they're
found only on the respective chips.

Replace the simple_lock with a kmutex_t. Update the locking to match
com(4) in the few places it didn't already.

DOH. Replace a line that got accidently deleted in the last commit.

device_t/softc split
struct device * -> device_t
struct cfdata * -> cfdata_t

Add the 'Z' to the 1176 cpu product name.

ok matt@

Fix locking botch introduced in 1.36.

Fix a KASSERT. From/OK'ed by matt@

Fix racy softint dispatch that lead to KASSERT(si->si_active) in
softint_execute

Discussed with matt@. "Looks good to me"

Add the documented ARM11[37]6 Auxiliary control register defines.

Add support for the ARM1176JZS

Add a flag for the lack of LED_ON in HOST_CTL (ti omap3 doesn't do that).

Provide a method for attachments to specify capabilites.

Add support for the PL011 to plcom. Pull across a bunch of fixes from
com(4) while I'm here and do some other tidyup.

Tested on a RaspberryPi.

PL010 not tested.

Initial commit of support for the RaspberryPI (www.raspberrypi.org)

This is enough for serial console via the gpio header pins and to get to
multiuser.

A huge thank you to Matt Thomas for all his help.

Add RPI to KERNEL_SETS

Remove #if 0 code.
 1.48.8.1.2.1  28-Nov-2012  matt Merge improved arm support (especially Cortex) from HEAD
including OMAP and BCM53xx support.
 1.48.6.1  02-Jun-2012  mrg sync to latest -current.
 1.48.2.5  22-May-2014  yamt sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
 1.48.2.4  23-Jan-2013  yamt sync with head
 1.48.2.3  16-Jan-2013  yamt sync with (a bit old) head
 1.48.2.2  30-Oct-2012  yamt sync with head
 1.48.2.1  23-May-2012  yamt sync with head.
 1.65.2.5  03-Dec-2017  jdolecek update from HEAD
 1.65.2.4  20-Aug-2014  tls Rebase to HEAD as of a few days ago.
 1.65.2.3  23-Jun-2013  tls resync from head
 1.65.2.2  25-Feb-2013  tls resync with head
 1.65.2.1  20-Nov-2012  tls Resync to 2012-11-19 00:00:00 UTC
 1.80.2.2  18-May-2014  rmind sync with head
 1.80.2.1  28-Aug-2013  rmind sync with head
 1.95.2.1  10-Aug-2014  tls Rebase.
 1.97.2.3  26-Jul-2017  snj Pull up following revision(s) (requested by jmcneill in ticket #1435):
sys/arch/arm/arm32/cpu.c: 1.113 via patch
sys/arch/arm/broadcom/bcm2835_bsc.c: 1.6 via patch
sys/arch/arm/broadcom/bcm2835_plcom.c: 1.4 via patch
sys/arch/arm/cortex/gtmr.c: 1.18 via patch
sys/arch/arm/include/armreg.h: 1.110 via patch
sys/arch/arm/include/vfpreg.h: 1.15 via patch
sys/arch/arm/vfp/vfp_init.c: 1.50 via patch
sys/arch/evbarm/rpi/rpi_machdep.c: 1.59, 1.70-1.72 via patch
sys/arch/evbarm/rpi/vcprop.h: 1.16
Get the RPI3 working (in aarch32 mode) by recognising Cortex A53 CPUs.
While I'm here add some A57/A72 info as well.
My RPI3 works with FB console - the uart needs some help with its clocks.
--
Do invalidate the cache as RPI2 build with Clang can't fetch the memory
config otherwise.
--
Use the VC property mailbox to request the UART clock rate and use it
appropriately
Newer firmwares use 48MHz
--
Disable BSC0 on Raspberry Pi 3 and Zero W boards.
--
Interrupts are enabled before the timer is configured. Ensure that the
timer is disabled when attaching so it doesn't go crazy between the time
interrupts are enabled and clocks are initialized. My RPI3 makes it
multi-user now.
--
Enable UART0 (PL011) on GPIO header for Raspberry Pi 3 / Zero W
 1.97.2.2  08-Dec-2016  snj Pull up following revision(s) (requested by msaitoh in ticket #1287):
sys/arch/arm/include/armreg.h: revision 1.111
Fix CORTEXA9Rx definitions.
 1.97.2.1  09-Nov-2014  martin branches: 1.97.2.1.4;
Pull up following revision(s) (requested by skrll in ticket #188):
sys/arch/arm/include/arm32/pmap.h: revision 1.136
sys/arch/arm/include/armreg.h: revision 1.100
sys/arch/arm/cortex/gic.c: revision 1.11
sys/arch/arm/arm32/db_interface.c: revision 1.54
sys/arch/arm/include/armreg.h: revision 1.101
sys/arch/arm/cortex/gic.c: revision 1.12
sys/arch/arm/arm32/arm32_machdep.c: revision 1.107
sys/arch/arm/arm/cpufunc_asm_armv7.S: revision 1.19
sys/arch/arm/cortex/a9_mpsubr.S: revision 1.20
sys/arch/evbarm/conf/BPI: revision 1.5
sys/arch/arm/cortex/a9_mpsubr.S: revision 1.21
sys/arch/arm/arm32/pmap.c: revision 1.306
sys/arch/arm/arm32/db_machdep.c: revision 1.22
sys/arch/arm/arm32/arm32_tlb.c: revision 1.3
sys/arch/arm/arm/undefined.c: revision 1.55
sys/arch/arm/cortex/a9_mpsubr.S: revision 1.22
sys/arch/arm/arm32/pmap.c: revision 1.307
sys/arch/arm/arm32/arm32_tlb.c: revision 1.4
sys/arch/arm/cortex/a9_mpsubr.S: revision 1.23
sys/arch/arm/arm32/arm32_tlb.c: revision 1.5
sys/arch/evbarm/conf/BPI: revision 1.8
sys/arch/arm/cortex/a9_mpsubr.S: revision 1.24
sys/arch/arm/arm32/arm32_tlb.c: revision 1.6
sys/arch/arm/arm32/arm32_tlb.c: revision 1.7
sys/arch/evbarm/conf/CUBIETRUCK: revision 1.5
sys/arch/arm/pic/pic.c: revision 1.23
sys/arch/arm/pic/pic.c: revision 1.24
sys/arch/arm/pic/picvar.h: revision 1.11
sys/arch/arm/arm/cpufunc_asm_armv7.S: revision 1.20
sys/arch/arm/mainbus/cpu_mainbus.c: revision 1.16
sys/arch/arm/arm32/pmap.c: revision 1.298
sys/arch/arm/arm/cpufunc_asm_arm11.S: revision 1.17
sys/arch/arm/arm/cpufunc_asm_pj4b.S: revision 1.5
sys/arch/arm/arm32/pmap.c: revision 1.310
sys/arch/arm/arm32/pmap.c: revision 1.311
sys/arch/arm/arm32/arm32_kvminit.c: revision 1.32
sys/arch/arm/cortex/a9_mpsubr.S: revision 1.19
sys/arch/arm/arm32/arm32_boot.c: revision 1.10
sys/arch/arm/arm/ast.c: revision 1.25
sys/arch/arm/include/armreg.h: revision 1.98
sys/uvm/pmap/pmap_tlb.c: revision 1.10
sys/arch/arm/arm32/arm32_boot.c: revision 1.8
sys/arch/arm/arm32/arm32_boot.c: revision 1.9
sys/arch/arm/arm/arm_machdep.c: revision 1.43
Various ARM MP fixes.
 1.97.2.1.4.1  18-Jan-2017  skrll Sync with netbsd-5
 1.102.2.5  29-May-2016  skrll Sync with HEAD
 1.102.2.4  19-Mar-2016  skrll Sync with HEAD
 1.102.2.3  27-Dec-2015  skrll Sync with HEAD (as of 26th Dec)
 1.102.2.2  22-Sep-2015  skrll Sync with HEAD
 1.102.2.1  06-Jun-2015  skrll Sync with HEAD
 1.111.14.1  13-Dec-2017  matt Add Cortex-A35 definitions
 1.118.2.5  06-Sep-2018  pgoyette Sync with HEAD

Resolve a couple of conflicts (result of the uimin/uimax changes)
 1.118.2.4  28-Jul-2018  pgoyette Sync with HEAD
 1.118.2.3  21-May-2018  pgoyette Sync with HEAD
 1.118.2.2  07-Apr-2018  pgoyette Sync with HEAD. 77 conflicts resolved - all of them $NetBSD$
 1.118.2.1  22-Mar-2018  pgoyette Synch with HEAD, resolve conflicts
 1.121.2.2  13-Apr-2020  martin Mostly merge changes from HEAD upto 20200411
 1.121.2.1  10-Jun-2019  christos Sync with HEAD
 1.127.2.1  13-Aug-2019  martin Pull up following revision(s) (requested by jmcneill in ticket #54):

sys/arch/aarch64/include/armreg.h: revision 1.26
sys/arch/arm/cortex/gtmr.c: revision 1.41
sys/arch/arm/include/armreg.h: revision 1.128
sys/arch/arm/cortex/gtmr_var.h: revision 1.12

Add support for physical timers and sprinkle isb where needed.
 1.129.8.1  03-Apr-2021  thorpej Sync with HEAD.

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