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      1 /*	$NetBSD: reg.h,v 1.2 2021/12/18 23:45:31 riastradh Exp $	*/
      2 
      3 /*
      4  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice (including the next
     14  * paragraph) shall be included in all copies or substantial portions of the
     15  * Software.
     16  *
     17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
     21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
     22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
     23  * SOFTWARE.
     24  */
     25 
     26 #ifndef _GVT_REG_H
     27 #define _GVT_REG_H
     28 
     29 #define INTEL_GVT_PCI_CLASS_VGA_OTHER   0x80
     30 
     31 #define INTEL_GVT_PCI_GMCH_CONTROL	0x50
     32 #define   BDW_GMCH_GMS_SHIFT		8
     33 #define   BDW_GMCH_GMS_MASK		0xff
     34 
     35 #define INTEL_GVT_PCI_SWSCI		0xe8
     36 #define   SWSCI_SCI_SELECT		(1 << 15)
     37 #define   SWSCI_SCI_TRIGGER		1
     38 
     39 #define INTEL_GVT_PCI_OPREGION		0xfc
     40 
     41 #define INTEL_GVT_OPREGION_CLID		0x1AC
     42 #define INTEL_GVT_OPREGION_SCIC		0x200
     43 #define   OPREGION_SCIC_FUNC_MASK	0x1E
     44 #define   OPREGION_SCIC_FUNC_SHIFT	1
     45 #define   OPREGION_SCIC_SUBFUNC_MASK	0xFF00
     46 #define   OPREGION_SCIC_SUBFUNC_SHIFT	8
     47 #define   OPREGION_SCIC_EXIT_MASK	0xE0
     48 #define INTEL_GVT_OPREGION_SCIC_F_GETBIOSDATA         4
     49 #define INTEL_GVT_OPREGION_SCIC_F_GETBIOSCALLBACKS    6
     50 #define INTEL_GVT_OPREGION_SCIC_SF_SUPPRTEDCALLS      0
     51 #define INTEL_GVT_OPREGION_SCIC_SF_REQEUSTEDCALLBACKS 1
     52 #define INTEL_GVT_OPREGION_PARM                   0x204
     53 
     54 #define INTEL_GVT_OPREGION_PAGES	2
     55 #define INTEL_GVT_OPREGION_SIZE		(INTEL_GVT_OPREGION_PAGES * PAGE_SIZE)
     56 #define INTEL_GVT_OPREGION_VBT_OFFSET	0x400
     57 #define INTEL_GVT_OPREGION_VBT_SIZE	\
     58 		(INTEL_GVT_OPREGION_SIZE - INTEL_GVT_OPREGION_VBT_OFFSET)
     59 
     60 #define VGT_SPRSTRIDE(pipe)	_PIPE(pipe, _SPRA_STRIDE, _PLANE_STRIDE_2_B)
     61 
     62 #define _REG_701C0(pipe, plane) (0x701c0 + pipe * 0x1000 + (plane - 1) * 0x100)
     63 #define _REG_701C4(pipe, plane) (0x701c4 + pipe * 0x1000 + (plane - 1) * 0x100)
     64 
     65 #define SKL_FLIP_EVENT(pipe, plane) (PRIMARY_A_FLIP_DONE + (plane) * 3 + (pipe))
     66 
     67 #define PLANE_CTL_ASYNC_FLIP		(1 << 9)
     68 #define REG50080_FLIP_TYPE_MASK	0x3
     69 #define REG50080_FLIP_TYPE_ASYNC	0x1
     70 
     71 #define REG_50080(_pipe, _plane) ({ \
     72 	typeof(_pipe) (p) = (_pipe); \
     73 	typeof(_plane) (q) = (_plane); \
     74 	(((p) == PIPE_A) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50080)) : \
     75 		(_MMIO(0x50090))) : \
     76 	(((p) == PIPE_B) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50088)) : \
     77 		(_MMIO(0x50098))) : \
     78 	(((p) == PIPE_C) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x5008C)) : \
     79 		(_MMIO(0x5009C))) : \
     80 		(_MMIO(0x50080))))); })
     81 
     82 #define REG_50080_TO_PIPE(_reg) ({ \
     83 	typeof(_reg) (reg) = (_reg); \
     84 	(((reg) == 0x50080 || (reg) == 0x50090) ? (PIPE_A) : \
     85 	(((reg) == 0x50088 || (reg) == 0x50098) ? (PIPE_B) : \
     86 	(((reg) == 0x5008C || (reg) == 0x5009C) ? (PIPE_C) : \
     87 	(INVALID_PIPE)))); })
     88 
     89 #define REG_50080_TO_PLANE(_reg) ({ \
     90 	typeof(_reg) (reg) = (_reg); \
     91 	(((reg) == 0x50080 || (reg) == 0x50088 || (reg) == 0x5008C) ? \
     92 		(PLANE_PRIMARY) : \
     93 	(((reg) == 0x50090 || (reg) == 0x50098 || (reg) == 0x5009C) ? \
     94 		(PLANE_SPRITE0) : (I915_MAX_PLANES))); })
     95 
     96 #define GFX_MODE_BIT_SET_IN_MASK(val, bit) \
     97 		((((bit) & 0xffff0000) == 0) && !!((val) & (((bit) << 16))))
     98 
     99 #define FORCEWAKE_RENDER_GEN9_REG 0xa278
    100 #define FORCEWAKE_ACK_RENDER_GEN9_REG 0x0D84
    101 #define FORCEWAKE_BLITTER_GEN9_REG 0xa188
    102 #define FORCEWAKE_ACK_BLITTER_GEN9_REG 0x130044
    103 #define FORCEWAKE_MEDIA_GEN9_REG 0xa270
    104 #define FORCEWAKE_ACK_MEDIA_GEN9_REG 0x0D88
    105 #define FORCEWAKE_ACK_HSW_REG 0x130044
    106 
    107 #define RB_HEAD_WRAP_CNT_MAX	((1 << 11) - 1)
    108 #define RB_HEAD_WRAP_CNT_OFF	21
    109 #define RB_HEAD_OFF_MASK	((1U << 21) - (1U << 2))
    110 #define RB_TAIL_OFF_MASK	((1U << 21) - (1U << 3))
    111 #define RB_TAIL_SIZE_MASK	((1U << 21) - (1U << 12))
    112 #define _RING_CTL_BUF_SIZE(ctl) (((ctl) & RB_TAIL_SIZE_MASK) + \
    113 		I915_GTT_PAGE_SIZE)
    114 
    115 #define PCH_GPIO_BASE	_MMIO(0xc5010)
    116 
    117 #define PCH_GMBUS0	_MMIO(0xc5100)
    118 #define PCH_GMBUS1	_MMIO(0xc5104)
    119 #define PCH_GMBUS2	_MMIO(0xc5108)
    120 #define PCH_GMBUS3	_MMIO(0xc510c)
    121 #define PCH_GMBUS4	_MMIO(0xc5110)
    122 #define PCH_GMBUS5	_MMIO(0xc5120)
    123 
    124 #define TRVATTL3PTRDW(i)	_MMIO(0x4de0 + (i) * 4)
    125 #define TRNULLDETCT		_MMIO(0x4de8)
    126 #define TRINVTILEDETCT		_MMIO(0x4dec)
    127 #define TRVADR			_MMIO(0x4df0)
    128 #define TRTTE			_MMIO(0x4df4)
    129 #define RING_EXCC(base)		_MMIO((base) + 0x28)
    130 #define RING_GFX_MODE(base)	_MMIO((base) + 0x29c)
    131 #define VF_GUARDBAND		_MMIO(0x83a4)
    132 
    133 #endif
    134