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    Searched defs:IR (Results 1 - 17 of 17) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/MCA/Stages/
MicroOpQueueStage.cpp 22 InstRef IR = Buffer[CurrentInstructionSlotIdx];
23 while (IR && checkNextStage(IR)) {
24 if (llvm::Error Val = moveToTheNextStage(IR))
28 unsigned NormalizedOpcodes = getNormalizedOpcodes(IR);
32 IR = Buffer[CurrentInstructionSlotIdx];
46 Error MicroOpQueueStage::execute(InstRef &IR) {
47 Buffer[NextAvailableSlotIdx] = IR;
48 unsigned NormalizedOpcodes = getNormalizedOpcodes(IR);
ExecuteStage.cpp 43 bool ExecuteStage::isAvailable(const InstRef &IR) const {
44 if (Scheduler::Status S = HWS.isAvailable(IR)) {
46 notifyEvent<HWStallEvent>(HWStallEvent(ET, IR));
53 Error ExecuteStage::issueInstruction(InstRef &IR) {
58 HWS.issueInstruction(IR, Used, Pending, Ready);
59 Instruction &IS = *IR.getInstruction();
62 notifyReservedOrReleasedBuffers(IR, /* Reserved */ false);
64 notifyInstructionIssued(IR, Used);
66 notifyInstructionExecuted(IR);
68 if (Error S = moveToTheNextStage(IR))
    [all...]
  /src/sys/arch/alpha/pci/
pci_1000.c 171 #define IR() bus_space_read_2(another_mystery_icu_iot, \
184 IW(IR() | 1 << irq);
190 IW(IR() & ~(1 << irq));
pci_1000a.c 189 #define IR(h) bus_space_read_2(mystery_icu_iot, mystery_icu_ioh[h], 0)
202 IW(i, IR(i) | 1 << (imrval & 0xf));
211 IW(i, IR(i) & ~(1 << (imrval & 0xf)));
220 IW(0, IR(0) & 1);
221 IW(1, IR(0) & 3);
  /src/external/apache2/llvm/dist/llvm/lib/MCA/
Pipeline.cpp 60 InstRef IR;
62 while (!Err && FirstStage.isAvailable(IR))
63 Err = FirstStage.execute(IR);
  /src/external/apache2/llvm/dist/llvm/include/llvm/MCA/HardwareUnits/
RetireControlUnit.h 52 InstRef IR;
  /src/external/apache2/llvm/dist/clang/lib/AST/
ComputeDependence.cpp 422 OMPIteratorExpr::IteratorRange IR = E->getIteratorRange(I);
423 if (Expr *BE = IR.Begin)
425 if (Expr *EE = IR.End)
427 if (Expr *SE = IR.Step)
  /src/external/apache2/llvm/dist/llvm/lib/MCA/HardwareUnits/
Scheduler.cpp 40 Scheduler::Status Scheduler::isAvailable(const InstRef &IR) {
42 Resources->canBeDispatched(IR.getInstruction()->getUsedBuffers());
55 LSUnit::Status LSS = LSU.isAvailable(IR);
71 InstRef &IR,
73 Instruction *IS = IR.getInstruction();
82 IS->execute(IR.getSourceIndex());
87 LSU.onInstructionIssued(IR);
93 IssuedSet.emplace_back(IR);
95 LSU.onInstructionExecuted(IR);
100 InstRef &IR,
    [all...]
  /src/external/gpl3/gdb.old/dist/sim/mips/
cp1.h 67 #define IR 0 /* I: Inexact Result */
  /src/external/gpl3/gdb/dist/sim/mips/
cp1.h 67 #define IR 0 /* I: Inexact Result */
  /src/external/apache2/llvm/dist/llvm/include/llvm/MCA/
HWEventListener.h 53 : Type(type), IR(Inst) {}
59 const InstRef &IR;
65 HWInstructionIssuedEvent(const InstRef &IR,
67 : HWInstructionEvent(HWInstructionEvent::Issued, IR), UsedResources(UR) {}
74 HWInstructionDispatchedEvent(const InstRef &IR, ArrayRef<unsigned> Regs,
76 : HWInstructionEvent(HWInstructionEvent::Dispatched, IR),
83 // the instruction descriptor of IR.
84 // The only exception is when IR declares a number of micro opcodes
95 HWInstructionRetiredEvent(const InstRef &IR, ArrayRef<unsigned> Regs)
96 : HWInstructionEvent(HWInstructionEvent::Retired, IR),
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/IPO/
Inliner.cpp 40 #include "llvm/IR/Attributes.h"
41 #include "llvm/IR/BasicBlock.h"
42 #include "llvm/IR/DataLayout.h"
43 #include "llvm/IR/DebugLoc.h"
44 #include "llvm/IR/DerivedTypes.h"
45 #include "llvm/IR/DiagnosticInfo.h"
46 #include "llvm/IR/Function.h"
47 #include "llvm/IR/InstIterator.h"
48 #include "llvm/IR/Instruction.h"
49 #include "llvm/IR/Instructions.h
    [all...]
  /src/external/apache2/llvm/dist/llvm/tools/llvm-lipo/
llvm-lipo.cpp 16 #include "llvm/IR/LLVMContext.h"
17 #include "llvm/IR/Module.h"
428 const auto *IR = cast<IRObjectFile>(Binary);
429 Expected<Slice> SliceOrErr = createSliceFromIR(*IR, 0);
431 reportError(IR->getFileName(), SliceOrErr.takeError());
  /src/external/apache2/llvm/dist/clang/lib/Basic/
SourceManager.cpp 544 SrcMgr::ContentCache &IR = getOrCreateContentCache(SourceFile,
549 if (IR.ContentsEntry->isNamedPipe())
550 (void)IR.getBufferOrNone(Diag, getFileManager(), SourceLocation());
552 return createFileIDImpl(IR, SourceFile.getName(), IncludePos, FileCharacter,
684 SrcMgr::ContentCache &IR = getOrCreateContentCache(File->getLastRef());
685 return IR.getBufferOrNone(Diag, getFileManager(), SourceLocation());
690 SrcMgr::ContentCache &IR = getOrCreateContentCache(SourceFile->getLastRef());
692 IR.setBuffer(std::move(Buffer));
693 IR.BufferOverridden = true;
  /src/external/apache2/llvm/dist/llvm/lib/Analysis/
InlineCost.cpp 31 #include "llvm/IR/AssemblyAnnotationWriter.h"
32 #include "llvm/IR/CallingConv.h"
33 #include "llvm/IR/DataLayout.h"
34 #include "llvm/IR/Dominators.h"
35 #include "llvm/IR/GetElementPtrTypeIterator.h"
36 #include "llvm/IR/GlobalAlias.h"
37 #include "llvm/IR/InstVisitor.h"
38 #include "llvm/IR/IntrinsicInst.h"
39 #include "llvm/IR/Operator.h"
40 #include "llvm/IR/PatternMatch.h
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonFrameLowering.cpp 42 #include "llvm/IR/Attributes.h"
43 #include "llvm/IR/DebugLoc.h"
44 #include "llvm/IR/Function.h"
2404 HexagonBlockRanges::IndexRange &IR = F->second.front();
2405 if (IR.start() == IndexType::Entry)
  /src/external/cddl/osnet/dev/dtrace/x86/
dis_tables.c 102 IR,
2228 /* [B,0] */ TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), TNS("movb",IR),
2229 /* [B,4] */ TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), TNS("movb",IR),
2230 /* [B,8] */ TS("mov",IR), TS("mov",IR), TS("mov",IR), TS("mov",IR)
    [all...]

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