1 /* $NetBSD: irongatereg.h,v 1.3 2008/04/28 20:23:11 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Register definitions for the AMD 751 (``Irongate'') core logic 34 * chipset. 35 */ 36 37 /* 38 * Address map. 39 * 40 * This from the Tsunami address map: 41 * EV6 has a new superpage which can pass through 44 address bits. (Umm, a 42 * superduperpage?) But, the firmware doesn't turn it on, so we use the old 43 * one and let the HW sign extend va/pa<40> to get us the pa<43> that makes 44 * the needed I/O space access. This is just as well; it means we don't have 45 * to worry about which GENERIC code might get called on other CPU models. 46 * 47 * E.g., we want this: 0x0801##fc00##0000 48 * We use this: 0x0101##fc00##0000 49 * ...mix in the old SP: 0xffff##fc00##0000##0000 50 * ...after PA sign ext: 0xffff##ff01##fc00##0000 51 * (PA<42:41> ignored) 52 * 53 * PCI memory and RAM: 0000.0000.0000 54 * IACK 0001.f800.0000 55 * PCI I/O: 0001.fc00.0000 56 * AMD 751 (also in PCI config space): 0001.fe00.0000 57 */ 58 59 /* 60 * This hack allows us to map the I/O address space without using 61 * the KSEG sign extension hack. 62 */ 63 #define IRONGATE_PHYSADDR(x) \ 64 (((x) & ~0x0100##0000##0000) | 0x0800##0000##0000) 65 66 #define IRONGATE_KSEG_BIAS 0x0100##0000##0000UL 67 68 #define IRONGATE_MEM_BASE (IRONGATE_KSEG_BIAS | 0x0000##0000##0000UL) 69 #define IRONGATE_IACK_BASE (IRONGATE_KSEG_BIAS | 0x0001##f800##0000UL) 70 #define IRONGATE_IO_BASE (IRONGATE_KSEG_BIAS | 0x0001##fc00##0000UL) 71 #define IRONGATE_SELF_BASE (IRONGATE_KSEG_BIAS | 0x0001##fe00##0000UL) 72 73 /* 74 * PCI configuration register access using done by using 75 * ``configuration mode 1'' (in PC lingo), using the I/O 76 * space addresses described in the PCI Local Bus Specification 77 * Revision 2.2. 78 */ 79 #define IRONGATE_CONFADDR 0x0cf8 80 #define IRONGATE_CONFDATA 0x0cfc 81 82 #define CONFADDR_ENABLE 0x80000000U 83 84 /* 85 * The AMD 751 PCI-Host bridge is located at device 0, and the 86 * AGP controller (seen as a PCI-PCI bridge) is at device 1. 87 */ 88 #define IRONGATE_PCIHOST_DEV 0 89 #define IRONGATE_PCIAGP_DEV 1 90
Indexes created Sun Sep 21 16:09:51 GMT 2025