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    Searched defs:MII_BMCR (Results 1 - 12 of 12) sorted by relevancy

  /src/sys/arch/evbarm/stand/boot2440/
dm9000.c 415 #define MII_BMCR 0x00 /* Basic mode control register (rw) */
439 mii_write(l, l->phy, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG);
  /src/sys/arch/sandpoint/stand/altboot/
pcn.c 338 #define MII_BMCR 0x00 /* Basic mode control register (rw) */
351 ctl = pcn_mii_read(l, phy, MII_BMCR);
359 ctl = pcn_mii_read(l, phy, MII_BMCR);
360 pcn_mii_write(l, phy, MII_BMCR, ctl | BMCR_RESET);
364 ctl = pcn_mii_read(l, phy, MII_BMCR);
374 pcn_mii_write(l, phy, MII_BMCR, ctl);
389 pcn_mii_write(l, l->phy, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG);
sip.c 338 #define MII_BMCR 0x00 /* Basic mode control register (rw) */
379 ctl = mii_read(l, phy, MII_BMCR);
387 ctl = mii_read(l, phy, MII_BMCR);
388 mii_write(l, phy, MII_BMCR, ctl | BMCR_RESET);
392 ctl = mii_read(l, phy, MII_BMCR);
402 mii_write(l, phy, MII_BMCR, ctl);
416 mii_write(l, l->phy, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG);
sme.c 258 #define MII_BMCR 0x00 /* Basic mode control register (rw) */
310 mii_write(l, l->phy, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG);
tlp.c 354 #define MII_BMCR 0x00 /* Basic mode control register (rw) */
377 ctl = mii_read(l, phy, MII_BMCR);
385 ctl = mii_read(l, phy, MII_BMCR);
386 mii_write(l, phy, MII_BMCR, ctl | BMCR_RESET);
390 ctl = mii_read(l, phy, MII_BMCR);
400 mii_write(l, phy, MII_BMCR, ctl);
414 mii_write(l, l->phy, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG);
wm.c 378 #define MII_BMCR 0x00 /* Basic mode control register (rw) */
408 ctl = mii_read(l, phy, MII_BMCR);
416 ctl = mii_read(l, phy, MII_BMCR);
417 mii_write(l, phy, MII_BMCR, ctl | BMCR_RESET);
421 ctl = mii_read(l, phy, MII_BMCR);
431 mii_write(l, phy, MII_BMCR, ctl);
448 mii_write(l, l->phy, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG);
nvt.c 376 #define MII_BMCR 0x00 /* Basic mode control register (rw) */
400 mii_write(l, l->phy, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG);
rge.c 342 #define MII_BMCR 0x00 /* Basic mode control register (rw) */
372 ctl = mii_read(l, phy, MII_BMCR);
373 mii_write(l, phy, MII_BMCR, ctl | BMCR_RESET);
377 ctl = mii_read(l, phy, MII_BMCR);
387 mii_write(l, phy, MII_BMCR, ctl);
404 mii_write(l, l->phy, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG);
stg.c 423 #define MII_BMCR 0x00 /* Basic mode control register (rw) */
449 ctl = mii_read(l, phy, MII_BMCR);
458 ctl = mii_read(l, phy, MII_BMCR);
459 mii_write(l, phy, MII_BMCR, ctl | BMCR_RESET);
464 ctl = mii_read(l, phy, MII_BMCR);
474 mii_write(l, phy, MII_BMCR, ctl);
488 mii_write(l, l->phy, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG);
skg.c 434 #define MII_BMCR 0x00 /* Basic mode control register (rw) */
491 mii_write(l, l->phy, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG);
vge.c 458 #define MII_BMCR 0x00 /* Basic mode control register (rw) */
492 mii_write(l, l->phy, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG);
  /src/sys/dev/mii/
mii.h 50 #define MII_BMCR 0x00 /* Basic mode control register (rw) */

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