1 /* $NetBSD: miidevs.h,v 1.172 2024/10/23 05:46:51 skrll Exp $ */ 2 3 /* 4 * THIS FILE IS AUTOMATICALLY GENERATED. DO NOT EDIT. 5 * 6 * generated from: 7 * NetBSD: miidevs,v 1.174 2024/10/23 05:44:10 skrll Exp 8 */ 9 10 /*- 11 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 12 * All rights reserved. 13 * 14 * This code is derived from software contributed to The NetBSD Foundation 15 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 16 * NASA Ames Research Center. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions 20 * are met: 21 * 1. Redistributions of source code must retain the above copyright 22 * notice, this list of conditions and the following disclaimer. 23 * 2. Redistributions in binary form must reproduce the above copyright 24 * notice, this list of conditions and the following disclaimer in the 25 * documentation and/or other materials provided with the distribution. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * List of known MII OUIs. 42 * For a complete list see http://standards.ieee.org/regauth/oui/ 43 * 44 * XXX Vendors do obviously not agree how OUIs (24 bit) are mapped 45 * to the 22 bits available in the id registers. 46 * IEEE 802.3u-1995, subclause 22.2.4.3.1, figure 22-12, depicts the right 47 * mapping; the bit positions are defined in IEEE 802-1990, figure 5.2. 48 * (There is a formal 802.3 interpretation, number 1-07/98 of July 09 1998, 49 * about this.) 50 * The MII_OUI() macro in "miivar.h" reflects this. 51 * If a vendor uses a different mapping, an "xx" prefixed OUI is defined here 52 * which is mangled accordingly to compensate. 53 */ 54 55 /* 56 * Use "make -f Makefile.miidevs" to regenerate miidevs.h and miidevs_data.h 57 */ 58 59 #define MII_OUI_AMD 0x00001a /* Advanced Micro Devices */ 60 #define MII_OUI_TRIDIUM 0x0001f0 /* Tridium */ 61 #define MII_OUI_DATATRACK 0x0002c6 /* Data Track Technology */ 62 #define MII_OUI_AGERE 0x00053d /* Agere */ 63 #define MII_OUI_QUAKE 0x000897 /* Quake Technologies */ 64 #define MII_OUI_BANKSPEED 0x0006b8 /* Bankspeed Pty */ 65 #define MII_OUI_NETEXCELL 0x0008bb /* NetExcell */ 66 #define MII_OUI_NETAS 0x0009c3 /* Netas */ 67 #define MII_OUI_BROADCOM2 0x000af7 /* Broadcom Corporation */ 68 #define MII_OUI_AELUROS 0x000b25 /* Aeluros */ 69 #define MII_OUI_RALINK 0x000c43 /* Ralink Technology */ 70 #define MII_OUI_ASIX 0x000ec6 /* ASIX */ 71 #define MII_OUI_BROADCOM 0x001018 /* Broadcom Corporation */ 72 #define MII_OUI_MICREL 0x0010a1 /* Micrel */ 73 #define MII_OUI_ALTIMA 0x0010a9 /* Altima Communications */ 74 #define MII_OUI_ENABLESEMI 0x0010dd /* Enable Semiconductor */ 75 #define MII_OUI_SUNPLUS 0x001105 /* Sunplus Technology */ 76 #define MII_OUI_TERANETICS 0x0014a6 /* Teranetics */ 77 #define MII_OUI_RALINK2 0x0017a5 /* Ralink Technology */ 78 #define MII_OUI_AQUANTIA 0x0017b6 /* Aquantia Corporation */ 79 #define MII_OUI_BROADCOM3 0x001be9 /* Broadcom Corporation */ 80 #define MII_OUI_LEVEL1 0x00207b /* Level 1 */ 81 #define MII_OUI_MARVELL 0x005043 /* Marvell Semiconductor */ 82 #define MII_OUI_QUALSEMI 0x006051 /* Quality Semiconductor */ 83 #define MII_OUI_AMLOGIC 0x006051 /* Amlogic */ 84 #define MII_OUI_DAVICOM 0x00606e /* Davicom Semiconductor */ 85 #define MII_OUI_SMSC 0x00800f /* SMSC */ 86 #define MII_OUI_SEEQ 0x00a07d /* Seeq */ 87 #define MII_OUI_ICS 0x00a0be /* Integrated Circuit Systems */ 88 #define MII_OUI_INTEL 0x00aa00 /* Intel */ 89 #define MII_OUI_TSC 0x00c039 /* TDK Semiconductor */ 90 #define MII_OUI_MYSON 0x00c0b4 /* Myson Technology */ 91 #define MII_OUI_ATTANSIC 0x00c82e /* Attansic Technology */ 92 #define MII_OUI_JMICRON 0x00d831 /* JMicron */ 93 #define MII_OUI_PMCSIERRA 0x00e004 /* PMC-Sierra */ 94 #define MII_OUI_SIS 0x00e006 /* Silicon Integrated Systems */ 95 #define MII_OUI_REALTEK 0x00e04c /* RealTek */ 96 #define MII_OUI_ADMTEK 0x00e092 /* ADMtek */ 97 #define MII_OUI_XAQTI 0x00e0ae /* XaQti Corp. */ 98 #define MII_OUI_NATSEMI 0x080017 /* National Semiconductor */ 99 #define MII_OUI_TI 0x080028 /* Texas Instruments */ 100 #define MII_OUI_BROADCOM4 0x18c086 /* Broadcom Corporation */ 101 #define MII_OUI_RENESAS 0x749050 /* Renesas */ 102 #define MII_OUI_INTEL2 0x984fee /* Intel */ 103 #define MII_OUI_MAXLINEAR 0xac9a96 /* MaxLinear */ 104 #define MII_OUI_MOTORCOMM 0xc82b5e /* Motorcomm */ 105 106 /* Unregistered or wrong OUI */ 107 #define MII_OUI_yyREALTEK 0x000004 /* Realtek */ 108 #define MII_OUI_yyAMD 0x000058 /* Advanced Micro Devices */ 109 #define MII_OUI_xxVIA 0x0002c6 /* VIA Technologies */ 110 #define MII_OUI_xxMYSON 0x00032d /* Myson Technology */ 111 #define MII_OUI_xxTSC 0x00039c /* TDK Semiconductor */ 112 #define MII_OUI_xxASIX 0x000674 /* Asix Semiconductor */ 113 #define MII_OUI_xxDAVICOM 0x000676 /* Davicom Semiconductor */ 114 #define MII_OUI_xxAMLOGIC 0x00068a /* Amlogic */ 115 #define MII_OUI_xxQUALSEMI 0x00068a /* Quality Semiconductor */ 116 #define MII_OUI_xxREALTEK 0x000732 /* Realtek */ 117 #define MII_OUI_xxADMTEK 0x000749 /* ADMTek */ 118 #define MII_OUI_xxBROADCOM 0x000818 /* Broadcom Corporation */ 119 #define MII_OUI_xxPMCSIERRA 0x0009c0 /* PMC-Sierra */ 120 #define MII_OUI_xxICPLUS 0x0009c3 /* IC Plus Corp. */ 121 #define MII_OUI_xxMARVELL 0x000ac2 /* Marvell Semiconductor */ 122 #define MII_OUI_xxINTEL 0x001f00 /* Intel */ 123 #define MII_OUI_xxBROADCOM_ALT1 0x0050ef /* Broadcom Corporation */ 124 #define MII_OUI_yyINTEL 0x005500 /* Intel */ 125 #define MII_OUI_yyASIX 0x007063 /* Asix Semiconductor */ 126 #define MII_OUI_xxVITESSE 0x008083 /* Vitesse Semiconductor */ 127 #define MII_OUI_xxPMCSIERRA2 0x009057 /* PMC-Sierra */ 128 #define MII_OUI_xxCICADA 0x00c08f /* Cicada Semiconductor */ 129 #define MII_OUI_xxRDC 0x00d02d /* RDC Semiconductor */ 130 #define MII_OUI_xxMAXLINEAR 0x0c32ab /* MaxLinear */ 131 #define MII_OUI_xxNATSEMI 0x1000e8 /* National Semiconductor */ 132 #define MII_OUI_xxLEVEL1 0x782000 /* Level 1 */ 133 #define MII_OUI_xxXAQTI 0xace000 /* XaQti Corp. */ 134 135 /* 136 * List of known models. Grouped by oui. 137 */ 138 139 /* 140 * Agere PHYs 141 */ 142 #define MII_MODEL_AGERE_ET1011 0x0001 /* ET1011 10/100/1000baseT PHY */ 143 #define MII_STR_AGERE_ET1011 "ET1011 10/100/1000baseT PHY" 144 #define MII_MODEL_AGERE_ET1011C 0x0004 /* ET1011C 10/100/1000baseT PHY */ 145 #define MII_STR_AGERE_ET1011C "ET1011C 10/100/1000baseT PHY" 146 147 /* Asix semiconductor PHYs */ 148 #define MII_MODEL_xxASIX_AX88X9X 0x0031 /* Ax88x9x internal PHY */ 149 #define MII_STR_xxASIX_AX88X9X "Ax88x9x internal PHY" 150 #define MII_MODEL_yyASIX_AX88772 0x0001 /* AX88772 internal PHY */ 151 #define MII_STR_yyASIX_AX88772 "AX88772 internal PHY" 152 #define MII_MODEL_yyASIX_AX88772A 0x0006 /* AX88772A internal PHY */ 153 #define MII_STR_yyASIX_AX88772A "AX88772A internal PHY" 154 #define MII_MODEL_yyASIX_AX88772B 0x0008 /* AX88772B internal PHY */ 155 #define MII_STR_yyASIX_AX88772B "AX88772B internal PHY" 156 157 /* Altima Communications PHYs */ 158 /* Don't know the model for ACXXX */ 159 #define MII_MODEL_ALTIMA_ACXXX 0x0001 /* ACXXX 10/100 media interface */ 160 #define MII_STR_ALTIMA_ACXXX "ACXXX 10/100 media interface" 161 #define MII_MODEL_ALTIMA_AC101L 0x0012 /* AC101L 10/100 media interface */ 162 #define MII_STR_ALTIMA_AC101L "AC101L 10/100 media interface" 163 #define MII_MODEL_ALTIMA_AC101 0x0021 /* AC101 10/100 media interface */ 164 #define MII_STR_ALTIMA_AC101 "AC101 10/100 media interface" 165 /* AMD Am79C87[45] have ALTIMA OUI */ 166 #define MII_MODEL_ALTIMA_Am79C875 0x0014 /* Am79C875 10/100 media interface */ 167 #define MII_STR_ALTIMA_Am79C875 "Am79C875 10/100 media interface" 168 #define MII_MODEL_ALTIMA_Am79C874 0x0021 /* Am79C874 10/100 media interface */ 169 #define MII_STR_ALTIMA_Am79C874 "Am79C874 10/100 media interface" 170 171 /* Amlogic PHYs */ 172 #define MII_MODEL_AMLOGIC_GXL 0x0000 /* Meson GXL internal PHY */ 173 #define MII_STR_AMLOGIC_GXL "Meson GXL internal PHY" 174 #define MII_MODEL_xxAMLOGIC_GXL 0x0000 /* Meson GXL internal PHY */ 175 #define MII_STR_xxAMLOGIC_GXL "Meson GXL internal PHY" 176 177 /* Attansic/Atheros PHYs */ 178 #define MII_MODEL_ATTANSIC_L1 0x0001 /* L1 10/100/1000 PHY */ 179 #define MII_STR_ATTANSIC_L1 "L1 10/100/1000 PHY" 180 #define MII_MODEL_ATTANSIC_L2 0x0002 /* L2 10/100 PHY */ 181 #define MII_STR_ATTANSIC_L2 "L2 10/100 PHY" 182 #define MII_MODEL_ATTANSIC_AR8021 0x0004 /* Atheros AR8021 10/100/1000 PHY */ 183 #define MII_STR_ATTANSIC_AR8021 "Atheros AR8021 10/100/1000 PHY" 184 #define MII_MODEL_ATTANSIC_AR8035 0x0007 /* Atheros AR8035 10/100/1000 PHY */ 185 #define MII_STR_ATTANSIC_AR8035 "Atheros AR8035 10/100/1000 PHY" 186 187 /* Advanced Micro Devices PHYs */ 188 /* see Davicom DM9101 for Am79C873 */ 189 #define MII_MODEL_yyAMD_79C972_10T 0x0001 /* Am79C972 internal 10BASE-T interface */ 190 #define MII_STR_yyAMD_79C972_10T "Am79C972 internal 10BASE-T interface" 191 #define MII_MODEL_yyAMD_79c973phy 0x0036 /* Am79C973 internal 10/100 media interface */ 192 #define MII_STR_yyAMD_79c973phy "Am79C973 internal 10/100 media interface" 193 #define MII_MODEL_yyAMD_79c901 0x0037 /* Am79C901 10BASE-T interface */ 194 #define MII_STR_yyAMD_79c901 "Am79C901 10BASE-T interface" 195 #define MII_MODEL_yyAMD_79c901home 0x0039 /* Am79C901 HomePNA 1.0 interface */ 196 #define MII_STR_yyAMD_79c901home "Am79C901 HomePNA 1.0 interface" 197 198 /* Broadcom Corp. PHYs */ 199 #define MII_MODEL_xxBROADCOM_3C905B 0x0012 /* Broadcom 3c905B internal PHY */ 200 #define MII_STR_xxBROADCOM_3C905B "Broadcom 3c905B internal PHY" 201 #define MII_MODEL_xxBROADCOM_3C905C 0x0017 /* Broadcom 3c905C internal PHY */ 202 #define MII_STR_xxBROADCOM_3C905C "Broadcom 3c905C internal PHY" 203 #define MII_MODEL_xxBROADCOM_BCM5221 0x001e /* BCM5221 10/100 media interface */ 204 #define MII_STR_xxBROADCOM_BCM5221 "BCM5221 10/100 media interface" 205 #define MII_MODEL_xxBROADCOM_BCM5201 0x0021 /* BCM5201 10/100 media interface */ 206 #define MII_STR_xxBROADCOM_BCM5201 "BCM5201 10/100 media interface" 207 #define MII_MODEL_xxBROADCOM_BCM5214 0x0028 /* BCM5214 Quad 10/100 media interface */ 208 #define MII_STR_xxBROADCOM_BCM5214 "BCM5214 Quad 10/100 media interface" 209 #define MII_MODEL_xxBROADCOM_BCM5222 0x0032 /* BCM5222 Dual 10/100 media interface */ 210 #define MII_STR_xxBROADCOM_BCM5222 "BCM5222 Dual 10/100 media interface" 211 #define MII_MODEL_xxBROADCOM_BCM4401 0x0036 /* BCM4401 10/100 media interface */ 212 #define MII_STR_xxBROADCOM_BCM4401 "BCM4401 10/100 media interface" 213 #define MII_MODEL_xxBROADCOM_BCM5365 0x0037 /* BCM5365 10/100 5-port PHY switch */ 214 #define MII_STR_xxBROADCOM_BCM5365 "BCM5365 10/100 5-port PHY switch" 215 #define MII_MODEL_BROADCOM_BCM5400 0x0004 /* BCM5400 1000BASE-T media interface */ 216 #define MII_STR_BROADCOM_BCM5400 "BCM5400 1000BASE-T media interface" 217 #define MII_MODEL_BROADCOM_BCM5401 0x0005 /* BCM5401 1000BASE-T media interface */ 218 #define MII_STR_BROADCOM_BCM5401 "BCM5401 1000BASE-T media interface" 219 #define MII_MODEL_BROADCOM_BCM5402 0x0006 /* BCM5402 1000BASE-T media interface */ 220 #define MII_STR_BROADCOM_BCM5402 "BCM5402 1000BASE-T media interface" 221 #define MII_MODEL_BROADCOM_BCM5411 0x0007 /* BCM5411 1000BASE-T media interface */ 222 #define MII_STR_BROADCOM_BCM5411 "BCM5411 1000BASE-T media interface" 223 #define MII_MODEL_BROADCOM_BCM5404 0x0008 /* BCM5404 1000BASE-T media interface */ 224 #define MII_STR_BROADCOM_BCM5404 "BCM5404 1000BASE-T media interface" 225 #define MII_MODEL_BROADCOM_BCM5424 0x000a /* BCM5424/BCM5234 1000BASE-T media interface */ 226 #define MII_STR_BROADCOM_BCM5424 "BCM5424/BCM5234 1000BASE-T media interface" 227 #define MII_MODEL_BROADCOM_BCM5464 0x000b /* BCM5464 1000BASE-T media interface */ 228 #define MII_STR_BROADCOM_BCM5464 "BCM5464 1000BASE-T media interface" 229 #define MII_MODEL_BROADCOM_BCM5461 0x000c /* BCM5461 1000BASE-T media interface */ 230 #define MII_STR_BROADCOM_BCM5461 "BCM5461 1000BASE-T media interface" 231 #define MII_MODEL_BROADCOM_BCM5462 0x000d /* BCM5462 1000BASE-T media interface */ 232 #define MII_STR_BROADCOM_BCM5462 "BCM5462 1000BASE-T media interface" 233 #define MII_MODEL_BROADCOM_BCM5421 0x000e /* BCM5421 1000BASE-T media interface */ 234 #define MII_STR_BROADCOM_BCM5421 "BCM5421 1000BASE-T media interface" 235 #define MII_MODEL_BROADCOM_BCM5752 0x0010 /* BCM5752 1000BASE-T media interface */ 236 #define MII_STR_BROADCOM_BCM5752 "BCM5752 1000BASE-T media interface" 237 #define MII_MODEL_BROADCOM_BCM5701 0x0011 /* BCM5701 1000BASE-T media interface */ 238 #define MII_STR_BROADCOM_BCM5701 "BCM5701 1000BASE-T media interface" 239 #define MII_MODEL_BROADCOM_BCM5706 0x0015 /* BCM5706 1000BASE-T/SX media interface */ 240 #define MII_STR_BROADCOM_BCM5706 "BCM5706 1000BASE-T/SX media interface" 241 #define MII_MODEL_BROADCOM_BCM5703 0x0016 /* BCM5703 1000BASE-T media interface */ 242 #define MII_STR_BROADCOM_BCM5703 "BCM5703 1000BASE-T media interface" 243 #define MII_MODEL_BROADCOM_BCM5750 0x0018 /* BCM5750 1000BASE-T media interface */ 244 #define MII_STR_BROADCOM_BCM5750 "BCM5750 1000BASE-T media interface" 245 #define MII_MODEL_BROADCOM_BCM5704 0x0019 /* BCM5704 1000BASE-T media interface */ 246 #define MII_STR_BROADCOM_BCM5704 "BCM5704 1000BASE-T media interface" 247 #define MII_MODEL_BROADCOM_BCM5705 0x001a /* BCM5705 1000BASE-T media interface */ 248 #define MII_STR_BROADCOM_BCM5705 "BCM5705 1000BASE-T media interface" 249 #define MII_MODEL_BROADCOM_BCM54K2 0x002e /* BCM54K2 1000BASE-T media interface */ 250 #define MII_STR_BROADCOM_BCM54K2 "BCM54K2 1000BASE-T media interface" 251 #define MII_MODEL_BROADCOM_BCM5714 0x0034 /* BCM5714 1000BASE-T/X media interface */ 252 #define MII_STR_BROADCOM_BCM5714 "BCM5714 1000BASE-T/X media interface" 253 #define MII_MODEL_BROADCOM_BCM5780 0x0035 /* BCM5780 1000BASE-T/X media interface */ 254 #define MII_STR_BROADCOM_BCM5780 "BCM5780 1000BASE-T/X media interface" 255 #define MII_MODEL_BROADCOM_BCM5708C 0x0036 /* BCM5708C 1000BASE-T media interface */ 256 #define MII_STR_BROADCOM_BCM5708C "BCM5708C 1000BASE-T media interface" 257 #define MII_MODEL_BROADCOM_BCM5466 0x003b /* BCM5466 1000BASE-T media interface */ 258 #define MII_STR_BROADCOM_BCM5466 "BCM5466 1000BASE-T media interface" 259 #define MII_MODEL_BROADCOM2_BCM5325 0x0003 /* BCM5325 10/100 5-port PHY switch */ 260 #define MII_STR_BROADCOM2_BCM5325 "BCM5325 10/100 5-port PHY switch" 261 #define MII_MODEL_BROADCOM2_BCM5906 0x0004 /* BCM5906 10/100baseTX media interface */ 262 #define MII_STR_BROADCOM2_BCM5906 "BCM5906 10/100baseTX media interface" 263 #define MII_MODEL_BROADCOM2_BCM5478 0x0008 /* BCM5478 1000BASE-T media interface */ 264 #define MII_STR_BROADCOM2_BCM5478 "BCM5478 1000BASE-T media interface" 265 #define MII_MODEL_BROADCOM2_BCM5488 0x0009 /* BCM5488 1000BASE-T media interface */ 266 #define MII_STR_BROADCOM2_BCM5488 "BCM5488 1000BASE-T media interface" 267 #define MII_MODEL_BROADCOM2_BCM5481 0x000a /* BCM5481 1000BASE-T media interface */ 268 #define MII_STR_BROADCOM2_BCM5481 "BCM5481 1000BASE-T media interface" 269 #define MII_MODEL_BROADCOM2_BCM5482 0x000b /* BCM5482 1000BASE-T media interface */ 270 #define MII_STR_BROADCOM2_BCM5482 "BCM5482 1000BASE-T media interface" 271 #define MII_MODEL_BROADCOM2_BCM5755 0x000c /* BCM5755 1000BASE-T media interface */ 272 #define MII_STR_BROADCOM2_BCM5755 "BCM5755 1000BASE-T media interface" 273 #define MII_MODEL_BROADCOM2_BCM5756 0x000d /* BCM5756 1000BASE-T media interface XXX */ 274 #define MII_STR_BROADCOM2_BCM5756 "BCM5756 1000BASE-T media interface XXX" 275 #define MII_MODEL_BROADCOM2_BCM5754 0x000e /* BCM5754/5787 1000BASE-T media interface */ 276 #define MII_STR_BROADCOM2_BCM5754 "BCM5754/5787 1000BASE-T media interface" 277 #define MII_MODEL_BROADCOM2_BCM5708S 0x0015 /* BCM5708S 1000/2500baseSX PHY */ 278 #define MII_STR_BROADCOM2_BCM5708S "BCM5708S 1000/2500baseSX PHY" 279 #define MII_MODEL_BROADCOM2_BCM5785 0x0016 /* BCM5785 1000BASE-T media interface */ 280 #define MII_STR_BROADCOM2_BCM5785 "BCM5785 1000BASE-T media interface" 281 #define MII_MODEL_BROADCOM2_BCM5709CAX 0x002c /* BCM5709CAX 10/100/1000baseT PHY */ 282 #define MII_STR_BROADCOM2_BCM5709CAX "BCM5709CAX 10/100/1000baseT PHY" 283 #define MII_MODEL_BROADCOM2_BCM5722 0x002d /* BCM5722 1000BASE-T media interface */ 284 #define MII_STR_BROADCOM2_BCM5722 "BCM5722 1000BASE-T media interface" 285 #define MII_MODEL_BROADCOM2_BCM5784 0x003a /* BCM5784 10/100/1000baseT PHY */ 286 #define MII_STR_BROADCOM2_BCM5784 "BCM5784 10/100/1000baseT PHY" 287 #define MII_MODEL_BROADCOM2_BCM5709C 0x003c /* BCM5709 10/100/1000baseT PHY */ 288 #define MII_STR_BROADCOM2_BCM5709C "BCM5709 10/100/1000baseT PHY" 289 #define MII_MODEL_BROADCOM2_BCM5761 0x003d /* BCM5761 10/100/1000baseT PHY */ 290 #define MII_STR_BROADCOM2_BCM5761 "BCM5761 10/100/1000baseT PHY" 291 #define MII_MODEL_BROADCOM2_BCM5709S 0x003f /* BCM5709S 1000/2500baseSX PHY */ 292 #define MII_STR_BROADCOM2_BCM5709S "BCM5709S 1000/2500baseSX PHY" 293 #define MII_MODEL_BROADCOM3_BCM57780 0x0019 /* BCM57780 1000BASE-T media interface */ 294 #define MII_STR_BROADCOM3_BCM57780 "BCM57780 1000BASE-T media interface" 295 #define MII_MODEL_BROADCOM3_BCM5717C 0x0020 /* BCM5717C 1000BASE-T media interface */ 296 #define MII_STR_BROADCOM3_BCM5717C "BCM5717C 1000BASE-T media interface" 297 #define MII_MODEL_BROADCOM3_BCM5719C 0x0022 /* BCM5719C 1000BASE-T media interface */ 298 #define MII_STR_BROADCOM3_BCM5719C "BCM5719C 1000BASE-T media interface" 299 #define MII_MODEL_BROADCOM3_BCM57765 0x0024 /* BCM57765 1000BASE-T media interface */ 300 #define MII_STR_BROADCOM3_BCM57765 "BCM57765 1000BASE-T media interface" 301 #define MII_MODEL_BROADCOM3_BCM53125 0x0032 /* BCM53125 1000BASE-T switch */ 302 #define MII_STR_BROADCOM3_BCM53125 "BCM53125 1000BASE-T switch" 303 #define MII_MODEL_BROADCOM3_BCM5720C 0x0036 /* BCM5720C 1000BASE-T media interface */ 304 #define MII_STR_BROADCOM3_BCM5720C "BCM5720C 1000BASE-T media interface" 305 #define MII_MODEL_BROADCOM4_BCM54213PE 0x000a /* BCM54213PE 1000BASE-T media interface */ 306 #define MII_STR_BROADCOM4_BCM54213PE "BCM54213PE 1000BASE-T media interface" 307 #define MII_MODEL_BROADCOM4_BCM5725C 0x0038 /* BCM5725C 1000BASE-T media interface */ 308 #define MII_STR_BROADCOM4_BCM5725C "BCM5725C 1000BASE-T media interface" 309 #define MII_MODEL_xxBROADCOM_ALT1_BCM5906 0x0004 /* BCM5906 10/100baseTX media interface */ 310 #define MII_STR_xxBROADCOM_ALT1_BCM5906 "BCM5906 10/100baseTX media interface" 311 312 /* Cicada Semiconductor PHYs (-> Vitesse -> Microsemi) */ 313 314 #define MII_MODEL_xxCICADA_CIS8201 0x0001 /* Cicada CIS8201 10/100/1000TX PHY */ 315 #define MII_STR_xxCICADA_CIS8201 "Cicada CIS8201 10/100/1000TX PHY" 316 #define MII_MODEL_xxCICADA_CIS8204 0x0004 /* Cicada CIS8204 10/100/1000TX PHY */ 317 #define MII_STR_xxCICADA_CIS8204 "Cicada CIS8204 10/100/1000TX PHY" 318 #define MII_MODEL_xxCICADA_VSC8211 0x000b /* Cicada VSC8211 10/100/1000TX PHY */ 319 #define MII_STR_xxCICADA_VSC8211 "Cicada VSC8211 10/100/1000TX PHY" 320 #define MII_MODEL_xxCICADA_VSC8221 0x0015 /* Vitesse VSC8221 10/100/1000BASE-T PHY */ 321 #define MII_STR_xxCICADA_VSC8221 "Vitesse VSC8221 10/100/1000BASE-T PHY" 322 #define MII_MODEL_xxCICADA_VSC8224 0x0018 /* Vitesse VSC8224 10/100/1000BASE-T PHY */ 323 #define MII_STR_xxCICADA_VSC8224 "Vitesse VSC8224 10/100/1000BASE-T PHY" 324 #define MII_MODEL_xxCICADA_CIS8201A 0x0020 /* Cicada CIS8201 10/100/1000TX PHY */ 325 #define MII_STR_xxCICADA_CIS8201A "Cicada CIS8201 10/100/1000TX PHY" 326 #define MII_MODEL_xxCICADA_CIS8201B 0x0021 /* Cicada CIS8201 10/100/1000TX PHY */ 327 #define MII_STR_xxCICADA_CIS8201B "Cicada CIS8201 10/100/1000TX PHY" 328 #define MII_MODEL_xxCICADA_VSC8234 0x0022 /* Vitesse VSC8234 10/100/1000TX PHY */ 329 #define MII_STR_xxCICADA_VSC8234 "Vitesse VSC8234 10/100/1000TX PHY" 330 #define MII_MODEL_xxCICADA_VSC8244 0x002c /* Vitesse VSC8244 Quad 10/100/1000BASE-T PHY */ 331 #define MII_STR_xxCICADA_VSC8244 "Vitesse VSC8244 Quad 10/100/1000BASE-T PHY" 332 333 /* Davicom Semiconductor PHYs */ 334 /* AMD Am79C873 seems to be a relabeled DM9101 */ 335 #define MII_MODEL_DAVICOM_DM9101 0x0000 /* DM9101 (AMD Am79C873) 10/100 media interface */ 336 #define MII_STR_DAVICOM_DM9101 "DM9101 (AMD Am79C873) 10/100 media interface" 337 #define MII_MODEL_xxDAVICOM_DM9101 0x0000 /* DM9101 (AMD Am79C873) 10/100 media interface */ 338 #define MII_STR_xxDAVICOM_DM9101 "DM9101 (AMD Am79C873) 10/100 media interface" 339 #define MII_MODEL_xxDAVICOM_DM9102 0x0004 /* DM9102 10/100 media interface */ 340 #define MII_STR_xxDAVICOM_DM9102 "DM9102 10/100 media interface" 341 #define MII_MODEL_xxDAVICOM_DM9161 0x0008 /* DM9161 10/100 media interface */ 342 #define MII_STR_xxDAVICOM_DM9161 "DM9161 10/100 media interface" 343 #define MII_MODEL_xxDAVICOM_DM9161A 0x000a /* DM9161A 10/100 media interface */ 344 #define MII_STR_xxDAVICOM_DM9161A "DM9161A 10/100 media interface" 345 #define MII_MODEL_xxDAVICOM_DM9161B 0x000b /* DM9161[BC] 10/100 media interface */ 346 #define MII_STR_xxDAVICOM_DM9161B "DM9161[BC] 10/100 media interface" 347 #define MII_MODEL_xxDAVICOM_DM9601 0x000c /* DM9601 internal 10/100 media interface */ 348 #define MII_STR_xxDAVICOM_DM9601 "DM9601 internal 10/100 media interface" 349 350 /* IC Plus Corp. PHYs */ 351 #define MII_MODEL_xxICPLUS_IP100 0x0004 /* IP100 10/100 PHY */ 352 #define MII_STR_xxICPLUS_IP100 "IP100 10/100 PHY" 353 #define MII_MODEL_xxICPLUS_IP101 0x0005 /* IP101 10/100 PHY */ 354 #define MII_STR_xxICPLUS_IP101 "IP101 10/100 PHY" 355 #define MII_MODEL_xxICPLUS_IP1000A 0x0008 /* IP1000A 10/100/1000 PHY */ 356 #define MII_STR_xxICPLUS_IP1000A "IP1000A 10/100/1000 PHY" 357 #define MII_MODEL_xxICPLUS_IP1001 0x0019 /* IP1001 10/100/1000 PHY */ 358 #define MII_STR_xxICPLUS_IP1001 "IP1001 10/100/1000 PHY" 359 360 /* Integrated Circuit Systems PHYs */ 361 #define MII_MODEL_ICS_1889 0x0001 /* ICS1889 10/100 media interface */ 362 #define MII_STR_ICS_1889 "ICS1889 10/100 media interface" 363 #define MII_MODEL_ICS_1890 0x0002 /* ICS1890 10/100 media interface */ 364 #define MII_STR_ICS_1890 "ICS1890 10/100 media interface" 365 #define MII_MODEL_ICS_1892 0x0003 /* ICS1892 10/100 media interface */ 366 #define MII_STR_ICS_1892 "ICS1892 10/100 media interface" 367 #define MII_MODEL_ICS_1893 0x0004 /* ICS1893 10/100 media interface */ 368 #define MII_STR_ICS_1893 "ICS1893 10/100 media interface" 369 #define MII_MODEL_ICS_1893C 0x0005 /* ICS1893C 10/100 media interface */ 370 #define MII_STR_ICS_1893C "ICS1893C 10/100 media interface" 371 372 /* Intel PHYs */ 373 #define MII_MODEL_xxINTEL_I82553 0x0000 /* i82553 10/100 media interface */ 374 #define MII_STR_xxINTEL_I82553 "i82553 10/100 media interface" 375 #define MII_MODEL_yyINTEL_I82555 0x0015 /* i82555 10/100 media interface */ 376 #define MII_STR_yyINTEL_I82555 "i82555 10/100 media interface" 377 #define MII_MODEL_yyINTEL_I82562EH 0x0017 /* i82562EH HomePNA interface */ 378 #define MII_STR_yyINTEL_I82562EH "i82562EH HomePNA interface" 379 #define MII_MODEL_yyINTEL_I82562G 0x0031 /* i82562G 10/100 media interface */ 380 #define MII_STR_yyINTEL_I82562G "i82562G 10/100 media interface" 381 #define MII_MODEL_yyINTEL_I82562EM 0x0032 /* i82562EM 10/100 media interface */ 382 #define MII_STR_yyINTEL_I82562EM "i82562EM 10/100 media interface" 383 #define MII_MODEL_yyINTEL_I82562ET 0x0033 /* i82562ET 10/100 media interface */ 384 #define MII_STR_yyINTEL_I82562ET "i82562ET 10/100 media interface" 385 #define MII_MODEL_yyINTEL_I82553 0x0035 /* i82553 10/100 media interface */ 386 #define MII_STR_yyINTEL_I82553 "i82553 10/100 media interface" 387 #define MII_MODEL_yyINTEL_IGP01E1000 0x0038 /* Intel IGP01E1000 Gigabit PHY */ 388 #define MII_STR_yyINTEL_IGP01E1000 "Intel IGP01E1000 Gigabit PHY" 389 #define MII_MODEL_yyINTEL_I82566 0x0039 /* i82566 10/100/1000 media interface */ 390 #define MII_STR_yyINTEL_I82566 "i82566 10/100/1000 media interface" 391 #define MII_MODEL_INTEL_I82577 0x0005 /* i82577 10/100/1000 media interface */ 392 #define MII_STR_INTEL_I82577 "i82577 10/100/1000 media interface" 393 #define MII_MODEL_INTEL_I82579 0x0009 /* i82579 10/100/1000 media interface */ 394 #define MII_STR_INTEL_I82579 "i82579 10/100/1000 media interface" 395 #define MII_MODEL_INTEL_I217 0x000a /* i217 10/100/1000 media interface */ 396 #define MII_STR_INTEL_I217 "i217 10/100/1000 media interface" 397 #define MII_MODEL_INTEL_X540 0x0020 /* X540 100M/1G/10G media interface */ 398 #define MII_STR_INTEL_X540 "X540 100M/1G/10G media interface" 399 #define MII_MODEL_INTEL_X550 0x0022 /* X550 100M/1G/10G media interface */ 400 #define MII_STR_INTEL_X550 "X550 100M/1G/10G media interface" 401 #define MII_MODEL_INTEL_X557 0x0024 /* X557 100M/1G/10G media interface */ 402 #define MII_STR_INTEL_X557 "X557 100M/1G/10G media interface" 403 #define MII_MODEL_INTEL_I82580 0x003a /* 82580 10/100/1000 media interface */ 404 #define MII_STR_INTEL_I82580 "82580 10/100/1000 media interface" 405 #define MII_MODEL_INTEL_I350 0x003b /* I350 10/100/1000 media interface */ 406 #define MII_STR_INTEL_I350 "I350 10/100/1000 media interface" 407 #define MII_MODEL_xxMARVELL_I210 0x0000 /* I210 10/100/1000 media interface */ 408 #define MII_STR_xxMARVELL_I210 "I210 10/100/1000 media interface" 409 #define MII_MODEL_xxMARVELL_I82563 0x000a /* i82563 10/100/1000 media interface */ 410 #define MII_STR_xxMARVELL_I82563 "i82563 10/100/1000 media interface" 411 #define MII_MODEL_ATTANSIC_I82578 0x0004 /* Intel 82578 10/100/1000 media interface */ 412 #define MII_STR_ATTANSIC_I82578 "Intel 82578 10/100/1000 media interface" 413 /* Acquired by MaxLinear */ 414 #define MII_MODEL_INTEL2_GPY211 0x0000 /* MaxLinear GPY21[125] 2.5G PHY */ 415 #define MII_STR_INTEL2_GPY211 "MaxLinear GPY21[125] 2.5G PHY" 416 #define MII_MODEL_INTEL2_I226_1 0x0001 /* I226 2.5G media interface (1) */ 417 #define MII_STR_INTEL2_I226_1 "I226 2.5G media interface (1)" 418 #define MII_MODEL_INTEL2_I226_2 0x0005 /* I226 2.5G media interface (2) */ 419 #define MII_STR_INTEL2_I226_2 "I226 2.5G media interface (2)" 420 #define MII_MODEL_INTEL2_I225 0x000c /* I225 2.5G media interface */ 421 #define MII_STR_INTEL2_I225 "I225 2.5G media interface" 422 #define MII_MODEL_INTEL2_GPY211_2 0x0020 /* MaxLinear GPY21[12] 2.5G PHY (2) */ 423 #define MII_STR_INTEL2_GPY211_2 "MaxLinear GPY21[12] 2.5G PHY (2)" 424 #define MII_MODEL_INTEL2_GPY211_3 0x0021 /* MaxLinear GPY211 2.5G PHY (3) */ 425 #define MII_STR_INTEL2_GPY211_3 "MaxLinear GPY211 2.5G PHY (3)" 426 #define MII_MODEL_INTEL2_GPY212 0x0022 /* MaxLinear GPY212 2.5G PHY */ 427 #define MII_STR_INTEL2_GPY212 "MaxLinear GPY212 2.5G PHY" 428 #define MII_MODEL_INTEL2_GPY115 0x0030 /* MaxLinear GPY115 Gigabit PHY */ 429 #define MII_STR_INTEL2_GPY115 "MaxLinear GPY115 Gigabit PHY" 430 #define MII_MODEL_INTEL2_GPY215 0x0032 /* MaxLinear GPY215 2.5G PHY */ 431 #define MII_STR_INTEL2_GPY215 "MaxLinear GPY215 2.5G PHY" 432 433 /* JMicron PHYs */ 434 #define MII_MODEL_JMICRON_JMP211 0x0021 /* JMP211 10/100/1000 media interface */ 435 #define MII_STR_JMICRON_JMP211 "JMP211 10/100/1000 media interface" 436 #define MII_MODEL_JMICRON_JMP202 0x0022 /* JMP202 10/100 media interface */ 437 #define MII_STR_JMICRON_JMP202 "JMP202 10/100 media interface" 438 439 /* Level 1 PHYs */ 440 #define MII_MODEL_xxLEVEL1_LXT970 0x0000 /* LXT970 10/100 media interface */ 441 #define MII_STR_xxLEVEL1_LXT970 "LXT970 10/100 media interface" 442 #define MII_MODEL_LEVEL1_LXT1000_OLD 0x0003 /* LXT1000 1000BASE-T media interface */ 443 #define MII_STR_LEVEL1_LXT1000_OLD "LXT1000 1000BASE-T media interface" 444 #define MII_MODEL_LEVEL1_LXT974 0x0004 /* LXT974 10/100 Quad PHY */ 445 #define MII_STR_LEVEL1_LXT974 "LXT974 10/100 Quad PHY" 446 #define MII_MODEL_LEVEL1_LXT975 0x0005 /* LXT975 10/100 Quad PHY */ 447 #define MII_STR_LEVEL1_LXT975 "LXT975 10/100 Quad PHY" 448 #define MII_MODEL_LEVEL1_LXT1000 0x000c /* LXT1000 1000BASE-T media interface */ 449 #define MII_STR_LEVEL1_LXT1000 "LXT1000 1000BASE-T media interface" 450 #define MII_MODEL_LEVEL1_LXT971 0x000e /* LXT971/2 10/100 media interface */ 451 #define MII_STR_LEVEL1_LXT971 "LXT971/2 10/100 media interface" 452 #define MII_MODEL_LEVEL1_LXT973 0x0021 /* LXT973 10/100 Dual PHY */ 453 #define MII_STR_LEVEL1_LXT973 "LXT973 10/100 Dual PHY" 454 455 /* Marvell Semiconductor PHYs */ 456 #define MII_MODEL_xxMARVELL_E1000 0x0000 /* Marvell 88E1000 Gigabit PHY */ 457 #define MII_STR_xxMARVELL_E1000 "Marvell 88E1000 Gigabit PHY" 458 #define MII_MODEL_xxMARVELL_E1011 0x0002 /* Marvell 88E1011 Gigabit PHY */ 459 #define MII_STR_xxMARVELL_E1011 "Marvell 88E1011 Gigabit PHY" 460 #define MII_MODEL_xxMARVELL_E1000_3 0x0003 /* Marvell 88E1000 Gigabit PHY */ 461 #define MII_STR_xxMARVELL_E1000_3 "Marvell 88E1000 Gigabit PHY" 462 #define MII_MODEL_xxMARVELL_E1000S 0x0004 /* Marvell 88E1000S Gigabit PHY */ 463 #define MII_STR_xxMARVELL_E1000S "Marvell 88E1000S Gigabit PHY" 464 #define MII_MODEL_xxMARVELL_E1000_5 0x0005 /* Marvell 88E1000 Gigabit PHY */ 465 #define MII_STR_xxMARVELL_E1000_5 "Marvell 88E1000 Gigabit PHY" 466 #define MII_MODEL_xxMARVELL_E1101 0x0006 /* Marvell 88E1101 Gigabit PHY */ 467 #define MII_STR_xxMARVELL_E1101 "Marvell 88E1101 Gigabit PHY" 468 #define MII_MODEL_xxMARVELL_E3082 0x0008 /* Marvell 88E3082 10/100 Fast Ethernet PHY */ 469 #define MII_STR_xxMARVELL_E3082 "Marvell 88E3082 10/100 Fast Ethernet PHY" 470 #define MII_MODEL_xxMARVELL_E1112 0x0009 /* Marvell 88E1112 Gigabit PHY */ 471 #define MII_STR_xxMARVELL_E1112 "Marvell 88E1112 Gigabit PHY" 472 #define MII_MODEL_xxMARVELL_E1149 0x000b /* Marvell 88E1149 Gigabit PHY */ 473 #define MII_STR_xxMARVELL_E1149 "Marvell 88E1149 Gigabit PHY" 474 #define MII_MODEL_xxMARVELL_E1111 0x000c /* Marvell 88E1111 Gigabit PHY */ 475 #define MII_STR_xxMARVELL_E1111 "Marvell 88E1111 Gigabit PHY" 476 #define MII_MODEL_xxMARVELL_E1145 0x000d /* Marvell 88E1145 Quad Gigabit PHY */ 477 #define MII_STR_xxMARVELL_E1145 "Marvell 88E1145 Quad Gigabit PHY" 478 #define MII_MODEL_xxMARVELL_E6060 0x0010 /* Marvell 88E6060 6-Port 10/100 Fast Ethernet Switch */ 479 #define MII_STR_xxMARVELL_E6060 "Marvell 88E6060 6-Port 10/100 Fast Ethernet Switch" 480 #define MII_MODEL_xxMARVELL_I347 0x001c /* Intel I347-AT4 Gigabit PHY */ 481 #define MII_STR_xxMARVELL_I347 "Intel I347-AT4 Gigabit PHY" 482 #define MII_MODEL_xxMARVELL_E1512 0x001d /* Marvell 88E151[0248] Gigabit PHY */ 483 #define MII_STR_xxMARVELL_E1512 "Marvell 88E151[0248] Gigabit PHY" 484 #define MII_MODEL_xxMARVELL_E1340M 0x001f /* Marvell 88E1340 Gigabit PHY */ 485 #define MII_STR_xxMARVELL_E1340M "Marvell 88E1340 Gigabit PHY" 486 #define MII_MODEL_xxMARVELL_E1116 0x0021 /* Marvell 88E1116 Gigabit PHY */ 487 #define MII_STR_xxMARVELL_E1116 "Marvell 88E1116 Gigabit PHY" 488 #define MII_MODEL_xxMARVELL_E1118 0x0022 /* Marvell 88E1118 Gigabit PHY */ 489 #define MII_STR_xxMARVELL_E1118 "Marvell 88E1118 Gigabit PHY" 490 #define MII_MODEL_xxMARVELL_E1240 0x0023 /* Marvell 88E1240 Gigabit PHY */ 491 #define MII_STR_xxMARVELL_E1240 "Marvell 88E1240 Gigabit PHY" 492 #define MII_MODEL_xxMARVELL_E1116R 0x0024 /* Marvell 88E1116R Gigabit PHY */ 493 #define MII_STR_xxMARVELL_E1116R "Marvell 88E1116R Gigabit PHY" 494 #define MII_MODEL_xxMARVELL_E1149R 0x0025 /* Marvell 88E1149R Quad Gigabit PHY */ 495 #define MII_STR_xxMARVELL_E1149R "Marvell 88E1149R Quad Gigabit PHY" 496 #define MII_MODEL_xxMARVELL_E3016 0x0026 /* Marvell 88E3016 10/100 Fast Ethernet PHY */ 497 #define MII_STR_xxMARVELL_E3016 "Marvell 88E3016 10/100 Fast Ethernet PHY" 498 #define MII_MODEL_xxMARVELL_PHYG65G 0x0027 /* Marvell PHYG65G Gigabit PHY */ 499 #define MII_STR_xxMARVELL_PHYG65G "Marvell PHYG65G Gigabit PHY" 500 #define MII_MODEL_xxMARVELL_E1318S 0x0029 /* Marvell 88E1318S Gigabit PHY */ 501 #define MII_STR_xxMARVELL_E1318S "Marvell 88E1318S Gigabit PHY" 502 #define MII_MODEL_xxMARVELL_E1543 0x002a /* Marvell 88E154[358] Alaska Quad Port Gb PHY */ 503 #define MII_STR_xxMARVELL_E1543 "Marvell 88E154[358] Alaska Quad Port Gb PHY" 504 #define MII_MODEL_MARVELL_E1000_0 0x0000 /* Marvell 88E1000 Gigabit PHY */ 505 #define MII_STR_MARVELL_E1000_0 "Marvell 88E1000 Gigabit PHY" 506 #define MII_MODEL_MARVELL_E1011 0x0002 /* Marvell 88E1011 Gigabit PHY */ 507 #define MII_STR_MARVELL_E1011 "Marvell 88E1011 Gigabit PHY" 508 #define MII_MODEL_MARVELL_E1000_3 0x0003 /* Marvell 88E1000 Gigabit PHY */ 509 #define MII_STR_MARVELL_E1000_3 "Marvell 88E1000 Gigabit PHY" 510 #define MII_MODEL_MARVELL_E1000_5 0x0005 /* Marvell 88E1000 Gigabit PHY */ 511 #define MII_STR_MARVELL_E1000_5 "Marvell 88E1000 Gigabit PHY" 512 #define MII_MODEL_MARVELL_E1000_6 0x0006 /* Marvell 88E1000 Gigabit PHY */ 513 #define MII_STR_MARVELL_E1000_6 "Marvell 88E1000 Gigabit PHY" 514 #define MII_MODEL_MARVELL_E1111 0x000c /* Marvell 88E1111 Gigabit PHY */ 515 #define MII_STR_MARVELL_E1111 "Marvell 88E1111 Gigabit PHY" 516 517 /* Micrel PHYs (Kendin and Microchip) */ 518 #define MII_MODEL_MICREL_KSZ8041 0x0011 /* Micrel KSZ8041TL/FTL/MLL 10/100 PHY */ 519 #define MII_STR_MICREL_KSZ8041 "Micrel KSZ8041TL/FTL/MLL 10/100 PHY" 520 #define MII_MODEL_MICREL_KSZ8041RNLI 0x0013 /* Micrel KSZ8041RNLI 10/100 PHY */ 521 #define MII_STR_MICREL_KSZ8041RNLI "Micrel KSZ8041RNLI 10/100 PHY" 522 #define MII_MODEL_MICREL_KSZ8051 0x0015 /* Micrel KSZ80[235]1 10/100 PHY */ 523 #define MII_STR_MICREL_KSZ8051 "Micrel KSZ80[235]1 10/100 PHY" 524 #define MII_MODEL_MICREL_KSZ8081 0x0016 /* Micrel KSZ80[89]1 10/100 PHY */ 525 #define MII_STR_MICREL_KSZ8081 "Micrel KSZ80[89]1 10/100 PHY" 526 #define MII_MODEL_MICREL_KSZ8061 0x0017 /* Micrel KSZ8061 10/100 PHY */ 527 #define MII_STR_MICREL_KSZ8061 "Micrel KSZ8061 10/100 PHY" 528 #define MII_MODEL_MICREL_KSZ9021_8001_8721 0x0021 /* Micrel KSZ9021 Gb & KSZ8001/8721 10/100 PHY */ 529 #define MII_STR_MICREL_KSZ9021_8001_8721 "Micrel KSZ9021 Gb & KSZ8001/8721 10/100 PHY" 530 #define MII_MODEL_MICREL_KSZ9031 0x0022 /* Micrel KSZ9031 10/100/1000 PHY */ 531 #define MII_STR_MICREL_KSZ9031 "Micrel KSZ9031 10/100/1000 PHY" 532 #define MII_MODEL_MICREL_KSZ9477 0x0023 /* Micrel KSZ9477 10/100/1000 PHY */ 533 #define MII_STR_MICREL_KSZ9477 "Micrel KSZ9477 10/100/1000 PHY" 534 #define MII_MODEL_MICREL_KSZ9131 0x0024 /* Micrel KSZ9131 10/100/1000 PHY */ 535 #define MII_STR_MICREL_KSZ9131 "Micrel KSZ9131 10/100/1000 PHY" 536 #define MII_MODEL_MICREL_KS8737 0x0032 /* Micrel KS8737 10/100 PHY */ 537 #define MII_STR_MICREL_KS8737 "Micrel KS8737 10/100 PHY" 538 539 /* Motorcomm */ 540 #define MII_MODEL_MOTORCOMM_YT8531 0x0011 /* Motorcomm YT8531 Gigabit PHY */ 541 #define MII_STR_MOTORCOMM_YT8531 "Motorcomm YT8531 Gigabit PHY" 542 543 /* Myson Technology PHYs */ 544 #define MII_MODEL_xxMYSON_MTD972 0x0000 /* MTD972 10/100 media interface */ 545 #define MII_STR_xxMYSON_MTD972 "MTD972 10/100 media interface" 546 #define MII_MODEL_MYSON_MTD803 0x0000 /* MTD803 3-in-1 media interface */ 547 #define MII_STR_MYSON_MTD803 "MTD803 3-in-1 media interface" 548 549 /* National Semiconductor PHYs */ 550 #define MII_MODEL_xxNATSEMI_DP83840 0x0000 /* DP83840 10/100 media interface */ 551 #define MII_STR_xxNATSEMI_DP83840 "DP83840 10/100 media interface" 552 #define MII_MODEL_xxNATSEMI_DP83843 0x0001 /* DP83843 10/100 media interface */ 553 #define MII_STR_xxNATSEMI_DP83843 "DP83843 10/100 media interface" 554 #define MII_MODEL_xxNATSEMI_DP83815 0x0002 /* DP83815/DP83846A 10/100 media interface */ 555 #define MII_STR_xxNATSEMI_DP83815 "DP83815/DP83846A 10/100 media interface" 556 #define MII_MODEL_xxNATSEMI_DP83847 0x0003 /* DP83847 10/100 media interface */ 557 #define MII_STR_xxNATSEMI_DP83847 "DP83847 10/100 media interface" 558 #define MII_MODEL_xxNATSEMI_DP83891 0x0005 /* DP83891 1000BASE-T media interface */ 559 #define MII_STR_xxNATSEMI_DP83891 "DP83891 1000BASE-T media interface" 560 #define MII_MODEL_xxNATSEMI_DP83861 0x0006 /* DP83861 1000BASE-T media interface */ 561 #define MII_STR_xxNATSEMI_DP83861 "DP83861 1000BASE-T media interface" 562 #define MII_MODEL_xxNATSEMI_DP83865 0x0007 /* DP83865 1000BASE-T media interface */ 563 #define MII_STR_xxNATSEMI_DP83865 "DP83865 1000BASE-T media interface" 564 #define MII_MODEL_xxNATSEMI_DP83849 0x000a /* DP83849 10/100 media interface */ 565 #define MII_STR_xxNATSEMI_DP83849 "DP83849 10/100 media interface" 566 567 /* PMC Sierra PHYs */ 568 #define MII_MODEL_xxPMCSIERRA_PM8351 0x0000 /* PM8351 OctalPHY Gigabit interface */ 569 #define MII_STR_xxPMCSIERRA_PM8351 "PM8351 OctalPHY Gigabit interface" 570 #define MII_MODEL_xxPMCSIERRA2_PM8352 0x0002 /* PM8352 OctalPHY Gigabit interface */ 571 #define MII_STR_xxPMCSIERRA2_PM8352 "PM8352 OctalPHY Gigabit interface" 572 #define MII_MODEL_xxPMCSIERRA2_PM8353 0x0003 /* PM8353 QuadPHY Gigabit interface */ 573 #define MII_STR_xxPMCSIERRA2_PM8353 "PM8353 QuadPHY Gigabit interface" 574 #define MII_MODEL_PMCSIERRA_PM8354 0x0004 /* PM8354 QuadPHY Gigabit interface */ 575 #define MII_STR_PMCSIERRA_PM8354 "PM8354 QuadPHY Gigabit interface" 576 577 /* Quality Semiconductor PHYs */ 578 #define MII_MODEL_xxQUALSEMI_QS6612 0x0000 /* QS6612 10/100 media interface */ 579 #define MII_STR_xxQUALSEMI_QS6612 "QS6612 10/100 media interface" 580 581 /* RDC Semiconductor PHYs */ 582 #define MII_MODEL_xxRDC_R6040 0x0003 /* R6040 10/100 media interface */ 583 #define MII_STR_xxRDC_R6040 "R6040 10/100 media interface" 584 #define MII_MODEL_xxRDC_R6040_2 0x0005 /* R6040 10/100 media interface */ 585 #define MII_STR_xxRDC_R6040_2 "R6040 10/100 media interface" 586 #define MII_MODEL_xxRDC_R6040_3 0x0006 /* R6040 10/100 media interface */ 587 #define MII_STR_xxRDC_R6040_3 "R6040 10/100 media interface" 588 589 /* RealTek PHYs */ 590 #define MII_MODEL_xxREALTEK_RTL8169S 0x0011 /* RTL8169S/8110S/8211 1000BASE-T media interface */ 591 #define MII_STR_xxREALTEK_RTL8169S "RTL8169S/8110S/8211 1000BASE-T media interface" 592 #define MII_MODEL_yyREALTEK_RTL8201L 0x0020 /* RTL8201L 10/100 media interface */ 593 #define MII_STR_yyREALTEK_RTL8201L "RTL8201L 10/100 media interface" 594 #define MII_MODEL_REALTEK_RTL8251 0x0000 /* RTL8251 1000BASE-T media interface */ 595 #define MII_STR_REALTEK_RTL8251 "RTL8251 1000BASE-T media interface" 596 #define MII_MODEL_REALTEK_RTL8201E 0x0008 /* RTL8201E 10/100 media interface */ 597 #define MII_STR_REALTEK_RTL8201E "RTL8201E 10/100 media interface" 598 #define MII_MODEL_REALTEK_RTL8169S 0x0011 /* RTL8169S/8110S/8211 1000BASE-T media interface */ 599 #define MII_STR_REALTEK_RTL8169S "RTL8169S/8110S/8211 1000BASE-T media interface" 600 601 /* Seeq PHYs */ 602 #define MII_MODEL_SEEQ_80220 0x0003 /* Seeq 80220 10/100 media interface */ 603 #define MII_STR_SEEQ_80220 "Seeq 80220 10/100 media interface" 604 #define MII_MODEL_SEEQ_84220 0x0004 /* Seeq 84220 10/100 media interface */ 605 #define MII_STR_SEEQ_84220 "Seeq 84220 10/100 media interface" 606 #define MII_MODEL_SEEQ_80225 0x0008 /* Seeq 80225 10/100 media interface */ 607 #define MII_STR_SEEQ_80225 "Seeq 80225 10/100 media interface" 608 609 /* Silicon Integrated Systems PHYs */ 610 #define MII_MODEL_SIS_900 0x0000 /* SiS 900 10/100 media interface */ 611 #define MII_STR_SIS_900 "SiS 900 10/100 media interface" 612 613 /* SMSC PHYs */ 614 #define MII_MODEL_SMSC_LAN83C185 0x000a /* SMSC LAN83C185 10/100 PHY */ 615 #define MII_STR_SMSC_LAN83C185 "SMSC LAN83C185 10/100 PHY" 616 #define MII_MODEL_SMSC_LAN8700 0x000c /* SMSC LAN8700 10/100 Ethernet Transceiver */ 617 #define MII_STR_SMSC_LAN8700 "SMSC LAN8700 10/100 Ethernet Transceiver" 618 #define MII_MODEL_SMSC_LAN911X 0x000d /* SMSC LAN911X internal 10/100 PHY */ 619 #define MII_STR_SMSC_LAN911X "SMSC LAN911X internal 10/100 PHY" 620 #define MII_MODEL_SMSC_LAN75XX 0x000e /* SMSC LAN75XX internal 10/100 PHY */ 621 #define MII_STR_SMSC_LAN75XX "SMSC LAN75XX internal 10/100 PHY" 622 #define MII_MODEL_SMSC_LAN8710_LAN8720 0x000f /* SMSC LAN8710/LAN8720 10/100 Ethernet Transceiver */ 623 #define MII_STR_SMSC_LAN8710_LAN8720 "SMSC LAN8710/LAN8720 10/100 Ethernet Transceiver" 624 #define MII_MODEL_SMSC_LAN8740 0x0011 /* SMSC LAN8740 10/100 media interface */ 625 #define MII_STR_SMSC_LAN8740 "SMSC LAN8740 10/100 media interface" 626 #define MII_MODEL_SMSC_LAN8741A 0x0012 /* SMSC LAN8741A 10/100 media interface */ 627 #define MII_STR_SMSC_LAN8741A "SMSC LAN8741A 10/100 media interface" 628 #define MII_MODEL_SMSC_LAN8742 0x0013 /* SMSC LAN8742 10/100 media interface */ 629 #define MII_STR_SMSC_LAN8742 "SMSC LAN8742 10/100 media interface" 630 631 /* Teranetics PHY */ 632 #define MII_MODEL_TERANETICS_TN1010 0x0001 /* Teranetics TN1010 10GBase-T PHY */ 633 #define MII_STR_TERANETICS_TN1010 "Teranetics TN1010 10GBase-T PHY" 634 635 /* Texas Instruments PHYs */ 636 #define MII_MODEL_TI_TLAN10T 0x0001 /* ThunderLAN 10BASE-T media interface */ 637 #define MII_STR_TI_TLAN10T "ThunderLAN 10BASE-T media interface" 638 #define MII_MODEL_TI_100VGPMI 0x0002 /* ThunderLAN 100VG-AnyLan media interface */ 639 #define MII_STR_TI_100VGPMI "ThunderLAN 100VG-AnyLan media interface" 640 #define MII_MODEL_TI_TNETE2101 0x0003 /* TNETE2101 media interface */ 641 #define MII_STR_TI_TNETE2101 "TNETE2101 media interface" 642 643 /* TDK Semiconductor PHYs */ 644 #define MII_MODEL_xxTSC_78Q2120 0x0014 /* 78Q2120 10/100 media interface */ 645 #define MII_STR_xxTSC_78Q2120 "78Q2120 10/100 media interface" 646 #define MII_MODEL_xxTSC_78Q2121 0x0015 /* 78Q2121 100BASE-TX media interface */ 647 #define MII_STR_xxTSC_78Q2121 "78Q2121 100BASE-TX media interface" 648 649 /* VIA Technologies PHYs */ 650 #define MII_MODEL_xxVIA_VT6103 0x0032 /* VT6103 10/100 PHY */ 651 #define MII_STR_xxVIA_VT6103 "VT6103 10/100 PHY" 652 #define MII_MODEL_xxVIA_VT6103_2 0x0034 /* VT6103 10/100 PHY */ 653 #define MII_STR_xxVIA_VT6103_2 "VT6103 10/100 PHY" 654 655 /* Vitesse PHYs (Now Microsemi) */ 656 #define MII_MODEL_xxVITESSE_VSC8601 0x0002 /* VSC8601 10/100/1000 PHY */ 657 #define MII_STR_xxVITESSE_VSC8601 "VSC8601 10/100/1000 PHY" 658 #define MII_MODEL_xxVITESSE_VSC8641 0x0003 /* Vitesse VSC8641 10/100/1000TX PHY */ 659 #define MII_STR_xxVITESSE_VSC8641 "Vitesse VSC8641 10/100/1000TX PHY" 660 #define MII_MODEL_xxVITESSE_VSC8504 0x000c /* Vitesse VSC8504 quad 10/100/1000TX PHY */ 661 #define MII_STR_xxVITESSE_VSC8504 "Vitesse VSC8504 quad 10/100/1000TX PHY" 662 #define MII_MODEL_xxVITESSE_VSC8552 0x000e /* Vitesse VSC8552 dual 10/100/1000TX PHY */ 663 #define MII_STR_xxVITESSE_VSC8552 "Vitesse VSC8552 dual 10/100/1000TX PHY" 664 #define MII_MODEL_xxVITESSE_VSC8502 0x0012 /* Vitesse VSC8502 dual 10/100/1000TX PHY */ 665 #define MII_STR_xxVITESSE_VSC8502 "Vitesse VSC8502 dual 10/100/1000TX PHY" 666 #define MII_MODEL_xxVITESSE_VSC8501 0x0013 /* Vitesse VSC8501 10/100/1000TX PHY */ 667 #define MII_STR_xxVITESSE_VSC8501 "Vitesse VSC8501 10/100/1000TX PHY" 668 #define MII_MODEL_xxVITESSE_VSC8531 0x0017 /* Vitesse VSC8531 10/100/1000TX PHY */ 669 #define MII_STR_xxVITESSE_VSC8531 "Vitesse VSC8531 10/100/1000TX PHY" 670 #define MII_MODEL_xxVITESSE_VSC8662 0x0026 /* Vitesse VSC866[24] dual/quad 1000T 100FX 1000X PHY */ 671 #define MII_STR_xxVITESSE_VSC8662 "Vitesse VSC866[24] dual/quad 1000T 100FX 1000X PHY" 672 #define MII_MODEL_xxVITESSE_VSC8514 0x0027 /* Vitesse VSC8514 quad 1000T PHY */ 673 #define MII_STR_xxVITESSE_VSC8514 "Vitesse VSC8514 quad 1000T PHY" 674 #define MII_MODEL_xxVITESSE_VSC8512 0x002e /* Vitesse VSC8512 12port 1000T PHY */ 675 #define MII_STR_xxVITESSE_VSC8512 "Vitesse VSC8512 12port 1000T PHY" 676 #define MII_MODEL_xxVITESSE_VSC8522 0x002f /* Vitesse VSC8522 12port 1000T PHY */ 677 #define MII_STR_xxVITESSE_VSC8522 "Vitesse VSC8522 12port 1000T PHY" 678 #define MII_MODEL_xxVITESSE_VSC8658 0x0035 /* Vitesse VSC8658 octal 1000T 100FX 1000X PHY */ 679 #define MII_STR_xxVITESSE_VSC8658 "Vitesse VSC8658 octal 1000T 100FX 1000X PHY" 680 #define MII_MODEL_xxVITESSE_VSC8541 0x0037 /* Vitesse VSC8541 1000T PHY */ 681 #define MII_STR_xxVITESSE_VSC8541 "Vitesse VSC8541 1000T PHY" 682 683 /* XaQti Corp. PHYs */ 684 #define MII_MODEL_xxXAQTI_XMACII 0x0000 /* XaQti Corp. XMAC II gigabit interface */ 685 #define MII_STR_xxXAQTI_XMACII "XaQti Corp. XMAC II gigabit interface" 686 687 /* Define format strings for non-existent values */ 688 #define mii_id1_format "oui %6.6x" 689 #define mii_id2_format "model %4.4x" 690
Indexes created Tue Sep 23 23:09:58 GMT 2025