1 /* ********************************************************************* 2 * SB1250 Board Support Package 3 * 4 * Generic Bus Constants File: sb1250_genbus.h 5 * 6 * This module contains constants and macros useful for 7 * manipulating the SB1250's Generic Bus interface 8 * 9 * SB1250 specification level: User's manual 10/21/02 10 * BCM1280 specification level: User's Manual 11/14/03 11 * 12 ********************************************************************* 13 * 14 * Copyright 2000,2001,2002,2003,2004 15 * Broadcom Corporation. All rights reserved. 16 * 17 * This software is furnished under license and may be used and 18 * copied only in accordance with the following terms and 19 * conditions. Subject to these conditions, you may download, 20 * copy, install, use, modify and distribute modified or unmodified 21 * copies of this software in source and/or binary form. No title 22 * or ownership is transferred hereby. 23 * 24 * 1) Any source code used, modified or distributed must reproduce 25 * and retain this copyright notice and list of conditions 26 * as they appear in the source file. 27 * 28 * 2) No right is granted to use any trade name, trademark, or 29 * logo of Broadcom Corporation. The "Broadcom Corporation" 30 * name may not be used to endorse or promote products derived 31 * from this software without the prior written permission of 32 * Broadcom Corporation. 33 * 34 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 35 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 36 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 37 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 38 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 39 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 40 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 41 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 42 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 43 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 44 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 45 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 46 * THE POSSIBILITY OF SUCH DAMAGE. 47 ********************************************************************* */ 48 49 50 #ifndef _SB1250_GENBUS_H 51 #define _SB1250_GENBUS_H 52 53 #include "sb1250_defs.h" 54 55 /* 56 * Generic Bus Region Configuration Registers (Table 11-4) 57 */ 58 59 #define S_IO_RDY_ACTIVE 0 60 #define M_IO_RDY_ACTIVE _SB_MAKEMASK1(S_IO_RDY_ACTIVE) 61 62 #define S_IO_ENA_RDY 1 63 #define M_IO_ENA_RDY _SB_MAKEMASK1(S_IO_ENA_RDY) 64 65 #define S_IO_WIDTH_SEL 2 66 #define M_IO_WIDTH_SEL _SB_MAKEMASK(2,S_IO_WIDTH_SEL) 67 #define K_IO_WIDTH_SEL_1 0 68 #define K_IO_WIDTH_SEL_2 1 69 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ 70 || SIBYTE_HDR_FEATURE_CHIP(1480) 71 #define K_IO_WIDTH_SEL_1L 2 72 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 73 #define K_IO_WIDTH_SEL_4 3 74 #define V_IO_WIDTH_SEL(x) _SB_MAKEVALUE(x,S_IO_WIDTH_SEL) 75 #define G_IO_WIDTH_SEL(x) _SB_GETVALUE(x,S_IO_WIDTH_SEL,M_IO_WIDTH_SEL) 76 77 #define S_IO_PARITY_ENA 4 78 #define M_IO_PARITY_ENA _SB_MAKEMASK1(S_IO_PARITY_ENA) 79 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ 80 || SIBYTE_HDR_FEATURE_CHIP(1480) 81 #define S_IO_BURST_EN 5 82 #define M_IO_BURST_EN _SB_MAKEMASK1(S_IO_BURST_EN) 83 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 84 #define S_IO_PARITY_ODD 6 85 #define M_IO_PARITY_ODD _SB_MAKEMASK1(S_IO_PARITY_ODD) 86 #define S_IO_NONMUX 7 87 #define M_IO_NONMUX _SB_MAKEMASK1(S_IO_NONMUX) 88 89 #define S_IO_TIMEOUT 8 90 #define M_IO_TIMEOUT _SB_MAKEMASK(8,S_IO_TIMEOUT) 91 #define V_IO_TIMEOUT(x) _SB_MAKEVALUE(x,S_IO_TIMEOUT) 92 #define G_IO_TIMEOUT(x) _SB_GETVALUE(x,S_IO_TIMEOUT,M_IO_TIMEOUT) 93 94 /* 95 * Generic Bus Region Size register (Table 11-5) 96 */ 97 98 #define S_IO_MULT_SIZE 0 99 #define M_IO_MULT_SIZE _SB_MAKEMASK(12,S_IO_MULT_SIZE) 100 #define V_IO_MULT_SIZE(x) _SB_MAKEVALUE(x,S_IO_MULT_SIZE) 101 #define G_IO_MULT_SIZE(x) _SB_GETVALUE(x,S_IO_MULT_SIZE,M_IO_MULT_SIZE) 102 103 #define S_IO_REGSIZE 16 /* # bits to shift size for this reg */ 104 105 /* 106 * Generic Bus Region Address (Table 11-6) 107 */ 108 109 #define S_IO_START_ADDR 0 110 #define M_IO_START_ADDR _SB_MAKEMASK(14,S_IO_START_ADDR) 111 #define V_IO_START_ADDR(x) _SB_MAKEVALUE(x,S_IO_START_ADDR) 112 #define G_IO_START_ADDR(x) _SB_GETVALUE(x,S_IO_START_ADDR,M_IO_START_ADDR) 113 114 #define S_IO_ADDRBASE 16 /* # bits to shift addr for this reg */ 115 116 #define M_IO_BLK_CACHE _SB_MAKEMASK1(15) 117 118 119 /* 120 * Generic Bus Timing 0 Registers (Table 11-7) 121 */ 122 123 #define S_IO_ALE_WIDTH 0 124 #define M_IO_ALE_WIDTH _SB_MAKEMASK(3,S_IO_ALE_WIDTH) 125 #define V_IO_ALE_WIDTH(x) _SB_MAKEVALUE(x,S_IO_ALE_WIDTH) 126 #define G_IO_ALE_WIDTH(x) _SB_GETVALUE(x,S_IO_ALE_WIDTH,M_IO_ALE_WIDTH) 127 128 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ 129 || SIBYTE_HDR_FEATURE_CHIP(1480) 130 #define M_IO_EARLY_CS _SB_MAKEMASK1(3) 131 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 132 133 #define S_IO_ALE_TO_CS 4 134 #define M_IO_ALE_TO_CS _SB_MAKEMASK(2,S_IO_ALE_TO_CS) 135 #define V_IO_ALE_TO_CS(x) _SB_MAKEVALUE(x,S_IO_ALE_TO_CS) 136 #define G_IO_ALE_TO_CS(x) _SB_GETVALUE(x,S_IO_ALE_TO_CS,M_IO_ALE_TO_CS) 137 138 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ 139 || SIBYTE_HDR_FEATURE_CHIP(1480) 140 #define S_IO_BURST_WIDTH _SB_MAKE64(6) 141 #define M_IO_BURST_WIDTH _SB_MAKEMASK(2,S_IO_BURST_WIDTH) 142 #define V_IO_BURST_WIDTH(x) _SB_MAKEVALUE(x,S_IO_BURST_WIDTH) 143 #define G_IO_BURST_WIDTH(x) _SB_GETVALUE(x,S_IO_BURST_WIDTH,M_IO_BURST_WIDTH) 144 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 145 146 #define S_IO_CS_WIDTH 8 147 #define M_IO_CS_WIDTH _SB_MAKEMASK(5,S_IO_CS_WIDTH) 148 #define V_IO_CS_WIDTH(x) _SB_MAKEVALUE(x,S_IO_CS_WIDTH) 149 #define G_IO_CS_WIDTH(x) _SB_GETVALUE(x,S_IO_CS_WIDTH,M_IO_CS_WIDTH) 150 151 #define S_IO_RDY_SMPLE 13 152 #define M_IO_RDY_SMPLE _SB_MAKEMASK(3,S_IO_RDY_SMPLE) 153 #define V_IO_RDY_SMPLE(x) _SB_MAKEVALUE(x,S_IO_RDY_SMPLE) 154 #define G_IO_RDY_SMPLE(x) _SB_GETVALUE(x,S_IO_RDY_SMPLE,M_IO_RDY_SMPLE) 155 156 157 /* 158 * Generic Bus Timing 1 Registers (Table 11-8) 159 */ 160 161 #define S_IO_ALE_TO_WRITE 0 162 #define M_IO_ALE_TO_WRITE _SB_MAKEMASK(3,S_IO_ALE_TO_WRITE) 163 #define V_IO_ALE_TO_WRITE(x) _SB_MAKEVALUE(x,S_IO_ALE_TO_WRITE) 164 #define G_IO_ALE_TO_WRITE(x) _SB_GETVALUE(x,S_IO_ALE_TO_WRITE,M_IO_ALE_TO_WRITE) 165 166 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ 167 || SIBYTE_HDR_FEATURE_CHIP(1480) 168 #define M_IO_RDY_SYNC _SB_MAKEMASK1(3) 169 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 170 171 #define S_IO_WRITE_WIDTH 4 172 #define M_IO_WRITE_WIDTH _SB_MAKEMASK(4,S_IO_WRITE_WIDTH) 173 #define V_IO_WRITE_WIDTH(x) _SB_MAKEVALUE(x,S_IO_WRITE_WIDTH) 174 #define G_IO_WRITE_WIDTH(x) _SB_GETVALUE(x,S_IO_WRITE_WIDTH,M_IO_WRITE_WIDTH) 175 176 #define S_IO_IDLE_CYCLE 8 177 #define M_IO_IDLE_CYCLE _SB_MAKEMASK(4,S_IO_IDLE_CYCLE) 178 #define V_IO_IDLE_CYCLE(x) _SB_MAKEVALUE(x,S_IO_IDLE_CYCLE) 179 #define G_IO_IDLE_CYCLE(x) _SB_GETVALUE(x,S_IO_IDLE_CYCLE,M_IO_IDLE_CYCLE) 180 181 #define S_IO_OE_TO_CS 12 182 #define M_IO_OE_TO_CS _SB_MAKEMASK(2,S_IO_OE_TO_CS) 183 #define V_IO_OE_TO_CS(x) _SB_MAKEVALUE(x,S_IO_OE_TO_CS) 184 #define G_IO_OE_TO_CS(x) _SB_GETVALUE(x,S_IO_OE_TO_CS,M_IO_OE_TO_CS) 185 186 #define S_IO_CS_TO_OE 14 187 #define M_IO_CS_TO_OE _SB_MAKEMASK(2,S_IO_CS_TO_OE) 188 #define V_IO_CS_TO_OE(x) _SB_MAKEVALUE(x,S_IO_CS_TO_OE) 189 #define G_IO_CS_TO_OE(x) _SB_GETVALUE(x,S_IO_CS_TO_OE,M_IO_CS_TO_OE) 190 191 /* 192 * Generic Bus Interrupt Status Register (Table 11-9) 193 */ 194 195 #define M_IO_CS_ERR_INT _SB_MAKEMASK(0,8) 196 #define M_IO_CS0_ERR_INT _SB_MAKEMASK1(0) 197 #define M_IO_CS1_ERR_INT _SB_MAKEMASK1(1) 198 #define M_IO_CS2_ERR_INT _SB_MAKEMASK1(2) 199 #define M_IO_CS3_ERR_INT _SB_MAKEMASK1(3) 200 #define M_IO_CS4_ERR_INT _SB_MAKEMASK1(4) 201 #define M_IO_CS5_ERR_INT _SB_MAKEMASK1(5) 202 #define M_IO_CS6_ERR_INT _SB_MAKEMASK1(6) 203 #define M_IO_CS7_ERR_INT _SB_MAKEMASK1(7) 204 205 #define M_IO_RD_PAR_INT _SB_MAKEMASK1(9) 206 #define M_IO_TIMEOUT_INT _SB_MAKEMASK1(10) 207 #define M_IO_ILL_ADDR_INT _SB_MAKEMASK1(11) 208 #define M_IO_MULT_CS_INT _SB_MAKEMASK1(12) 209 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 210 #define M_IO_COH_ERR _SB_MAKEMASK1(14) 211 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 212 213 214 /* 215 * Generic Bus Output Drive Control Register 0 (Table 14-18) 216 */ 217 218 #define S_IO_SLEW0 0 219 #define M_IO_SLEW0 _SB_MAKEMASK(2,S_IO_SLEW0) 220 #define V_IO_SLEW0(x) _SB_MAKEVALUE(x,S_IO_SLEW0) 221 #define G_IO_SLEW0(x) _SB_GETVALUE(x,S_IO_SLEW0,M_IO_SLEW0) 222 223 #define S_IO_DRV_A 2 224 #define M_IO_DRV_A _SB_MAKEMASK(2,S_IO_DRV_A) 225 #define V_IO_DRV_A(x) _SB_MAKEVALUE(x,S_IO_DRV_A) 226 #define G_IO_DRV_A(x) _SB_GETVALUE(x,S_IO_DRV_A,M_IO_DRV_A) 227 228 #define S_IO_DRV_B 6 229 #define M_IO_DRV_B _SB_MAKEMASK(2,S_IO_DRV_B) 230 #define V_IO_DRV_B(x) _SB_MAKEVALUE(x,S_IO_DRV_B) 231 #define G_IO_DRV_B(x) _SB_GETVALUE(x,S_IO_DRV_B,M_IO_DRV_B) 232 233 #define S_IO_DRV_C 10 234 #define M_IO_DRV_C _SB_MAKEMASK(2,S_IO_DRV_C) 235 #define V_IO_DRV_C(x) _SB_MAKEVALUE(x,S_IO_DRV_C) 236 #define G_IO_DRV_C(x) _SB_GETVALUE(x,S_IO_DRV_C,M_IO_DRV_C) 237 238 #define S_IO_DRV_D 14 239 #define M_IO_DRV_D _SB_MAKEMASK(2,S_IO_DRV_D) 240 #define V_IO_DRV_D(x) _SB_MAKEVALUE(x,S_IO_DRV_D) 241 #define G_IO_DRV_D(x) _SB_GETVALUE(x,S_IO_DRV_D,M_IO_DRV_D) 242 243 /* 244 * Generic Bus Output Drive Control Register 1 (Table 14-19) 245 */ 246 247 #define S_IO_DRV_E 2 248 #define M_IO_DRV_E _SB_MAKEMASK(2,S_IO_DRV_E) 249 #define V_IO_DRV_E(x) _SB_MAKEVALUE(x,S_IO_DRV_E) 250 #define G_IO_DRV_E(x) _SB_GETVALUE(x,S_IO_DRV_E,M_IO_DRV_E) 251 252 #define S_IO_DRV_F 6 253 #define M_IO_DRV_F _SB_MAKEMASK(2,S_IO_DRV_F) 254 #define V_IO_DRV_F(x) _SB_MAKEVALUE(x,S_IO_DRV_F) 255 #define G_IO_DRV_F(x) _SB_GETVALUE(x,S_IO_DRV_F,M_IO_DRV_F) 256 257 #define S_IO_SLEW1 8 258 #define M_IO_SLEW1 _SB_MAKEMASK(2,S_IO_SLEW1) 259 #define V_IO_SLEW1(x) _SB_MAKEVALUE(x,S_IO_SLEW1) 260 #define G_IO_SLEW1(x) _SB_GETVALUE(x,S_IO_SLEW1,M_IO_SLEW1) 261 262 #define S_IO_DRV_G 10 263 #define M_IO_DRV_G _SB_MAKEMASK(2,S_IO_DRV_G) 264 #define V_IO_DRV_G(x) _SB_MAKEVALUE(x,S_IO_DRV_G) 265 #define G_IO_DRV_G(x) _SB_GETVALUE(x,S_IO_DRV_G,M_IO_DRV_G) 266 267 #define S_IO_SLEW2 12 268 #define M_IO_SLEW2 _SB_MAKEMASK(2,S_IO_SLEW2) 269 #define V_IO_SLEW2(x) _SB_MAKEVALUE(x,S_IO_SLEW2) 270 #define G_IO_SLEW2(x) _SB_GETVALUE(x,S_IO_SLEW2,M_IO_SLEW2) 271 272 #define S_IO_DRV_H 14 273 #define M_IO_DRV_H _SB_MAKEMASK(2,S_IO_DRV_H) 274 #define V_IO_DRV_H(x) _SB_MAKEVALUE(x,S_IO_DRV_H) 275 #define G_IO_DRV_H(x) _SB_GETVALUE(x,S_IO_DRV_H,M_IO_DRV_H) 276 277 /* 278 * Generic Bus Output Drive Control Register 2 (Table 14-20) 279 */ 280 281 #define S_IO_DRV_J 2 282 #define M_IO_DRV_J _SB_MAKEMASK(2,S_IO_DRV_J) 283 #define V_IO_DRV_J(x) _SB_MAKEVALUE(x,S_IO_DRV_J) 284 #define G_IO_DRV_J(x) _SB_GETVALUE(x,S_IO_DRV_J,M_IO_DRV_J) 285 286 #define S_IO_DRV_K 6 287 #define M_IO_DRV_K _SB_MAKEMASK(2,S_IO_DRV_K) 288 #define V_IO_DRV_K(x) _SB_MAKEVALUE(x,S_IO_DRV_K) 289 #define G_IO_DRV_K(x) _SB_GETVALUE(x,S_IO_DRV_K,M_IO_DRV_K) 290 291 #define S_IO_DRV_L 10 292 #define M_IO_DRV_L _SB_MAKEMASK(2,S_IO_DRV_L) 293 #define V_IO_DRV_L(x) _SB_MAKEVALUE(x,S_IO_DRV_L) 294 #define G_IO_DRV_L(x) _SB_GETVALUE(x,S_IO_DRV_L,M_IO_DRV_L) 295 296 #define S_IO_DRV_M 14 297 #define M_IO_DRV_M _SB_MAKEMASK(2,S_IO_DRV_M) 298 #define V_IO_DRV_M(x) _SB_MAKEVALUE(x,S_IO_DRV_M) 299 #define G_IO_DRV_M(x) _SB_GETVALUE(x,S_IO_DRV_M,M_IO_DRV_M) 300 301 /* 302 * Generic Bus Output Drive Control Register 3 (Table 14-21) 303 */ 304 305 #define S_IO_SLEW3 0 306 #define M_IO_SLEW3 _SB_MAKEMASK(2,S_IO_SLEW3) 307 #define V_IO_SLEW3(x) _SB_MAKEVALUE(x,S_IO_SLEW3) 308 #define G_IO_SLEW3(x) _SB_GETVALUE(x,S_IO_SLEW3,M_IO_SLEW3) 309 310 #define S_IO_DRV_N 2 311 #define M_IO_DRV_N _SB_MAKEMASK(2,S_IO_DRV_N) 312 #define V_IO_DRV_N(x) _SB_MAKEVALUE(x,S_IO_DRV_N) 313 #define G_IO_DRV_N(x) _SB_GETVALUE(x,S_IO_DRV_N,M_IO_DRV_N) 314 315 #define S_IO_DRV_P 6 316 #define M_IO_DRV_P _SB_MAKEMASK(2,S_IO_DRV_P) 317 #define V_IO_DRV_P(x) _SB_MAKEVALUE(x,S_IO_DRV_P) 318 #define G_IO_DRV_P(x) _SB_GETVALUE(x,S_IO_DRV_P,M_IO_DRV_P) 319 320 #define S_IO_DRV_Q 10 321 #define M_IO_DRV_Q _SB_MAKEMASK(2,S_IO_DRV_Q) 322 #define V_IO_DRV_Q(x) _SB_MAKEVALUE(x,S_IO_DRV_Q) 323 #define G_IO_DRV_Q(x) _SB_GETVALUE(x,S_IO_DRV_Q,M_IO_DRV_Q) 324 325 #define S_IO_DRV_R 14 326 #define M_IO_DRV_R _SB_MAKEMASK(2,S_IO_DRV_R) 327 #define V_IO_DRV_R(x) _SB_MAKEVALUE(x,S_IO_DRV_R) 328 #define G_IO_DRV_R(x) _SB_GETVALUE(x,S_IO_DRV_R,M_IO_DRV_R) 329 330 331 /* 332 * PCMCIA configuration register (Table 12-6) 333 */ 334 335 #define M_PCMCIA_CFG_ATTRMEM _SB_MAKEMASK1(0) 336 #define M_PCMCIA_CFG_3VEN _SB_MAKEMASK1(1) 337 #define M_PCMCIA_CFG_5VEN _SB_MAKEMASK1(2) 338 #define M_PCMCIA_CFG_VPPEN _SB_MAKEMASK1(3) 339 #define M_PCMCIA_CFG_RESET _SB_MAKEMASK1(4) 340 #define M_PCMCIA_CFG_APWRONEN _SB_MAKEMASK1(5) 341 #define M_PCMCIA_CFG_CDMASK _SB_MAKEMASK1(6) 342 #define M_PCMCIA_CFG_WPMASK _SB_MAKEMASK1(7) 343 #define M_PCMCIA_CFG_RDYMASK _SB_MAKEMASK1(8) 344 #define M_PCMCIA_CFG_PWRCTL _SB_MAKEMASK1(9) 345 346 #if SIBYTE_HDR_FEATURE_CHIP(1480) 347 #define S_PCMCIA_MODE 16 348 #define M_PCMCIA_MODE _SB_MAKEMASK(3,S_PCMCIA_MODE) 349 #define V_PCMCIA_MODE(x) _SB_MAKEVALUE(x,S_PCMCIA_MODE) 350 #define G_PCMCIA_MODE(x) _SB_GETVALUE(x,S_PCMCIA_MODE,M_PCMCIA_MODE) 351 352 #define K_PCMCIA_MODE_PCMA_NOB 0 /* standard PCMCIA "A", no "B" */ 353 #define K_PCMCIA_MODE_IDEA_NOB 1 /* IDE "A", no "B" */ 354 #define K_PCMCIA_MODE_PCMIOA_NOB 2 /* PCMCIA with I/O "A", no "B" */ 355 #define K_PCMCIA_MODE_PCMA_PCMB 4 /* standard PCMCIA "A", standard PCMCIA "B" */ 356 #define K_PCMCIA_MODE_IDEA_PCMB 5 /* IDE "A", standard PCMCIA "B" */ 357 #define K_PCMCIA_MODE_PCMA_IDEB 6 /* standard PCMCIA "A", IDE "B" */ 358 #define K_PCMCIA_MODE_IDEA_IDEB 7 /* IDE "A", IDE "B" */ 359 #endif 360 361 362 /* 363 * PCMCIA status register (Table 12-7) 364 */ 365 366 #define M_PCMCIA_STATUS_CD1 _SB_MAKEMASK1(0) 367 #define M_PCMCIA_STATUS_CD2 _SB_MAKEMASK1(1) 368 #define M_PCMCIA_STATUS_VS1 _SB_MAKEMASK1(2) 369 #define M_PCMCIA_STATUS_VS2 _SB_MAKEMASK1(3) 370 #define M_PCMCIA_STATUS_WP _SB_MAKEMASK1(4) 371 #define M_PCMCIA_STATUS_RDY _SB_MAKEMASK1(5) 372 #define M_PCMCIA_STATUS_3VEN _SB_MAKEMASK1(6) 373 #define M_PCMCIA_STATUS_5VEN _SB_MAKEMASK1(7) 374 #define M_PCMCIA_STATUS_CDCHG _SB_MAKEMASK1(8) 375 #define M_PCMCIA_STATUS_WPCHG _SB_MAKEMASK1(9) 376 #define M_PCMCIA_STATUS_RDYCHG _SB_MAKEMASK1(10) 377 378 /* 379 * GPIO Interrupt Type Register (table 13-3) 380 */ 381 382 #define K_GPIO_INTR_DISABLE 0 383 #define K_GPIO_INTR_EDGE 1 384 #define K_GPIO_INTR_LEVEL 2 385 #define K_GPIO_INTR_SPLIT 3 386 387 #define S_GPIO_INTR_TYPEX(n) (((n)/2)*2) 388 #define M_GPIO_INTR_TYPEX(n) _SB_MAKEMASK(2,S_GPIO_INTR_TYPEX(n)) 389 #define V_GPIO_INTR_TYPEX(n,x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPEX(n)) 390 #define G_GPIO_INTR_TYPEX(n,x) _SB_GETVALUE(x,S_GPIO_INTR_TYPEX(n),M_GPIO_INTR_TYPEX(n)) 391 392 #define S_GPIO_INTR_TYPE0 0 393 #define M_GPIO_INTR_TYPE0 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE0) 394 #define V_GPIO_INTR_TYPE0(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE0) 395 #define G_GPIO_INTR_TYPE0(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE0,M_GPIO_INTR_TYPE0) 396 397 #define S_GPIO_INTR_TYPE2 2 398 #define M_GPIO_INTR_TYPE2 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE2) 399 #define V_GPIO_INTR_TYPE2(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE2) 400 #define G_GPIO_INTR_TYPE2(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE2,M_GPIO_INTR_TYPE2) 401 402 #define S_GPIO_INTR_TYPE4 4 403 #define M_GPIO_INTR_TYPE4 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE4) 404 #define V_GPIO_INTR_TYPE4(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE4) 405 #define G_GPIO_INTR_TYPE4(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE4,M_GPIO_INTR_TYPE4) 406 407 #define S_GPIO_INTR_TYPE6 6 408 #define M_GPIO_INTR_TYPE6 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE6) 409 #define V_GPIO_INTR_TYPE6(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE6) 410 #define G_GPIO_INTR_TYPE6(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE6,M_GPIO_INTR_TYPE6) 411 412 #define S_GPIO_INTR_TYPE8 8 413 #define M_GPIO_INTR_TYPE8 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE8) 414 #define V_GPIO_INTR_TYPE8(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE8) 415 #define G_GPIO_INTR_TYPE8(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE8,M_GPIO_INTR_TYPE8) 416 417 #define S_GPIO_INTR_TYPE10 10 418 #define M_GPIO_INTR_TYPE10 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE10) 419 #define V_GPIO_INTR_TYPE10(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE10) 420 #define G_GPIO_INTR_TYPE10(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE10,M_GPIO_INTR_TYPE10) 421 422 #define S_GPIO_INTR_TYPE12 12 423 #define M_GPIO_INTR_TYPE12 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE12) 424 #define V_GPIO_INTR_TYPE12(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE12) 425 #define G_GPIO_INTR_TYPE12(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE12,M_GPIO_INTR_TYPE12) 426 427 #define S_GPIO_INTR_TYPE14 14 428 #define M_GPIO_INTR_TYPE14 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE14) 429 #define V_GPIO_INTR_TYPE14(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE14) 430 #define G_GPIO_INTR_TYPE14(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE14,M_GPIO_INTR_TYPE14) 431 432 #if SIBYTE_HDR_FEATURE_CHIP(1480) 433 434 /* 435 * GPIO Interrupt Additional Type Register 436 */ 437 438 #define K_GPIO_INTR_BOTHEDGE 0 439 #define K_GPIO_INTR_RISEEDGE 1 440 #define K_GPIO_INTR_UNPRED1 2 441 #define K_GPIO_INTR_UNPRED2 3 442 443 #define S_GPIO_INTR_ATYPEX(n) (((n)/2)*2) 444 #define M_GPIO_INTR_ATYPEX(n) _SB_MAKEMASK(2,S_GPIO_INTR_ATYPEX(n)) 445 #define V_GPIO_INTR_ATYPEX(n,x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPEX(n)) 446 #define G_GPIO_INTR_ATYPEX(n,x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPEX(n),M_GPIO_INTR_ATYPEX(n)) 447 448 #define S_GPIO_INTR_ATYPE0 0 449 #define M_GPIO_INTR_ATYPE0 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE0) 450 #define V_GPIO_INTR_ATYPE0(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE0) 451 #define G_GPIO_INTR_ATYPE0(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE0,M_GPIO_INTR_ATYPE0) 452 453 #define S_GPIO_INTR_ATYPE2 2 454 #define M_GPIO_INTR_ATYPE2 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE2) 455 #define V_GPIO_INTR_ATYPE2(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE2) 456 #define G_GPIO_INTR_ATYPE2(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE2,M_GPIO_INTR_ATYPE2) 457 458 #define S_GPIO_INTR_ATYPE4 4 459 #define M_GPIO_INTR_ATYPE4 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE4) 460 #define V_GPIO_INTR_ATYPE4(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE4) 461 #define G_GPIO_INTR_ATYPE4(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE4,M_GPIO_INTR_ATYPE4) 462 463 #define S_GPIO_INTR_ATYPE6 6 464 #define M_GPIO_INTR_ATYPE6 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE6) 465 #define V_GPIO_INTR_ATYPE6(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE6) 466 #define G_GPIO_INTR_ATYPE6(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE6,M_GPIO_INTR_ATYPE6) 467 468 #define S_GPIO_INTR_ATYPE8 8 469 #define M_GPIO_INTR_ATYPE8 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE8) 470 #define V_GPIO_INTR_ATYPE8(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE8) 471 #define G_GPIO_INTR_ATYPE8(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE8,M_GPIO_INTR_ATYPE8) 472 473 #define S_GPIO_INTR_ATYPE10 10 474 #define M_GPIO_INTR_ATYPE10 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE10) 475 #define V_GPIO_INTR_ATYPE10(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE10) 476 #define G_GPIO_INTR_ATYPE10(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE10,M_GPIO_INTR_ATYPE10) 477 478 #define S_GPIO_INTR_ATYPE12 12 479 #define M_GPIO_INTR_ATYPE12 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE12) 480 #define V_GPIO_INTR_ATYPE12(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE12) 481 #define G_GPIO_INTR_ATYPE12(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE12,M_GPIO_INTR_ATYPE12) 482 483 #define S_GPIO_INTR_ATYPE14 14 484 #define M_GPIO_INTR_ATYPE14 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE14) 485 #define V_GPIO_INTR_ATYPE14(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE14) 486 #define G_GPIO_INTR_ATYPE14(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE14,M_GPIO_INTR_ATYPE14) 487 #endif 488 489 490 #endif 491
Indexes created Sun Sep 21 19:09:51 GMT 2025