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      1 /*	$NetBSD: pcireg.h,v 1.172 2024/12/31 14:00:35 skrll Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 1995, 1996, 1999, 2000
      5  *     Christopher G. Demetriou.  All rights reserved.
      6  * Copyright (c) 1994, 1996 Charles M. Hannum.  All rights reserved.
      7  *
      8  * Redistribution and use in source and binary forms, with or without
      9  * modification, are permitted provided that the following conditions
     10  * are met:
     11  * 1. Redistributions of source code must retain the above copyright
     12  *    notice, this list of conditions and the following disclaimer.
     13  * 2. Redistributions in binary form must reproduce the above copyright
     14  *    notice, this list of conditions and the following disclaimer in the
     15  *    documentation and/or other materials provided with the distribution.
     16  * 3. All advertising materials mentioning features or use of this software
     17  *    must display the following acknowledgement:
     18  *	This product includes software developed by Charles M. Hannum.
     19  * 4. The name of the author may not be used to endorse or promote products
     20  *    derived from this software without specific prior written permission.
     21  *
     22  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     24  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     25  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     26  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     27  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     28  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     29  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     31  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     32  */
     33 
     34 #ifndef _DEV_PCI_PCIREG_H_
     35 #define	_DEV_PCI_PCIREG_H_
     36 
     37 /*
     38  * Standardized PCI configuration information
     39  */
     40 
     41 /*
     42  * Size of each function's configuration space.
     43  */
     44 
     45 #define	PCI_CONF_SIZE		0x100
     46 #define	PCI_EXTCONF_SIZE	0x1000
     47 
     48 /*
     49  * Device identification register; contains a vendor ID and a device ID.
     50  */
     51 #define	PCI_ID_REG		0x00
     52 
     53 typedef uint16_t pci_vendor_id_t;
     54 typedef uint16_t pci_product_id_t;
     55 
     56 #define	PCI_VENDOR_SHIFT		0
     57 #define	PCI_VENDOR_MASK			0xffffU
     58 #define	PCI_VENDOR(id) \
     59 	    (((id) >> PCI_VENDOR_SHIFT) & PCI_VENDOR_MASK)
     60 
     61 #define	PCI_PRODUCT_SHIFT		16
     62 #define	PCI_PRODUCT_MASK		0xffffU
     63 #define	PCI_PRODUCT(id) \
     64 	    (((id) >> PCI_PRODUCT_SHIFT) & PCI_PRODUCT_MASK)
     65 
     66 #define PCI_ID_CODE(vid,pid)					\
     67 	((((vid) & PCI_VENDOR_MASK) << PCI_VENDOR_SHIFT) |	\
     68 	 (((pid) & PCI_PRODUCT_MASK) << PCI_PRODUCT_SHIFT))	\
     69 
     70 /*
     71  * Standard format of a PCI Type 0 Configuration Cycle address.
     72  */
     73 #define	PCI_CONF_TYPE0_IDSEL(d)		__BIT((d) + 11)
     74 #define	PCI_CONF_TYPE0_FUNCTION		__BITS(8,10)
     75 #define	PCI_CONF_TYPE0_OFFSET		__BITS(0,7)
     76 
     77 /*
     78  * Standard format of a PCI Type 1 Configuration Cycle address.
     79  */
     80 #define	PCI_CONF_TYPE1_BUS		__BITS(16,23)
     81 #define	PCI_CONF_TYPE1_DEVICE		__BITS(11,15)
     82 #define	PCI_CONF_TYPE1_FUNCTION		__BITS(8,10)
     83 #define	PCI_CONF_TYPE1_OFFSET		__BITS(0,7)
     84 
     85 /*
     86  * Command and status register.
     87  */
     88 #define	PCI_COMMAND_STATUS_REG	0x04
     89 #define	PCI_COMMAND_SHIFT		0
     90 #define	PCI_COMMAND_MASK		0xffff
     91 #define	PCI_STATUS_SHIFT		16
     92 #define	PCI_STATUS_MASK			0xffff
     93 
     94 #define PCI_COMMAND_STATUS_CODE(cmd,stat)			\
     95 	((((cmd) & PCI_COMMAND_MASK) << PCI_COMMAND_SHIFT) |	\
     96 	 (((stat) & PCI_STATUS_MASK) << PCI_STATUS_SHIFT))	\
     97 
     98 #define	PCI_COMMAND_IO_ENABLE		0x00000001
     99 #define	PCI_COMMAND_MEM_ENABLE		0x00000002
    100 #define	PCI_COMMAND_MASTER_ENABLE	0x00000004
    101 #define	PCI_COMMAND_SPECIAL_ENABLE	0x00000008
    102 #define	PCI_COMMAND_INVALIDATE_ENABLE	0x00000010
    103 #define	PCI_COMMAND_PALETTE_ENABLE	0x00000020
    104 #define	PCI_COMMAND_PARITY_ENABLE	0x00000040
    105 #define	PCI_COMMAND_STEPPING_ENABLE	0x00000080
    106 #define	PCI_COMMAND_SERR_ENABLE		0x00000100
    107 #define	PCI_COMMAND_BACKTOBACK_ENABLE	0x00000200
    108 #define	PCI_COMMAND_INTERRUPT_DISABLE	0x00000400
    109 
    110 #define	PCI_STATUS_IMMD_READNESS	__BIT(0+16)
    111 #define	PCI_STATUS_INT_STATUS		0x00080000
    112 #define	PCI_STATUS_CAPLIST_SUPPORT	0x00100000
    113 #define	PCI_STATUS_66MHZ_SUPPORT	0x00200000
    114 #define	PCI_STATUS_UDF_SUPPORT		0x00400000
    115 #define	PCI_STATUS_BACKTOBACK_SUPPORT	0x00800000
    116 #define	PCI_STATUS_PARITY_ERROR		0x01000000
    117 #define	PCI_STATUS_DEVSEL_FAST		0x00000000
    118 #define	PCI_STATUS_DEVSEL_MEDIUM	0x02000000
    119 #define	PCI_STATUS_DEVSEL_SLOW		0x04000000
    120 #define	PCI_STATUS_DEVSEL_MASK		0x06000000
    121 #define	PCI_STATUS_TARGET_TARGET_ABORT	0x08000000
    122 #define	PCI_STATUS_MASTER_TARGET_ABORT	0x10000000
    123 #define	PCI_STATUS_MASTER_ABORT		0x20000000
    124 #define	PCI_STATUS_SPECIAL_ERROR	0x40000000
    125 #define	PCI_STATUS_PARITY_DETECT	0x80000000
    126 
    127 /*
    128  * PCI Class and Revision Register; defines type and revision of device.
    129  */
    130 #define	PCI_CLASS_REG		0x08
    131 
    132 typedef uint8_t pci_class_t;
    133 typedef uint8_t pci_subclass_t;
    134 typedef uint8_t pci_interface_t;
    135 typedef uint8_t pci_revision_t;
    136 
    137 #define	PCI_CLASS_SHIFT			24
    138 #define	PCI_CLASS_MASK			0xffU
    139 #define	PCI_CLASS(cr) \
    140 	    (((cr) >> PCI_CLASS_SHIFT) & PCI_CLASS_MASK)
    141 
    142 #define	PCI_SUBCLASS_SHIFT		16
    143 #define	PCI_SUBCLASS_MASK		0xff
    144 #define	PCI_SUBCLASS(cr) \
    145 	    (((cr) >> PCI_SUBCLASS_SHIFT) & PCI_SUBCLASS_MASK)
    146 
    147 #define	PCI_INTERFACE_SHIFT		8
    148 #define	PCI_INTERFACE_MASK		0xff
    149 #define	PCI_INTERFACE(cr) \
    150 	    (((cr) >> PCI_INTERFACE_SHIFT) & PCI_INTERFACE_MASK)
    151 
    152 #define	PCI_REVISION_SHIFT		0
    153 #define	PCI_REVISION_MASK		0xff
    154 #define	PCI_REVISION(cr) \
    155 	    (((cr) >> PCI_REVISION_SHIFT) & PCI_REVISION_MASK)
    156 
    157 #define	PCI_CLASS_CODE(mainclass, subclass, interface) \
    158 	    ((((mainclass) & PCI_CLASS_MASK) << PCI_CLASS_SHIFT) | \
    159 	     (((subclass) & PCI_SUBCLASS_MASK) << PCI_SUBCLASS_SHIFT) | \
    160 	     (((interface) & PCI_INTERFACE_MASK) << PCI_INTERFACE_SHIFT))
    161 
    162 /* base classes */
    163 #define	PCI_CLASS_PREHISTORIC		0x00
    164 #define	PCI_CLASS_MASS_STORAGE		0x01
    165 #define	PCI_CLASS_NETWORK		0x02
    166 #define	PCI_CLASS_DISPLAY		0x03
    167 #define	PCI_CLASS_MULTIMEDIA		0x04
    168 #define	PCI_CLASS_MEMORY		0x05
    169 #define	PCI_CLASS_BRIDGE		0x06
    170 #define	PCI_CLASS_COMMUNICATIONS	0x07
    171 #define	PCI_CLASS_SYSTEM		0x08
    172 #define	PCI_CLASS_INPUT			0x09
    173 #define	PCI_CLASS_DOCK			0x0a
    174 #define	PCI_CLASS_PROCESSOR		0x0b
    175 #define	PCI_CLASS_SERIALBUS		0x0c
    176 #define	PCI_CLASS_WIRELESS		0x0d
    177 #define	PCI_CLASS_I2O			0x0e
    178 #define	PCI_CLASS_SATCOM		0x0f
    179 #define	PCI_CLASS_CRYPTO		0x10
    180 #define	PCI_CLASS_DASP			0x11
    181 #define	PCI_CLASS_ACCEL			0x12
    182 #define	PCI_CLASS_INSTRUMENT		0x13
    183 #define	PCI_CLASS_UNDEFINED		0xff
    184 
    185 /* 0x00 prehistoric subclasses */
    186 #define	PCI_SUBCLASS_PREHISTORIC_MISC		0x00
    187 #define	PCI_SUBCLASS_PREHISTORIC_VGA		0x01
    188 
    189 /* 0x01 mass storage subclasses */
    190 #define	PCI_SUBCLASS_MASS_STORAGE_SCSI		0x00
    191 #define		PCI_INTERFACE_SCSI_VND			0x00
    192 #define		PCI_INTERFACE_SCSI_PQI_STORAGE		0x11
    193 #define		PCI_INTERFACE_SCSI_PQI_CNTRL		0x12
    194 #define		PCI_INTERFACE_SCSI_PQI_STORAGE_CNTRL	0x13
    195 #define		PCI_INTERFACE_SCSI_NVME			0x21
    196 #define	PCI_SUBCLASS_MASS_STORAGE_IDE		0x01
    197 #define	PCI_SUBCLASS_MASS_STORAGE_FLOPPY	0x02
    198 #define	PCI_SUBCLASS_MASS_STORAGE_IPI		0x03
    199 #define	PCI_SUBCLASS_MASS_STORAGE_RAID		0x04
    200 #define	PCI_SUBCLASS_MASS_STORAGE_ATA		0x05
    201 #define		PCI_INTERFACE_ATA_SINGLEDMA		0x20
    202 #define		PCI_INTERFACE_ATA_CHAINEDDMA		0x30
    203 #define	PCI_SUBCLASS_MASS_STORAGE_SATA		0x06
    204 #define		PCI_INTERFACE_SATA_VND			0x00
    205 #define		PCI_INTERFACE_SATA_AHCI10		0x01
    206 #define		PCI_INTERFACE_SATA_SSBI			0x02
    207 #define	PCI_SUBCLASS_MASS_STORAGE_SAS		0x07
    208 #define	PCI_SUBCLASS_MASS_STORAGE_NVM		0x08
    209 #define		PCI_INTERFACE_NVM_VND			0x00
    210 #define		PCI_INTERFACE_NVM_NVMHCI10		0x01
    211 #define		PCI_INTERFACE_NVM_NVME_IO		0x02
    212 #define		PCI_INTERFACE_NVM_NVME_ADMIN		0x03
    213 #define	PCI_SUBCLASS_MASS_STORAGE_UFS		0x09
    214 #define		PCI_INTERFACE_UFS_VND			0x00
    215 #define		PCI_INTERFACE_UFS_UFSHCI		0x01
    216 #define	PCI_SUBCLASS_MASS_STORAGE_MISC		0x80
    217 
    218 /* 0x02 network subclasses */
    219 #define	PCI_SUBCLASS_NETWORK_ETHERNET		0x00
    220 #define	PCI_SUBCLASS_NETWORK_TOKENRING		0x01
    221 #define	PCI_SUBCLASS_NETWORK_FDDI		0x02
    222 #define	PCI_SUBCLASS_NETWORK_ATM		0x03
    223 #define	PCI_SUBCLASS_NETWORK_ISDN		0x04
    224 #define	PCI_SUBCLASS_NETWORK_WORLDFIP		0x05
    225 #define	PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP	0x06
    226 #define	PCI_SUBCLASS_NETWORK_INFINIBAND		0x07
    227 #define	PCI_SUBCLASS_NETWORK_HFC		0x08
    228 #define	PCI_SUBCLASS_NETWORK_MISC		0x80
    229 
    230 /* 0x03 display subclasses */
    231 #define	PCI_SUBCLASS_DISPLAY_VGA		0x00
    232 #define		PCI_INTERFACE_VGA_VGA			0x00
    233 #define		PCI_INTERFACE_VGA_8514			0x01
    234 #define	PCI_SUBCLASS_DISPLAY_XGA		0x01
    235 #define	PCI_SUBCLASS_DISPLAY_3D			0x02
    236 #define	PCI_SUBCLASS_DISPLAY_MISC		0x80
    237 
    238 /* 0x04 multimedia subclasses */
    239 #define	PCI_SUBCLASS_MULTIMEDIA_VIDEO		0x00
    240 #define	PCI_SUBCLASS_MULTIMEDIA_AUDIO		0x01
    241 #define	PCI_SUBCLASS_MULTIMEDIA_TELEPHONY	0x02
    242 #define	PCI_SUBCLASS_MULTIMEDIA_HDAUDIO		0x03
    243 #define		PCI_INTERFACE_HDAUDIO			0x00
    244 #define		PCI_INTERFACE_HDAUDIO_VND		0x80
    245 #define	PCI_SUBCLASS_MULTIMEDIA_MISC		0x80
    246 
    247 /* 0x05 memory subclasses */
    248 #define	PCI_SUBCLASS_MEMORY_RAM			0x00
    249 #define	PCI_SUBCLASS_MEMORY_FLASH		0x01
    250 #define	PCI_SUBCLASS_MEMORY_MISC		0x80
    251 
    252 /* 0x06 bridge subclasses */
    253 #define	PCI_SUBCLASS_BRIDGE_HOST		0x00
    254 #define	PCI_SUBCLASS_BRIDGE_ISA			0x01
    255 #define	PCI_SUBCLASS_BRIDGE_EISA		0x02
    256 #define	PCI_SUBCLASS_BRIDGE_MC			0x03	/* XXX _MCA */
    257 #define	PCI_SUBCLASS_BRIDGE_PCI			0x04
    258 #define		PCI_INTERFACE_BRIDGE_PCI_PCI		0x00
    259 #define		PCI_INTERFACE_BRIDGE_PCI_SUBDEC		0x01
    260 #define	PCI_SUBCLASS_BRIDGE_PCMCIA		0x05
    261 #define	PCI_SUBCLASS_BRIDGE_NUBUS		0x06
    262 #define	PCI_SUBCLASS_BRIDGE_CARDBUS		0x07
    263 #define	PCI_SUBCLASS_BRIDGE_RACEWAY		0x08
    264 		/* bit0 == 0 ? "transparent mode" : "endpoint mode" */
    265 #define	PCI_SUBCLASS_BRIDGE_STPCI		0x09
    266 #define		PCI_INTERFACE_STPCI_PRIMARY		0x40
    267 #define		PCI_INTERFACE_STPCI_SECONDARY		0x80
    268 #define	PCI_SUBCLASS_BRIDGE_INFINIBAND		0x0a
    269 #define	PCI_SUBCLASS_BRIDGE_ADVSW		0x0b
    270 #define		PCI_INTERFACE_ADVSW_CUSTOM		0x00
    271 #define		PCI_INTERFACE_ADVSW_ASISIG		0x01
    272 #define	PCI_SUBCLASS_BRIDGE_MISC		0x80
    273 
    274 /* 0x07 communications subclasses */
    275 #define	PCI_SUBCLASS_COMMUNICATIONS_SERIAL	0x00
    276 #define		PCI_INTERFACE_SERIAL_XT			0x00
    277 #define		PCI_INTERFACE_SERIAL_16450		0x01
    278 #define		PCI_INTERFACE_SERIAL_16550		0x02
    279 #define		PCI_INTERFACE_SERIAL_16650		0x03
    280 #define		PCI_INTERFACE_SERIAL_16750		0x04
    281 #define		PCI_INTERFACE_SERIAL_16850		0x05
    282 #define		PCI_INTERFACE_SERIAL_16950		0x06
    283 #define	PCI_SUBCLASS_COMMUNICATIONS_PARALLEL	0x01
    284 #define		PCI_INTERFACE_PARALLEL			0x00
    285 #define		PCI_INTERFACE_PARALLEL_BIDIRECTIONAL	0x01
    286 #define		PCI_INTERFACE_PARALLEL_ECP1X		0x02
    287 #define		PCI_INTERFACE_PARALLEL_IEEE1284_CNTRL	0x03
    288 #define		PCI_INTERFACE_PARALLEL_IEEE1284_TGT	0xfe
    289 #define	PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL	0x02
    290 #define	PCI_SUBCLASS_COMMUNICATIONS_MODEM	0x03
    291 #define		PCI_INTERFACE_MODEM			0x00
    292 #define		PCI_INTERFACE_MODEM_HAYES16450		0x01
    293 #define		PCI_INTERFACE_MODEM_HAYES16550		0x02
    294 #define		PCI_INTERFACE_MODEM_HAYES16650		0x03
    295 #define		PCI_INTERFACE_MODEM_HAYES16750		0x04
    296 #define	PCI_SUBCLASS_COMMUNICATIONS_GPIB	0x04
    297 #define	PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD	0x05
    298 #define	PCI_SUBCLASS_COMMUNICATIONS_MISC	0x80
    299 
    300 /* 0x08 system subclasses */
    301 #define	PCI_SUBCLASS_SYSTEM_PIC			0x00
    302 #define		PCI_INTERFACE_PIC_8259			0x00
    303 #define		PCI_INTERFACE_PIC_ISA			0x01
    304 #define		PCI_INTERFACE_PIC_EISA			0x02
    305 #define		PCI_INTERFACE_PIC_IOAPIC		0x10
    306 #define		PCI_INTERFACE_PIC_IOXAPIC		0x20
    307 #define	PCI_SUBCLASS_SYSTEM_DMA			0x01
    308 #define		PCI_INTERFACE_DMA_8237			0x00
    309 #define		PCI_INTERFACE_DMA_ISA			0x01
    310 #define		PCI_INTERFACE_DMA_EISA			0x02
    311 #define	PCI_SUBCLASS_SYSTEM_TIMER		0x02
    312 #define		PCI_INTERFACE_TIMER_8254		0x00
    313 #define		PCI_INTERFACE_TIMER_ISA			0x01
    314 #define		PCI_INTERFACE_TIMER_EISA		0x02
    315 #define		PCI_INTERFACE_TIMER_HPET		0x03
    316 #define	PCI_SUBCLASS_SYSTEM_RTC			0x03
    317 #define		PCI_INTERFACE_RTC_GENERIC		0x00
    318 #define		PCI_INTERFACE_RTC_ISA			0x01
    319 #define	PCI_SUBCLASS_SYSTEM_PCIHOTPLUG		0x04
    320 #define	PCI_SUBCLASS_SYSTEM_SDHC		0x05
    321 #define	PCI_SUBCLASS_SYSTEM_IOMMU		0x06 /* or RCEC in old spec */
    322 #define	PCI_SUBCLASS_SYSTEM_RCEC		0x07
    323 #define	PCI_SUBCLASS_SYSTEM_MISC		0x80
    324 
    325 /* 0x09 input subclasses */
    326 #define	PCI_SUBCLASS_INPUT_KEYBOARD		0x00
    327 #define	PCI_SUBCLASS_INPUT_DIGITIZER		0x01
    328 #define	PCI_SUBCLASS_INPUT_MOUSE		0x02
    329 #define	PCI_SUBCLASS_INPUT_SCANNER		0x03
    330 #define	PCI_SUBCLASS_INPUT_GAMEPORT		0x04
    331 #define		PCI_INTERFACE_GAMEPORT_GENERIC		0x00
    332 #define		PCI_INTERFACE_GAMEPORT_LEGACY		0x10
    333 #define	PCI_SUBCLASS_INPUT_MISC			0x80
    334 
    335 /* 0x0a dock subclasses */
    336 #define	PCI_SUBCLASS_DOCK_GENERIC		0x00
    337 #define	PCI_SUBCLASS_DOCK_MISC			0x80
    338 
    339 /* 0x0b processor subclasses */
    340 #define	PCI_SUBCLASS_PROCESSOR_386		0x00
    341 #define	PCI_SUBCLASS_PROCESSOR_486		0x01
    342 #define	PCI_SUBCLASS_PROCESSOR_PENTIUM		0x02
    343 #define	PCI_SUBCLASS_PROCESSOR_ALPHA		0x10
    344 #define	PCI_SUBCLASS_PROCESSOR_POWERPC		0x20
    345 #define	PCI_SUBCLASS_PROCESSOR_MIPS		0x30
    346 #define	PCI_SUBCLASS_PROCESSOR_COPROC		0x40
    347 #define	PCI_SUBCLASS_PROCESSOR_MISC		0x80
    348 
    349 /* 0x0c serial bus subclasses */
    350 #define	PCI_SUBCLASS_SERIALBUS_FIREWIRE		0x00
    351 #define		PCI_INTERFACE_IEEE1394_FIREWIRE		0x00
    352 #define		PCI_INTERFACE_IEEE1394_OPENHCI		0x10
    353 #define	PCI_SUBCLASS_SERIALBUS_ACCESS		0x01
    354 #define	PCI_SUBCLASS_SERIALBUS_SSA		0x02
    355 #define	PCI_SUBCLASS_SERIALBUS_USB		0x03
    356 #define		PCI_INTERFACE_USB_UHCI			0x00
    357 #define		PCI_INTERFACE_USB_OHCI			0x10
    358 #define		PCI_INTERFACE_USB_EHCI			0x20
    359 #define		PCI_INTERFACE_USB_XHCI			0x30
    360 #define		PCI_INTERFACE_USB_USB4HCI		0x40
    361 #define		PCI_INTERFACE_USB_OTHERHC		0x80
    362 #define		PCI_INTERFACE_USB_DEVICE		0xfe
    363 #define	PCI_SUBCLASS_SERIALBUS_FIBER		0x04	/* XXX _FIBRECHANNEL */
    364 #define	PCI_SUBCLASS_SERIALBUS_SMBUS		0x05
    365 #define	PCI_SUBCLASS_SERIALBUS_INFINIBAND	0x06	/* Deprecated */
    366 #define	PCI_SUBCLASS_SERIALBUS_IPMI		0x07
    367 #define		PCI_INTERFACE_IPMI_SMIC			0x00
    368 #define		PCI_INTERFACE_IPMI_KBD			0x01
    369 #define		PCI_INTERFACE_IPMI_BLOCKXFER		0x02
    370 #define	PCI_SUBCLASS_SERIALBUS_SERCOS		0x08
    371 #define	PCI_SUBCLASS_SERIALBUS_CANBUS		0x09
    372 #define	PCI_SUBCLASS_SERIALBUS_MIPI_I3C		0x0a
    373 #define	PCI_SUBCLASS_SERIALBUS_MISC		0x80
    374 
    375 /* 0x0d wireless subclasses */
    376 #define	PCI_SUBCLASS_WIRELESS_IRDA		0x00
    377 #define	PCI_SUBCLASS_WIRELESS_CONSUMERIR	0x01
    378 #define		PCI_INTERFACE_CONSUMERIR		0x00
    379 #define		PCI_INTERFACE_UWB			0x10
    380 #define	PCI_SUBCLASS_WIRELESS_RF		0x10
    381 #define	PCI_SUBCLASS_WIRELESS_BLUETOOTH		0x11
    382 #define	PCI_SUBCLASS_WIRELESS_BROADBAND		0x12
    383 #define	PCI_SUBCLASS_WIRELESS_802_11A		0x20
    384 #define	PCI_SUBCLASS_WIRELESS_802_11B		0x21
    385 #define	PCI_SUBCLASS_WIRELESS_CELL		0x40
    386 #define	PCI_SUBCLASS_WIRELESS_CELL_E		0x41
    387 #define	PCI_SUBCLASS_WIRELESS_MISC		0x80
    388 
    389 /* 0x0e I2O (Intelligent I/O) subclasses */
    390 #define	PCI_SUBCLASS_I2O_STANDARD		0x00
    391 #define		PCI_INTERFACE_I2O_FIFOAT40		0x00
    392 		/* others for I2O spec */
    393 #define	PCI_SUBCLASS_I2O_MISC			0x80
    394 
    395 /* 0x0f satellite communication subclasses */
    396 /*	PCI_SUBCLASS_SATCOM_???			0x00	/ * XXX ??? */
    397 #define	PCI_SUBCLASS_SATCOM_TV			0x01
    398 #define	PCI_SUBCLASS_SATCOM_AUDIO		0x02
    399 #define	PCI_SUBCLASS_SATCOM_VOICE		0x03
    400 #define	PCI_SUBCLASS_SATCOM_DATA		0x04
    401 #define	PCI_SUBCLASS_SATCOM_MISC		0x80
    402 
    403 /* 0x10 encryption/decryption subclasses */
    404 #define	PCI_SUBCLASS_CRYPTO_NETCOMP		0x00
    405 #define	PCI_SUBCLASS_CRYPTO_ENTERTAINMENT	0x10
    406 #define	PCI_SUBCLASS_CRYPTO_MISC		0x80
    407 
    408 /* 0x11 data acquisition and signal processing subclasses */
    409 #define	PCI_SUBCLASS_DASP_DPIO			0x00
    410 #define	PCI_SUBCLASS_DASP_TIMEFREQ		0x01 /* performance counters */
    411 #define	PCI_SUBCLASS_DASP_SYNC			0x10
    412 #define	PCI_SUBCLASS_DASP_MGMT			0x20
    413 #define	PCI_SUBCLASS_DASP_MISC			0x80
    414 
    415 /*
    416  * PCI BIST/Header Type/Latency Timer/Cache Line Size Register.
    417  */
    418 #define	PCI_BHLC_REG		0x0c
    419 
    420 #define	PCI_BIST_SHIFT			24
    421 #define	PCI_BIST_MASK			0xff
    422 #define	PCI_BIST(bhlcr) \
    423 	    (((bhlcr) >> PCI_BIST_SHIFT) & PCI_BIST_MASK)
    424 
    425 #define	PCI_HDRTYPE_SHIFT		16
    426 #define	PCI_HDRTYPE_MASK		0xff
    427 #define	PCI_HDRTYPE(bhlcr) \
    428 	    (((bhlcr) >> PCI_HDRTYPE_SHIFT) & PCI_HDRTYPE_MASK)
    429 
    430 #define	PCI_HDRTYPE_TYPE(bhlcr) \
    431 	    (PCI_HDRTYPE(bhlcr) & 0x7f)
    432 #define	PCI_HDRTYPE_MULTIFN(bhlcr) \
    433 	    ((PCI_HDRTYPE(bhlcr) & 0x80) != 0)
    434 
    435 #define	PCI_LATTIMER_SHIFT		8
    436 #define	PCI_LATTIMER_MASK		0xff
    437 #define	PCI_LATTIMER(bhlcr) \
    438 	    (((bhlcr) >> PCI_LATTIMER_SHIFT) & PCI_LATTIMER_MASK)
    439 
    440 #define	PCI_CACHELINE_SHIFT		0
    441 #define	PCI_CACHELINE_MASK		0xff
    442 #define	PCI_CACHELINE(bhlcr) \
    443 	    (((bhlcr) >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK)
    444 
    445 #define PCI_BHLC_CODE(bist,type,multi,latency,cacheline)		\
    446 	    ((((bist) & PCI_BIST_MASK) << PCI_BIST_SHIFT) |		\
    447 	     (((type) & PCI_HDRTYPE_MASK) << PCI_HDRTYPE_SHIFT) |	\
    448 	     (((multi)?0x80:0) << PCI_HDRTYPE_SHIFT) |			\
    449 	     (((latency) & PCI_LATTIMER_MASK) << PCI_LATTIMER_SHIFT) |	\
    450 	     (((cacheline) & PCI_CACHELINE_MASK) << PCI_CACHELINE_SHIFT))
    451 
    452 /*
    453  * PCI header type
    454  */
    455 #define PCI_HDRTYPE_DEVICE	0	/* PCI/PCIX/Cardbus */
    456 #define PCI_HDRTYPE_PPB		1	/* PCI/PCIX/Cardbus */
    457 #define PCI_HDRTYPE_PCB		2	/* PCI/PCIX/Cardbus */
    458 #define PCI_HDRTYPE_EP		0	/* PCI Express */
    459 #define PCI_HDRTYPE_RC		1	/* PCI Express */
    460 
    461 
    462 /*
    463  * Mapping registers
    464  */
    465 #define	PCI_MAPREG_START	0x10
    466 #define	PCI_MAPREG_END		0x28
    467 #define	PCI_MAPREG_ROM		0x30
    468 #define	PCI_MAPREG_PPB_END	0x18
    469 #define	PCI_MAPREG_PCB_END	0x14
    470 
    471 #define PCI_BAR0		0x10
    472 #define PCI_BAR1		0x14
    473 #define PCI_BAR2		0x18
    474 #define PCI_BAR3		0x1C
    475 #define PCI_BAR4		0x20
    476 #define PCI_BAR5		0x24
    477 
    478 #define	PCI_BAR(n)		(PCI_MAPREG_START + 4 * (n))
    479 
    480 #define	PCI_MAPREG_TYPE(mr)						\
    481 	    ((mr) & PCI_MAPREG_TYPE_MASK)
    482 #define	PCI_MAPREG_TYPE_MASK		0x00000001
    483 
    484 #define	PCI_MAPREG_TYPE_MEM		0x00000000
    485 #define	PCI_MAPREG_TYPE_ROM		0x00000000
    486 #define	PCI_MAPREG_TYPE_IO		0x00000001
    487 #define	PCI_MAPREG_ROM_ENABLE		0x00000001
    488 
    489 #define	PCI_MAPREG_MEM_TYPE(mr)						\
    490 	    ((mr) & PCI_MAPREG_MEM_TYPE_MASK)
    491 #define	PCI_MAPREG_MEM_TYPE_MASK	0x00000006
    492 
    493 #define	PCI_MAPREG_MEM_TYPE_32BIT	0x00000000
    494 #define	PCI_MAPREG_MEM_TYPE_32BIT_1M	0x00000002
    495 #define	PCI_MAPREG_MEM_TYPE_64BIT	0x00000004
    496 
    497 #define	PCI_MAPREG_MEM_PREFETCHABLE(mr)				\
    498 	    (((mr) & PCI_MAPREG_MEM_PREFETCHABLE_MASK) != 0)
    499 #define	PCI_MAPREG_MEM_PREFETCHABLE_MASK 0x00000008
    500 
    501 #define	PCI_MAPREG_MEM_ADDR(mr)						\
    502 	    ((mr) & PCI_MAPREG_MEM_ADDR_MASK)
    503 #define	PCI_MAPREG_MEM_SIZE(mr)						\
    504 	    (PCI_MAPREG_MEM_ADDR(mr) & -PCI_MAPREG_MEM_ADDR(mr))
    505 #define	PCI_MAPREG_MEM_ADDR_MASK	0xfffffff0
    506 
    507 #define	PCI_MAPREG_MEM64_ADDR(mr)					\
    508 	    ((mr) & PCI_MAPREG_MEM64_ADDR_MASK)
    509 #define	PCI_MAPREG_MEM64_SIZE(mr)					\
    510 	    (PCI_MAPREG_MEM64_ADDR(mr) & -PCI_MAPREG_MEM64_ADDR(mr))
    511 #define	PCI_MAPREG_MEM64_ADDR_MASK	0xfffffffffffffff0ULL
    512 
    513 #define	PCI_MAPREG_IO_ADDR(mr)						\
    514 	    ((mr) & PCI_MAPREG_IO_ADDR_MASK)
    515 #define	PCI_MAPREG_IO_SIZE(mr)						\
    516 	    (PCI_MAPREG_IO_ADDR(mr) & -PCI_MAPREG_IO_ADDR(mr))
    517 #define	PCI_MAPREG_IO_ADDR_MASK		0xfffffffc
    518 
    519 #define	PCI_MAPREG_ROM_ADDR(mr)						\
    520 	    ((mr) & PCI_MAPREG_ROM_ADDR_MASK)
    521 #define	PCI_MAPREG_ROM_VALID_STAT   __BITS(3, 1) /* Validation Status */
    522 #define	PCI_MAPREG_ROM_VSTAT_NOTSUPP	0x0 /* Validation not supported */
    523 #define	PCI_MAPREG_ROM_VSTAT_INPROG	0x1 /* Validation in Progress */
    524 #define	PCI_MAPREG_ROM_VSTAT_VPASS	0x2 /* Valid contnt, trust test nperf*/
    525 #define	PCI_MAPREG_ROM_VSTAT_VPASSTRUST	0x3 /* Valid and trusted contents */
    526 #define	PCI_MAPREG_ROM_VSTAT_VFAIL	0x4 /* Invalid contents */
    527 #define	PCI_MAPREG_ROM_VSTAT_VFAILUNTRUST 0x5 /* Valid but untrusted contents */
    528 #define	PCI_MAPREG_ROM_VSTAT_WPASS	0x6 /* VPASS + warning */
    529 #define	PCI_MAPREG_ROM_VSTAT_WPASSTRUST	0x7 /* VPASSTRUST + warning */
    530 #define	PCI_MAPREG_ROM_VALID_DETAIL __BITS(7, 4) /* Validation Details */
    531 #define	PCI_MAPREG_ROM_ADDR_MASK	__BITS(31, 11)
    532 
    533 #define PCI_MAPREG_SIZE_TO_MASK(size)					\
    534 	    (-(size))
    535 
    536 #define PCI_MAPREG_NUM(offset)						\
    537 	    (((unsigned)(offset)-PCI_MAPREG_START)/4)
    538 
    539 
    540 /*
    541  * Cardbus CIS pointer (PCI rev. 2.1)
    542  */
    543 #define PCI_CARDBUS_CIS_REG	0x28
    544 
    545 /*
    546  * Subsystem identification register; contains a vendor ID and a device ID.
    547  * Types/macros for PCI_ID_REG apply.
    548  * (PCI rev. 2.1)
    549  */
    550 #define PCI_SUBSYS_ID_REG	0x2c
    551 
    552 #define	PCI_SUBSYS_VENDOR_MASK		__BITS(15, 0)
    553 #define	PCI_SUBSYS_ID_MASK		__BITS(31, 16)
    554 
    555 #define	PCI_SUBSYS_VENDOR(__subsys_id)	\
    556     __SHIFTOUT(__subsys_id, PCI_SUBSYS_VENDOR_MASK)
    557 
    558 #define	PCI_SUBSYS_ID(__subsys_id)	\
    559     __SHIFTOUT(__subsys_id, PCI_SUBSYS_ID_MASK)
    560 
    561 /*
    562  * Capabilities link list (PCI rev. 2.2)
    563  */
    564 #define	PCI_CAPLISTPTR_REG	0x34	/* header type 0 */
    565 #define	PCI_CARDBUS_CAPLISTPTR_REG 0x14	/* header type 2 */
    566 #define	PCI_CAPLIST_PTR(cpr)	((cpr) & 0xff)
    567 #define	PCI_CAPLIST_NEXT(cr)	(((cr) >> 8) & 0xff)
    568 #define	PCI_CAPLIST_CAP(cr)	((cr) & 0xff)
    569 
    570 #define	PCI_CAP_RESERVED0	0x00
    571 #define	PCI_CAP_PWRMGMT		0x01
    572 #define	PCI_CAP_AGP		0x02
    573 #define	PCI_CAP_VPD		0x03
    574 #define	PCI_CAP_SLOTID		0x04
    575 #define	PCI_CAP_MSI		0x05
    576 #define	PCI_CAP_CPCI_HOTSWAP	0x06
    577 #define	PCI_CAP_PCIX		0x07
    578 #define	PCI_CAP_LDT		0x08	/* HyperTransport */
    579 #define	PCI_CAP_VENDSPEC	0x09
    580 #define	PCI_CAP_DEBUGPORT	0x0a
    581 #define	PCI_CAP_CPCI_RSRCCTL	0x0b
    582 #define	PCI_CAP_HOTPLUG		0x0c	/* Standard Hot-Plug Controller(SHPC)*/
    583 #define	PCI_CAP_SUBVENDOR	0x0d
    584 #define	PCI_CAP_AGP8		0x0e
    585 #define	PCI_CAP_SECURE		0x0f
    586 #define	PCI_CAP_PCIEXPRESS	0x10
    587 #define	PCI_CAP_MSIX		0x11
    588 #define	PCI_CAP_SATA		0x12
    589 #define	PCI_CAP_PCIAF		0x13
    590 #define	PCI_CAP_EA		0x14	/* Enhanced Allocation (EA) */
    591 #define	PCI_CAP_FPB		0x15	/* Flattening Portal Bridge (FPB) */
    592 
    593 /*
    594  * Capability ID: 0x01
    595  * Power Management Capability; access via capability pointer.
    596  */
    597 
    598 /* Power Management Capability Register */
    599 #define PCI_PMCR		0x02
    600 #define PCI_PMCR_SHIFT		16
    601 #define PCI_PMCR_VERSION_MASK	0x0007
    602 #define PCI_PMCR_VERSION_10	0x0001
    603 #define PCI_PMCR_VERSION_11	0x0002
    604 #define PCI_PMCR_VERSION_12	0x0003
    605 #define PCI_PMCR_PME_CLOCK	0x0008
    606 #define PCI_PMCR_DSI		0x0020
    607 #define PCI_PMCR_AUXCUR_MASK	0x01c0
    608 #define PCI_PMCR_AUXCUR_0	0x0000
    609 #define PCI_PMCR_AUXCUR_55	0x0040
    610 #define PCI_PMCR_AUXCUR_100	0x0080
    611 #define PCI_PMCR_AUXCUR_160	0x00c0
    612 #define PCI_PMCR_AUXCUR_220	0x0100
    613 #define PCI_PMCR_AUXCUR_270	0x0140
    614 #define PCI_PMCR_AUXCUR_320	0x0180
    615 #define PCI_PMCR_AUXCUR_375	0x01c0
    616 #define PCI_PMCR_D1SUPP		0x0200
    617 #define PCI_PMCR_D2SUPP		0x0400
    618 #define PCI_PMCR_PME_D0		0x0800
    619 #define PCI_PMCR_PME_D1		0x1000
    620 #define PCI_PMCR_PME_D2		0x2000
    621 #define PCI_PMCR_PME_D3HOT	0x4000
    622 #define PCI_PMCR_PME_D3COLD	0x8000
    623 /*
    624  * Power Management Control Status Register, Bridge Support Extensions Register
    625  * and Data Register.
    626  */
    627 #define PCI_PMCSR		0x04
    628 #define PCI_PMCSR_STATE_MASK	0x00000003
    629 #define PCI_PMCSR_STATE_D0	0x00000000
    630 #define PCI_PMCSR_STATE_D1	0x00000001
    631 #define PCI_PMCSR_STATE_D2	0x00000002
    632 #define PCI_PMCSR_STATE_D3	0x00000003
    633 #define PCI_PMCSR_NO_SOFTRST	0x00000008
    634 #define	PCI_PMCSR_PME_EN	0x00000100
    635 #define PCI_PMCSR_DATASEL_MASK	0x00001e00
    636 #define PCI_PMCSR_DATASCL_MASK	0x00006000
    637 #define PCI_PMCSR_PME_STS	0x00008000 /* PME Status (R/W1C) */
    638 #define PCI_PMCSR_B2B3_SUPPORT	0x00400000
    639 #define PCI_PMCSR_BPCC_EN	0x00800000
    640 #define PCI_PMCSR_DATA		0xff000000
    641 
    642 
    643 /*
    644  * Capability ID: 0x02
    645  * AGP
    646  */
    647 #define PCI_CAP_AGP_MAJOR(cr)	(((cr) >> 20) & 0xf)
    648 #define PCI_CAP_AGP_MINOR(cr)	(((cr) >> 16) & 0xf)
    649 #define PCI_AGP_STATUS		0x04
    650 #define PCI_AGP_COMMAND		0x08
    651 /* Definitions for STATUS and COMMAND register bits */
    652 #define AGP_MODE_RQ		__BITS(31, 24)
    653 #define AGP_MODE_ARQSZ		__BITS(15, 13)
    654 #define AGP_MODE_CAL		__BITS(12, 10)
    655 #define AGP_MODE_SBA		__BIT(9)
    656 #define AGP_MODE_AGP		__BIT(8)
    657 #define AGP_MODE_HTRANS		__BIT(6)
    658 #define AGP_MODE_4G		__BIT(5)
    659 #define AGP_MODE_FW		__BIT(4)
    660 #define AGP_MODE_MODE_3		__BIT(3)
    661 #define AGP_MODE_RATE		__BITS(2, 0)
    662 #define AGP_MODE_V2_RATE_1x		0x1
    663 #define AGP_MODE_V2_RATE_2x		0x2
    664 #define AGP_MODE_V2_RATE_4x		0x4
    665 #define AGP_MODE_V3_RATE_4x		0x1
    666 #define AGP_MODE_V3_RATE_8x		0x2
    667 #define AGP_MODE_V3_RATE_RSVD		0x4
    668 
    669 
    670 /*
    671  * Capability ID: 0x03
    672  * Vital Product Data; access via capability pointer (PCI rev 2.2).
    673  */
    674 #define	PCI_VPD_ADDRESS_MASK	0x7fff
    675 #define	PCI_VPD_ADDRESS_SHIFT	16
    676 #define	PCI_VPD_ADDRESS(ofs)	\
    677 	(((ofs) & PCI_VPD_ADDRESS_MASK) << PCI_VPD_ADDRESS_SHIFT)
    678 #define	PCI_VPD_DATAREG(ofs)	((ofs) + 4)
    679 #define	PCI_VPD_OPFLAG		0x80000000
    680 
    681 /*
    682  * Capability ID: 0x04
    683  * Slot ID
    684  */
    685 
    686 /*
    687  * Capability ID: 0x05
    688  * MSI
    689  */
    690 
    691 #define	PCI_MSI_CTL		0x0	/* Message Control Register offset */
    692 #define	PCI_MSI_MADDR		0x4	/* Message Address Register (least
    693 					 * significant bits) offset
    694 					 */
    695 #define	PCI_MSI_MADDR64_LO	0x4	/* 64-bit Message Address Register
    696 					 * (least significant bits) offset
    697 					 */
    698 #define	PCI_MSI_MADDR64_HI	0x8	/* 64-bit Message Address Register
    699 					 * (most significant bits) offset
    700 					 */
    701 #define	PCI_MSI_MDATA		0x8	/* Message Data Register offset */
    702 #define	PCI_MSI_MDATA64		0xc	/* 64-bit Message Data Register
    703 					 * offset
    704 					 */
    705 
    706 #define	PCI_MSI_MASK		0x0c	/* Vector Mask register */
    707 #define	PCI_MSI_MASK64		0x10	/* 64-bit Vector Mask register */
    708 
    709 #define	PCI_MSI_PENDING		0x10	/* Vector Pending register */
    710 #define	PCI_MSI_PENDING64	0x14	/* 64-bit Vector Pending register */
    711 
    712 #define	PCI_MSI_CTL_MASK	__BITS(31, 16)
    713 #define	PCI_MSI_CTL_EXTMDATA_EN	__SHIFTIN(__BIT(10), PCI_MSI_CTL_MASK)
    714 #define	PCI_MSI_CTL_EXTMDATA_CAP __SHIFTIN(__BIT(9), PCI_MSI_CTL_MASK)
    715 #define	PCI_MSI_CTL_PERVEC_MASK	__SHIFTIN(__BIT(8), PCI_MSI_CTL_MASK)
    716 #define	PCI_MSI_CTL_64BIT_ADDR	__SHIFTIN(__BIT(7), PCI_MSI_CTL_MASK)
    717 #define	PCI_MSI_CTL_MME_MASK	__SHIFTIN(__BITS(6, 4), PCI_MSI_CTL_MASK)
    718 #define	PCI_MSI_CTL_MME(reg)	__SHIFTOUT(reg, PCI_MSI_CTL_MME_MASK)
    719 #define	PCI_MSI_CTL_MMC_MASK	__SHIFTIN(__BITS(3, 1), PCI_MSI_CTL_MASK)
    720 #define	PCI_MSI_CTL_MMC(reg)	__SHIFTOUT(reg, PCI_MSI_CTL_MMC_MASK)
    721 #define	PCI_MSI_CTL_MSI_ENABLE	__SHIFTIN(__BIT(0), PCI_MSI_CTL_MASK)
    722 
    723 /*
    724  * MSI Message Address is at offset 4.
    725  * MSI Message Upper Address (if 64bit) is at offset 8.
    726  * MSI Message data is at offset 8 or 12 and is lower 16 bits.
    727  * MSI Extended Message data is at offset 8 or 12 and is upper 16 bits.
    728  * MSI Mask Bits (32 bit field)
    729  * MSI Pending Bits (32 bit field)
    730  */
    731 
    732  /* Max number of MSI vectors. See PCI-SIG specification. */
    733 #define	PCI_MSI_MAX_VECTORS	32
    734 
    735 /*
    736  * Capability ID: 0x07
    737  * PCI-X capability.
    738  *
    739  * PCI-X capability register has two different layouts. One is for bridge
    740  * function. Another is for non-bridge functions.
    741  */
    742 
    743 
    744 /* For non-bridge functions */
    745 
    746 /*
    747  * Command. 16 bits at offset 2 (e.g. upper 16 bits of the first 32-bit
    748  * word at the capability; the lower 16 bits are the capability ID and
    749  * next capability pointer).
    750  *
    751  * Since we always read PCI config space in 32-bit words, we define these
    752  * as 32-bit values, offset and shifted appropriately.  Make sure you perform
    753  * the appropriate R/M/W cycles!
    754  */
    755 #define PCIX_CMD		0x00
    756 #define PCIX_CMD_PERR_RECOVER	0x00010000
    757 #define PCIX_CMD_RELAXED_ORDER	0x00020000
    758 #define PCIX_CMD_BYTECNT_MASK	0x000c0000
    759 #define	PCIX_CMD_BYTECNT_SHIFT	18
    760 #define	PCIX_CMD_BYTECNT(reg)	\
    761 	(512 << (((reg) & PCIX_CMD_BYTECNT_MASK) >> PCIX_CMD_BYTECNT_SHIFT))
    762 #define		PCIX_CMD_BCNT_512	0x00000000
    763 #define		PCIX_CMD_BCNT_1024	0x00040000
    764 #define		PCIX_CMD_BCNT_2048	0x00080000
    765 #define		PCIX_CMD_BCNT_4096	0x000c0000
    766 #define PCIX_CMD_SPLTRANS_MASK	0x00700000
    767 #define	PCIX_CMD_SPLTRANS_SHIFT	20
    768 #define		PCIX_CMD_SPLTRANS_1	0x00000000
    769 #define		PCIX_CMD_SPLTRANS_2	0x00100000
    770 #define		PCIX_CMD_SPLTRANS_3	0x00200000
    771 #define		PCIX_CMD_SPLTRANS_4	0x00300000
    772 #define		PCIX_CMD_SPLTRANS_8	0x00400000
    773 #define		PCIX_CMD_SPLTRANS_12	0x00500000
    774 #define		PCIX_CMD_SPLTRANS_16	0x00600000
    775 #define		PCIX_CMD_SPLTRANS_32	0x00700000
    776 
    777 /*
    778  * Status. 32 bits at offset 4.
    779  */
    780 #define PCIX_STATUS		0x04
    781 #define PCIX_STATUS_FN_MASK	0x00000007
    782 #define PCIX_STATUS_DEV_MASK	0x000000f8
    783 #define PCIX_STATUS_DEV_SHIFT	3
    784 #define PCIX_STATUS_BUS_MASK	0x0000ff00
    785 #define PCIX_STATUS_BUS_SHIFT	8
    786 #define PCIX_STATUS_FN(val)	((val) & PCIX_STATUS_FN_MASK)
    787 #define PCIX_STATUS_DEV(val)	\
    788 	(((val) & PCIX_STATUS_DEV_MASK) >> PCIX_STATUS_DEV_SHIFT)
    789 #define PCIX_STATUS_BUS(val)	\
    790 	(((val) & PCIX_STATUS_BUS_MASK) >> PCIX_STATUS_BUS_SHIFT)
    791 #define PCIX_STATUS_64BIT	0x00010000	/* 64bit device */
    792 #define PCIX_STATUS_133		0x00020000	/* 133MHz capable */
    793 #define PCIX_STATUS_SPLDISC	0x00040000	/* Split completion discarded*/
    794 #define PCIX_STATUS_SPLUNEX	0x00080000	/* Unexpected split complet. */
    795 #define PCIX_STATUS_DEVCPLX	0x00100000	/* Device Complexity */
    796 #define PCIX_STATUS_MAXB_MASK	0x00600000	/* MAX memory read Byte count*/
    797 #define	PCIX_STATUS_MAXB_SHIFT	21
    798 #define		PCIX_STATUS_MAXB_512	0x00000000
    799 #define		PCIX_STATUS_MAXB_1024	0x00200000
    800 #define		PCIX_STATUS_MAXB_2048	0x00400000
    801 #define		PCIX_STATUS_MAXB_4096	0x00600000
    802 #define PCIX_STATUS_MAXST_MASK	0x03800000	/* MAX outstand. Split Trans.*/
    803 #define	PCIX_STATUS_MAXST_SHIFT	23
    804 #define		PCIX_STATUS_MAXST_1	0x00000000
    805 #define		PCIX_STATUS_MAXST_2	0x00800000
    806 #define		PCIX_STATUS_MAXST_3	0x01000000
    807 #define		PCIX_STATUS_MAXST_4	0x01800000
    808 #define		PCIX_STATUS_MAXST_8	0x02000000
    809 #define		PCIX_STATUS_MAXST_12	0x02800000
    810 #define		PCIX_STATUS_MAXST_16	0x03000000
    811 #define		PCIX_STATUS_MAXST_32	0x03800000
    812 #define PCIX_STATUS_MAXRS_MASK	0x1c000000	/* MAX cumulative Read Size */
    813 #define PCIX_STATUS_MAXRS_SHIFT	26
    814 #define		PCIX_STATUS_MAXRS_1K	0x00000000
    815 #define		PCIX_STATUS_MAXRS_2K	0x04000000
    816 #define		PCIX_STATUS_MAXRS_4K	0x08000000
    817 #define		PCIX_STATUS_MAXRS_8K	0x0c000000
    818 #define		PCIX_STATUS_MAXRS_16K	0x10000000
    819 #define		PCIX_STATUS_MAXRS_32K	0x14000000
    820 #define		PCIX_STATUS_MAXRS_64K	0x18000000
    821 #define		PCIX_STATUS_MAXRS_128K	0x1c000000
    822 #define PCIX_STATUS_SCERR	0x20000000	/* rcv. Split Completion ERR.*/
    823 #define PCIX_STATUS_266		0x40000000	/* 266MHz capable */
    824 #define PCIX_STATUS_533		0x80000000	/* 533MHz capable */
    825 
    826 /* For bridge function */
    827 
    828 #define PCIX_BRIDGE_2ND_STATUS	0x00
    829 #define PCIX_BRIDGE_ST_64BIT	0x00010000	/* Same as PCIX_STATUS (nonb)*/
    830 #define PCIX_BRIDGE_ST_133	0x00020000	/* Same as PCIX_STATUS (nonb)*/
    831 #define PCIX_BRIDGE_ST_SPLDISC	0x00040000	/* Same as PCIX_STATUS (nonb)*/
    832 #define PCIX_BRIDGE_ST_SPLUNEX	0x00080000	/* Same as PCIX_STATUS (nonb)*/
    833 #define PCIX_BRIDGE_ST_SPLOVRN	0x00100000	/* Split completion overrun */
    834 #define PCIX_BRIDGE_ST_SPLRQDL	0x00200000	/* Split request delayed */
    835 #define PCIX_BRIDGE_2NDST_CLKF	0x03c00000	/* Secondary clock frequency */
    836 #define PCIX_BRIDGE_2NDST_CLKF_SHIFT 22
    837 #define PCIX_BRIDGE_2NDST_VER_MASK 0x30000000	/* Version */
    838 #define PCIX_BRIDGE_2NDST_VER_SHIFT 28
    839 #define PCIX_BRIDGE_ST_266	0x40000000	/* Same as PCIX_STATUS (nonb)*/
    840 #define PCIX_BRIDGE_ST_533	0x80000000	/* Same as PCIX_STATUS (nonb)*/
    841 
    842 #define PCIX_BRIDGE_PRI_STATUS	0x04
    843 /* Bit 0 to 15 are the same as PCIX_STATUS */
    844 /* Bit 16 to 21 are the same as PCIX_BRIDGE_2ND_STATUS */
    845 /* Bit 30 and 31 are the same as PCIX_BRIDGE_2ND_STATUS */
    846 
    847 #define PCIX_BRIDGE_UP_STCR	0x08 /* Upstream Split Transaction Control */
    848 #define PCIX_BRIDGE_DOWN_STCR	0x0c /* Downstream Split Transaction Control */
    849 /* The layouts of above two registers are the same */
    850 #define PCIX_BRIDGE_STCAP	0x0000ffff	/* Sp. Tr. Capacity */
    851 #define PCIX_BRIDGE_STCLIM	0xffff0000	/* Sp. Tr. Commitment Limit */
    852 #define PCIX_BRIDGE_STCLIM_SHIFT 16
    853 
    854 /*
    855  * Capability ID: 0x08
    856  * HyperTransport
    857  */
    858 
    859 #define PCI_HT_CMD	0x00	/* Capability List & Command Register */
    860 #define	PCI_HT_CMD_MASK		__BITS(31, 16)
    861 #define PCI_HT_CAP(cr) ((((cr) >> 27) < 0x08) ?				      \
    862     (((cr) >> 27) & 0x1c) : (((cr) >> 27) & 0x1f))
    863 #define PCI_HT_CAPMASK		__BITS(31, 27)
    864 #define PCI_HT_CAP_SLAVE	0b00000 /* 000xx */
    865 #define PCI_HT_CAP_HOST		0b00100 /* 001xx */
    866 #define PCI_HT_CAP_SWITCH	0b01000
    867 #define PCI_HT_CAP_INTERRUPT	0b10000
    868 #define PCI_HT_CAP_REVID	0b10001
    869 #define PCI_HT_CAP_UNITID_CLUMP	0b10010
    870 #define PCI_HT_CAP_EXTCNFSPACE	0b10011
    871 #define PCI_HT_CAP_ADDRMAP	0b10100
    872 #define PCI_HT_CAP_MSIMAP	0b10101
    873 #define PCI_HT_CAP_DIRECTROUTE	0b10110
    874 #define PCI_HT_CAP_VCSET	0b10111
    875 #define PCI_HT_CAP_RETRYMODE	0b11000
    876 #define PCI_HT_CAP_X86ENCODE	0b11001
    877 #define PCI_HT_CAP_GEN3		0b11010
    878 #define PCI_HT_CAP_FLE		0b11011
    879 #define PCI_HT_CAP_PM		0b11100
    880 #define PCI_HT_CAP_HIGHNODECNT	0b11101
    881 
    882 /*
    883  * HT Cap ID: 0b10101
    884  * MSI Mapping
    885  */
    886 
    887 /* Command register bits (31-16)*/
    888 #define PCI_HT_MSI_ENABLED	__BIT(16)
    889 #define PCI_HT_MSI_FIXED	__BIT(17)
    890 
    891 #define PCI_HT_MSI_ADDR_LO	0x04 /* Address register (low) */
    892 #define PCI_HT_MSI_ADDR_LO_MASK	__BITS(31, 20)
    893 #define PCI_HT_MSI_FIXED_ADDR	0xfee00000UL
    894 #define PCI_HT_MSI_ADDR_HI	0x08 /* Address Register (high) */
    895 
    896 /*
    897  * Capability ID: 0x09
    898  * Vendor Specific
    899  */
    900 #define PCI_VENDORSPECIFIC	0x02
    901 #define PCI_VENDORSPECIFIC_SHIFT	16
    902 
    903 /*
    904  * Capability ID: 0x0a
    905  * Debug Port
    906  */
    907 #define PCI_DEBUG_BASER		0x00	/* Debug Base Register */
    908 #define PCI_DEBUG_BASER_SHIFT	16
    909 #define PCI_DEBUG_PORTOFF_SHIFT	16
    910 #define	PCI_DEBUG_PORTOFF_MASK	0x1fff0000	/* Debug port offset */
    911 #define PCI_DEBUG_BARNUM_SHIFT	29
    912 #define	PCI_DEBUG_BARNUM_MASK	0xe0000000	/* BAR number */
    913 
    914 /*
    915  * Capability ID: 0x0b
    916  * Compact PCI
    917  */
    918 
    919 /*
    920  * Capability ID: 0x0c
    921  * Hotplug
    922  */
    923 
    924 /*
    925  * Capability ID: 0x0d
    926  * Subsystem
    927  */
    928 #define PCI_CAP_SUBSYS_ID 0x04
    929 /* bit field layout is the same as PCI_SUBSYS_ID_REG's one */
    930 
    931 /*
    932  * Capability ID: 0x0e
    933  * AGP8
    934  */
    935 
    936 /*
    937  * Capability ID: 0x0f
    938  * Secure Device
    939  *
    940  * Reference: AMD I/O Virtualization Technology(IOMMU) Specification (#48882)
    941  * Revision 3.00.
    942  */
    943 #define PCI_SECURE_CAP	       0x00 /* Capability Header */
    944 #define PCI_SECURE_CAP_TYPE	__BITS(18, 16)	/* Capability block type */
    945 #define PCI_SECURE_CAP_TYPE_IOMMU	0x3		/* IOMMU Cap */
    946 #define PCI_SECURE_CAP_REV	__BITS(23, 19)	/* Capability revision */
    947 #define PCI_SECURE_CAP_REV_IOMMU	0x01		/* IOMMU interface  */
    948 /* For IOMMU only */
    949 #define PCI_SECURE_CAP_IOTLBSUP	__BIT(24)	/* IOTLB */
    950 #define PCI_SECURE_CAP_HTTUNNEL	__BIT(25)	/* HT tunnel translation */
    951 #define PCI_SECURE_CAP_NPCACHE	__BIT(26) /* Not present table entries cached */
    952 #define PCI_SECURE_CAP_EFRSUP	__BIT(27)	/* IOMMU Ext-Feature Reg */
    953 #define PCI_SECURE_CAP_EXT	__BIT(28)	/* IOMMU Misc Info Reg 1 */
    954 #define PCI_SECURE_IOMMU_BAL   0x04 /* Base Address Low */
    955 #define PCI_SECURE_IOMMU_BAL_EN		__BIT(0)	/* Enable */
    956 #define PCI_SECURE_IOMMU_BAL_L		__BITS(18, 14)	/* Base Addr [18:14] */
    957 #define PCI_SECURE_IOMMU_BAL_H		__BITS(31, 19)	/* Base Addr [31:19] */
    958 #define PCI_SECURE_IOMMU_BAH   0x08 /* Base Address High */
    959 #define PCI_SECURE_IOMMU_RANGE 0x0c /* IOMMU Range */
    960 #define PCI_SECURE_IOMMU_RANGE_UNITID	__BITS(4, 0)	/* HT UnitID */
    961 #define PCI_SECURE_IOMMU_RANGE_RNGVALID	__BIT(7)	/* Range valid */
    962 #define PCI_SECURE_IOMMU_RANGE_BUSNUM	__BITS(15, 8)	/* bus number */
    963 #define PCI_SECURE_IOMMU_RANGE_FIRSTDEV	__BITS(23, 16)	/* First device */
    964 #define PCI_SECURE_IOMMU_RANGE_LASTDEV	__BITS(31, 24)	/* Last device */
    965 #define PCI_SECURE_IOMMU_MISC0 0x10 /* IOMMU Miscellaneous Information 0 */
    966 #define PCI_SECURE_IOMMU_MISC0_MSINUM  __BITS(4, 0)  /* MSI Message number */
    967 #define PCI_SECURE_IOMMU_MISC0_GVASIZE __BITS(7, 5) /* Guest Virtual Adr size */
    968 #define PCI_SECURE_IOMMU_MISC0_GVASIZE_48B	0x2	/* 48bits */
    969 #define PCI_SECURE_IOMMU_MISC0_PASIZE  __BITS(14, 8) /* Physical Address size */
    970 #define PCI_SECURE_IOMMU_MISC0_VASIZE  __BITS(21, 15)/* Virtual Address size */
    971 #define PCI_SECURE_IOMMU_MISC0_ATSRESV __BIT(22) /* ATS resp addr range rsvd */
    972 #define PCI_SECURE_IOMMU_MISC0_MISNPPR __BITS(31, 27)/* Periph Pg Rq MSI Msgn*/
    973 #define PCI_SECURE_IOMMU_MISC1 0x14 /* IOMMU Miscellaneous Information 1 */
    974 #define PCI_SECURE_IOMMU_MISC1_MSINUM __BITS(4, 0) /* MSI Message number(GA) */
    975 
    976 /*
    977  * Capability ID: 0x10
    978  * PCI Express; access via capability pointer.
    979  */
    980 #define PCIE_XCAP	0x00	/* Capability List & Capabilities Register */
    981 #define	PCIE_XCAP_MASK		__BITS(31, 16)
    982 /* Capability Version */
    983 #define PCIE_XCAP_VER_MASK	__SHIFTIN(__BITS(3, 0), PCIE_XCAP_MASK)
    984 #define PCIE_XCAP_VER(x)	__SHIFTOUT((x), PCIE_XCAP_VER_MASK)
    985 #define	 PCIE_XCAP_VER_1		1
    986 #define	 PCIE_XCAP_VER_2		2
    987 #define	PCIE_XCAP_TYPE_MASK	__SHIFTIN(__BITS(7, 4), PCIE_XCAP_MASK)
    988 #define	PCIE_XCAP_TYPE(x)	__SHIFTOUT((x), PCIE_XCAP_TYPE_MASK)
    989 #define	 PCIE_XCAP_TYPE_PCIE_DEV	0x0
    990 #define	 PCIE_XCAP_TYPE_PCI_DEV		0x1
    991 #define	 PCIE_XCAP_TYPE_RP		0x4
    992 #define	 PCIE_XCAP_TYPE_UP		0x5
    993 #define	 PCIE_XCAP_TYPE_DOWN		0x6
    994 #define	 PCIE_XCAP_TYPE_PCIE2PCI	0x7
    995 #define	 PCIE_XCAP_TYPE_PCI2PCIE	0x8
    996 #define	 PCIE_XCAP_TYPE_RCIEP		0x9
    997 #define	 PCIE_XCAP_TYPE_RC_EVNTC	0xa
    998 #define PCIE_XCAP_SI		__SHIFTIN(__BIT(8), PCIE_XCAP_MASK) /* Slot Implemented */
    999 #define PCIE_XCAP_IRQ		__SHIFTIN(__BITS(13, 9), PCIE_XCAP_MASK)
   1000 #define PCIE_DCAP	0x04	/* Device Capabilities Register */
   1001 #define PCIE_DCAP_MAX_PAYLOAD	__BITS(2, 0)   /* Max Payload Size Supported */
   1002 #define PCIE_DCAP_PHANTOM_FUNCS	__BITS(4, 3)   /* Phantom Functions Supported*/
   1003 #define PCIE_DCAP_EXT_TAG_FIELD	__BIT(5)       /* Extended Tag Field Support */
   1004 #define PCIE_DCAP_L0S_LATENCY	__BITS(8, 6)   /* Endpoint L0 Accptbl Latency*/
   1005 #define PCIE_DCAP_L1_LATENCY	__BITS(11, 9)  /* Endpoint L1 Accptbl Latency*/
   1006 #define PCIE_DCAP_ATTN_BUTTON	__BIT(12)      /* Attention Indicator Button */
   1007 #define PCIE_DCAP_ATTN_IND	__BIT(13)      /* Attention Indicator Present*/
   1008 #define PCIE_DCAP_PWR_IND	__BIT(14)      /* Power Indicator Present */
   1009 #define PCIE_DCAP_ROLE_ERR_RPT	__BIT(15)      /* Role-Based Error Reporting */
   1010 #define PCIE_DCAP_SLOT_PWR_LIM_VAL __BITS(25, 18) /* Cap. Slot PWR Limit Val */
   1011 #define PCIE_DCAP_SLOT_PWR_LIM_SCALE __BITS(27, 26) /* Cap. SlotPWRLimit Scl */
   1012 #define PCIE_DCAP_FLR		__BIT(28)      /* Function-Level Reset Cap. */
   1013 #define PCIE_DCSR	0x08	/* Device Control & Status Register */
   1014 #define PCIE_DCSR_ENA_COR_ERR	__BIT(0)       /* Correctable Error Report En*/
   1015 #define PCIE_DCSR_ENA_NFER	__BIT(1)       /* Non-Fatal Error Report En. */
   1016 #define PCIE_DCSR_ENA_FER	__BIT(2)       /* Fatal Error Reporting Enabl*/
   1017 #define PCIE_DCSR_ENA_URR	__BIT(3)       /* Unsupported Request Rpt En */
   1018 #define PCIE_DCSR_ENA_RELAX_ORD	__BIT(4)       /* Enable Relaxed Ordering */
   1019 #define PCIE_DCSR_MAX_PAYLOAD	__BITS(7, 5)   /* Max Payload Size */
   1020 #define PCIE_DCSR_EXT_TAG_FIELD	__BIT(8)       /* Extended Tag Field Enable */
   1021 #define PCIE_DCSR_PHANTOM_FUNCS	__BIT(9)       /* Phantom Functions Enable */
   1022 #define PCIE_DCSR_AUX_POWER_PM	__BIT(10)      /* Aux Power PM Enable */
   1023 #define PCIE_DCSR_ENA_NO_SNOOP	__BIT(11)      /* Enable No Snoop */
   1024 #define PCIE_DCSR_MAX_READ_REQ	__BITS(14, 12) /* Max Read Request Size */
   1025 #define PCIE_DCSR_BRDG_CFG_RETRY __BIT(15)     /* Bridge Config Retry Enable */
   1026 #define PCIE_DCSR_INITIATE_FLR	__BIT(15)      /* Initiate Function-Level Rst*/
   1027 #define PCIE_DCSR_CED		__BIT(0 + 16)  /* Correctable Error Detected */
   1028 #define PCIE_DCSR_NFED		__BIT(1 + 16)  /* Non-Fatal Error Detected */
   1029 #define PCIE_DCSR_FED		__BIT(2 + 16)  /* Fatal Error Detected */
   1030 #define PCIE_DCSR_URD		__BIT(3 + 16)  /* Unsupported Req. Detected */
   1031 #define PCIE_DCSR_AUX_PWR	__BIT(4 + 16)  /* Aux Power Detected */
   1032 #define PCIE_DCSR_TRANSACTION_PND __BIT(5 + 16) /* Transaction Pending */
   1033 #define PCIE_DCSR_EMGPWRREDD	__BIT(6 + 16)  /* Emg. Pwr. Reduct. Detected */
   1034 #define PCIE_LCAP	0x0c	/* Link Capabilities Register */
   1035 #define PCIE_LCAP_MAX_SPEED	__BITS(3, 0)   /* Max Link Speed */
   1036 #define  PCIE_LCAP_MAX_SPEED_2	1	       /* 2.5GT/s */
   1037 #define  PCIE_LCAP_MAX_SPEED_5	2	       /* 5GT/s */
   1038 #define  PCIE_LCAP_MAX_SPEED_8	3	       /* 8GT/s */
   1039 #define  PCIE_LCAP_MAX_SPEED_16	4	       /* 16GT/s */
   1040 #define  PCIE_LCAP_MAX_SPEED_32	5	       /* 32GT/s */
   1041 #define  PCIE_LCAP_MAX_SPEED_64	6	       /* 64GT/s */
   1042 #define PCIE_LCAP_MAX_WIDTH	__BITS(9, 4)   /* Maximum Link Width */
   1043 #define PCIE_LCAP_ASPM		__BITS(11, 10) /* Active State Link PM Supp. */
   1044 #define PCIE_LCAP_L0S_EXIT	__BITS(14, 12) /* L0s Exit Latency */
   1045 #define PCIE_LCAP_L1_EXIT	__BITS(17, 15) /* L1 Exit Latency */
   1046 #define PCIE_LCAP_CLOCK_PM	__BIT(18)      /* Clock Power Management */
   1047 #define PCIE_LCAP_SURPRISE_DOWN	__BIT(19)      /* Surprise Down Err Rpt Cap. */
   1048 #define PCIE_LCAP_DL_ACTIVE	__BIT(20)      /* Data Link Layer Link Active*/
   1049 #define PCIE_LCAP_LINK_BW_NOTIFY __BIT(21)     /* Link BW Notification Capabl*/
   1050 #define PCIE_LCAP_ASPM_COMPLIANCE __BIT(22)    /* ASPM Optionally Compliance */
   1051 #define PCIE_LCAP_PORT		__BITS(31, 24) /* Port Number */
   1052 #define PCIE_LCSR	0x10	/* Link Control & Status Register */
   1053 #define PCIE_LCSR_ASPM_L0S	__BIT(0)       /* Active State PM Control L0s*/
   1054 #define PCIE_LCSR_ASPM_L1	__BIT(1)       /* Active State PM Control L1 */
   1055 #define PCIE_LCSR_RCB		__BIT(3)       /* Read Completion Boundary Ctl*/
   1056 #define PCIE_LCSR_LINK_DIS	__BIT(4)       /* Link Disable */
   1057 #define PCIE_LCSR_RETRAIN	__BIT(5)       /* Retrain Link */
   1058 #define PCIE_LCSR_COMCLKCFG	__BIT(6)       /* Common Clock Configuration */
   1059 #define PCIE_LCSR_EXTNDSYNC	__BIT(7)       /* Extended Synch */
   1060 #define PCIE_LCSR_ENCLKPM	__BIT(8)       /* Enable Clock Power Managmt */
   1061 #define PCIE_LCSR_HAWD		__BIT(9)       /* HW Autonomous Width Disable*/
   1062 #define PCIE_LCSR_LBMIE		__BIT(10)      /* Link BW Management Intr En */
   1063 #define PCIE_LCSR_LABIE		__BIT(11)      /* Link Autonomous BW Intr En */
   1064 #define	PCIE_LCSR_DRSSGNL	__BITS(15, 14) /* DRS Signaling */
   1065 #define	PCIE_LCSR_LINKSPEED	__BITS(19, 16) /* Link Speed */
   1066 #define  PCIE_LCSR_LINKSPEED_2	1	       /* 2.5GT/s */
   1067 #define  PCIE_LCSR_LINKSPEED_5	2	       /* 5GT/s */
   1068 #define  PCIE_LCSR_LINKSPEED_8	3	       /* 8GT/s */
   1069 #define  PCIE_LCSR_LINKSPEED_16	4	       /* 16GT/s */
   1070 #define  PCIE_LCSR_LINKSPEED_32	5	       /* 32GT/s */
   1071 #define  PCIE_LCSR_LINKSPEED_64	6	       /* 64GT/s */
   1072 #define	PCIE_LCSR_NLW		__BITS(25, 20) /* Negotiated Link Width */
   1073 #define  PCIE_LCSR_NLW_X1	__BIT(20)	/* Negotiated x1 */
   1074 #define  PCIE_LCSR_NLW_X2	__BIT(21)	/* Negotiated x2 */
   1075 #define  PCIE_LCSR_NLW_X4	__BIT(22)	/* Negotiated x4 */
   1076 #define  PCIE_LCSR_NLW_X8	__BIT(23)	/* Negotiated x8 */
   1077 #define  PCIE_LCSR_NLW_X12	__BITS(22, 23)	/* Negotiated x12 */
   1078 #define  PCIE_LCSR_NLW_X16	__BIT(24)	/* Negotiated x16 */
   1079 #define  PCIE_LCSR_NLW_X32	__BIT(25)	/* Negotiated x32 */
   1080 #define	PCIE_LCSR_LINKTRAIN_ERR	__BIT(10 + 16) /* Link Training Error */
   1081 #define	PCIE_LCSR_LINKTRAIN	__BIT(11 + 16) /* Link Training */
   1082 #define	PCIE_LCSR_SLOTCLKCFG	__BIT(12 + 16) /* Slot Clock Configuration */
   1083 #define	PCIE_LCSR_DLACTIVE	__BIT(13 + 16) /* Data Link Layer Link Active*/
   1084 #define	PCIE_LCSR_LINK_BW_MGMT	__BIT(14 + 16) /* Link BW Management Status */
   1085 #define	PCIE_LCSR_LINK_AUTO_BW	__BIT(15 + 16) /* Link Autonomous BW Status */
   1086 #define PCIE_SLCAP	0x14	/* Slot Capabilities Register */
   1087 #define PCIE_SLCAP_ABP		__BIT(0)       /* Attention Button Present */
   1088 #define PCIE_SLCAP_PCP		__BIT(1)       /* Power Controller Present */
   1089 #define PCIE_SLCAP_MSP		__BIT(2)       /* MRL Sensor Present */
   1090 #define PCIE_SLCAP_AIP		__BIT(3)       /* Attention Indicator Present*/
   1091 #define PCIE_SLCAP_PIP		__BIT(4)       /* Power Indicator Present */
   1092 #define PCIE_SLCAP_HPS		__BIT(5)       /* Hot-Plug Surprise */
   1093 #define PCIE_SLCAP_HPC		__BIT(6)       /* Hot-Plug Capable */
   1094 #define	PCIE_SLCAP_SPLV		__BITS(14, 7)  /* Slot Power Limit Value */
   1095 #define	PCIE_SLCAP_SPLS		__BITS(16, 15) /* Slot Power Limit Scale */
   1096 #define	PCIE_SLCAP_EIP		__BIT(17)      /* Electromechanical Interlock*/
   1097 #define	PCIE_SLCAP_NCCS		__BIT(18)      /* No Command Completed Supp. */
   1098 #define	PCIE_SLCAP_PSN		__BITS(31, 19) /* Physical Slot Number */
   1099 #define PCIE_SLCSR	0x18	/* Slot Control & Status Register */
   1100 #define PCIE_SLCSR_ABE		__BIT(0)       /* Attention Button Pressed En*/
   1101 #define PCIE_SLCSR_PFE		__BIT(1)       /* Power Button Pressed Enable*/
   1102 #define PCIE_SLCSR_MSE		__BIT(2)       /* MRL Sensor Changed Enable */
   1103 #define PCIE_SLCSR_PDE		__BIT(3)       /* Presence Detect Changed Ena*/
   1104 #define PCIE_SLCSR_CCE		__BIT(4)       /* Command Completed Intr. En */
   1105 #define PCIE_SLCSR_HPE		__BIT(5)       /* Hot Plug Interrupt Enable */
   1106 #define PCIE_SLCSR_AIC		__BITS(7, 6)   /* Attention Indicator Control*/
   1107 #define PCIE_SLCSR_PIC		__BITS(9, 8)   /* Power Indicator Control */
   1108 #define PCIE_SLCSR_IND_ON	0x1	       /* Attn/Power Indicator On */
   1109 #define PCIE_SLCSR_IND_BLINK	0x2	       /* Attn/Power Indicator Blink */
   1110 #define PCIE_SLCSR_IND_OFF	0x3	       /* Attn/Power Indicator Off */
   1111 #define PCIE_SLCSR_PCC		__BIT(10)      /*
   1112 						* Power Controller Control:
   1113 						* 0: Power on, 1: Power off.
   1114 						*/
   1115 #define PCIE_SLCSR_EIC		__BIT(11)      /* Electromechanical Interlock*/
   1116 #define PCIE_SLCSR_DLLSCE	__BIT(12)      /* DataLinkLayer State Changed*/
   1117 #define PCIE_SLCSR_AUTOSPLDIS	__BIT(13)      /* Auto Slot Power Limit Dis. */
   1118 #define PCIE_SLCSR_ABP		__BIT(0 + 16)  /* Attention Button Pressed */
   1119 #define PCIE_SLCSR_PFD		__BIT(1 + 16)  /* Power Fault Detected */
   1120 #define PCIE_SLCSR_MSC		__BIT(2 + 16)  /* MRL Sensor Changed */
   1121 #define PCIE_SLCSR_PDC		__BIT(3 + 16)  /* Presence Detect Changed */
   1122 #define PCIE_SLCSR_CC		__BIT(4 + 16)  /* Command Completed */
   1123 #define PCIE_SLCSR_MS		__BIT(5 + 16)  /* MRL Sensor State */
   1124 #define PCIE_SLCSR_PDS		__BIT(6 + 16)  /* Presence Detect State */
   1125 #define PCIE_SLCSR_EIS		__BIT(7 + 16)  /* Electromechanical Interlock*/
   1126 #define PCIE_SLCSR_LACS		__BIT(8 + 16)  /* Data Link Layer State Chg. */
   1127 #define PCIE_RCR	0x1c	/* Root Control & Capabilities Reg. */
   1128 #define PCIE_RCR_SERR_CER	__BIT(0)       /* SERR on Correctable Err. En*/
   1129 #define PCIE_RCR_SERR_NFER	__BIT(1)       /* SERR on Non-Fatal Error En */
   1130 #define PCIE_RCR_SERR_FER	__BIT(2)       /* SERR on Fatal Error Enable */
   1131 #define PCIE_RCR_PME_IE		__BIT(3)       /* PME Interrupt Enable */
   1132 #define PCIE_RCR_CRS_SVE	__BIT(4)       /* CRS Software Visibility En */
   1133 #define PCIE_RCR_CRS_SV		__BIT(16)      /* CRS Software Visibility */
   1134 #define PCIE_RSR	0x20	/* Root Status Register */
   1135 #define PCIE_RSR_PME_REQESTER	__BITS(15, 0)  /* PME Requester ID */
   1136 #define PCIE_RSR_PME_STAT	__BIT(16)      /* PME Status */
   1137 #define PCIE_RSR_PME_PEND	__BIT(17)      /* PME Pending */
   1138 #define PCIE_DCAP2	0x24	/* Device Capabilities 2 Register */
   1139 #define PCIE_DCAP2_COMPT_RANGE	__BITS(3,0)    /* Compl. Timeout Ranges Supp */
   1140 #define PCIE_DCAP2_COMPT_DIS	__BIT(4)       /* Compl. Timeout Disable Supp*/
   1141 #define PCIE_DCAP2_ARI_FWD	__BIT(5)       /* ARI Forward Supported */
   1142 #define PCIE_DCAP2_ATOM_ROUT	__BIT(6)       /* AtomicOp Routing Supported */
   1143 #define PCIE_DCAP2_32ATOM	__BIT(7)       /* 32bit AtomicOp Compl. Supp */
   1144 #define PCIE_DCAP2_64ATOM	__BIT(8)       /* 64bit AtomicOp Compl. Supp */
   1145 #define PCIE_DCAP2_128CAS	__BIT(9)       /* 128bit Cas Completer Supp. */
   1146 #define PCIE_DCAP2_NO_ROPR_PASS	__BIT(10)      /* No RO-enabled PR-PR Passng */
   1147 #define PCIE_DCAP2_LTR_MEC	__BIT(11)      /* LTR Mechanism Supported */
   1148 #define PCIE_DCAP2_TPH_COMP	__BITS(13, 12) /* TPH Completer Supported */
   1149 #define PCIE_DCAP2_LNSYSCLS	__BITS(15, 14) /* LN System CLS */
   1150 #define PCIE_DCAP2_TBT_COMP	__BIT(16)      /* 10-bit Tag Completer Supp. */
   1151 #define PCIE_DCAP2_TBT_REQ	__BIT(17)      /* 10-bit Tag Requester Supp. */
   1152 #define PCIE_DCAP2_OBFF		__BITS(19, 18) /* Optimized Buffer Flush/Fill*/
   1153 #define PCIE_DCAP2_EXTFMT_FLD	__BIT(20)      /* Extended Fmt Field Support */
   1154 #define PCIE_DCAP2_EETLP_PREF	__BIT(21)      /* End-End TLP Prefix Support */
   1155 #define PCIE_DCAP2_MAX_EETLP	__BITS(23, 22) /* Max End-End TLP Prefix Sup */
   1156 #define PCIE_DCAP2_EMGPWRRED	__BITS(25, 24) /* Emergency Power Reduc. Sup */
   1157 #define PCIE_DCAP2_EMGPWRRED_INI __BIT(26)     /* Emrg. Pwr. Reduc. Ini. Req */
   1158 #define PCIE_DCAP2_FRS		__BIT(31)      /* FRS Supported */
   1159 #define PCIE_DCSR2	0x28	/* Device Control & Status 2 Register */
   1160 #define PCIE_DCSR2_COMPT_VAL	__BITS(3, 0)   /* Completion Timeout Value */
   1161 #define PCIE_DCSR2_COMPT_DIS	__BIT(4)       /* Completion Timeout Disable */
   1162 #define PCIE_DCSR2_ARI_FWD	__BIT(5)       /* ARI Forwarding Enable */
   1163 #define PCIE_DCSR2_ATOM_REQ	__BIT(6)       /* AtomicOp Requester Enable */
   1164 #define PCIE_DCSR2_ATOM_EBLK	__BIT(7)       /* AtomicOp Egress Blocking */
   1165 #define PCIE_DCSR2_IDO_REQ	__BIT(8)       /* IDO Request Enable */
   1166 #define PCIE_DCSR2_IDO_COMP	__BIT(9)       /* IDO Completion Enable */
   1167 #define PCIE_DCSR2_LTR_MEC	__BIT(10)      /* LTR Mechanism Enable */
   1168 #define PCIE_DCSR2_EMGPWRRED_REQ __BIT(11)     /* Emergency Power Reduc. Req */
   1169 #define PCIE_DCSR2_TBT_REQ	__BIT(12)      /* 10-bit Tag Requester Ena. */
   1170 #define PCIE_DCSR2_OBFF_EN	__BITS(14, 13) /* OBFF Enable */
   1171 #define PCIE_DCSR2_EETLP	__BIT(15)      /* End-End TLP Prefix Blcking */
   1172 #define PCIE_LCAP2	0x2c	/* Link Capabilities 2 Register */
   1173 #define PCIE_LCAP2_SUP_LNKSV	__BITS(7, 1)   /* Supported Link Speeds Vect */
   1174 #define  PCIE_LCAP2_SUP_LNKS2	__BIT(1)       /* Supported Speed 2.5GT/ */
   1175 #define  PCIE_LCAP2_SUP_LNKS5	__BIT(2)       /* Supported Speed 5GT/ */
   1176 #define  PCIE_LCAP2_SUP_LNKS8	__BIT(3)       /* Supported Speed 8GT/ */
   1177 #define  PCIE_LCAP2_SUP_LNKS16	__BIT(4)       /* Supported Speed 16GT/ */
   1178 #define  PCIE_LCAP2_SUP_LNKS32	__BIT(5)       /* Supported Speed 32GT/ */
   1179 #define  PCIE_LCAP2_SUP_LNKS64	__BIT(6)       /* Supported Speed 64GT/ */
   1180 #define PCIE_LCAP2_CROSSLNK	__BIT(8)       /* Crosslink Supported */
   1181 #define PCIE_LCAP2_LOWSKPOS_GENSUPPSV __BITS(15, 9)
   1182 				  /* Lower SKP OS Generation Supp. Spd. Vect */
   1183 #define PCIE_LCAP2_LOWSKPOS_RECSUPPSV __BITS(22, 16)
   1184 				   /* Lower SKP OS Reception Supp. Spd. Vect */
   1185 #define PCIE_LCAP2_RETIMERPD	__BIT(23)       /* Retimer Presence Detect */
   1186 #define PCIE_LCAP2_DRS		__BIT(31)       /* DRS Supported */
   1187 #define PCIE_LCSR2	0x30	/* Link Control & Status 2 Register */
   1188 #define PCIE_LCSR2_TGT_LSPEED	__BITS(3, 0)   /* Target Link Speed */
   1189 #define  PCIE_LCSR2_TGT_LSPEED_2_5G  0x1       /* 2.5GT/s supported */
   1190 #define  PCIE_LCSR2_TGT_LSPEED_5G    0x2       /* 5.0GT/s supported */
   1191 #define  PCIE_LCSR2_TGT_LSPEED_8G    0x3       /* 8.0GT/s supported */
   1192 #define PCIE_LCSR2_ENT_COMPL	__BIT(4)       /* Enter Compliance */
   1193 #define PCIE_LCSR2_HW_AS_DIS	__BIT(5)       /* HW Autonomous Speed Disabl */
   1194 #define PCIE_LCSR2_SEL_DEEMP	__BIT(6)       /* Selectable De-emphasis */
   1195 #define PCIE_LCSR2_TX_MARGIN	__BITS(9, 7)   /* Transmit Margin */
   1196 #define PCIE_LCSR2_EN_MCOMP	__BIT(10)      /* Enter Modified Compliance */
   1197 #define PCIE_LCSR2_COMP_SOS	__BIT(11)      /* Compliance SOS */
   1198 #define PCIE_LCSR2_COMP_DEEMP	__BITS(15, 12) /* Compliance Preset/De-emph */
   1199 #define PCIE_LCSR2_DEEMP_LVL	__BIT(0 + 16)  /* Current De-emphasis Level */
   1200 #define PCIE_LCSR2_EQ_COMPL	__BIT(1 + 16)  /* Equalization Complete */
   1201 #define PCIE_LCSR2_EQP1_SUC	__BIT(2 + 16)  /* Equaliz Phase 1 Successful */
   1202 #define PCIE_LCSR2_EQP2_SUC	__BIT(3 + 16)  /* Equaliz Phase 2 Successful */
   1203 #define PCIE_LCSR2_EQP3_SUC	__BIT(4 + 16)  /* Equaliz Phase 3 Successful */
   1204 #define PCIE_LCSR2_LNKEQ_REQ	__BIT(5 + 16)  /* Link Equalization Request */
   1205 #define PCIE_LCSR2_RETIMERPD	__BIT(6 + 16)  /* Retimer Presence Detected */
   1206 #define PCIE_LCSR2_DSCOMPN	__BITS(30, 28) /* Downstream Component Pres. */
   1207 #define   PCIE_DSCOMPN_DOWN_NOTDETERM	0x00	/* LD: Presence Not Determin.*/
   1208 #define   PCIE_DSCOMPN_DOWN_NOTPRES	0x01	/* LD: Component Not Present */
   1209 #define   PCIE_DSCOMPN_DOWN_PRES	0x02	/* LD: Component Present */
   1210 						/* 0x03 is reserved */
   1211 #define   PCIE_DSCOMPN_UP_PRES		0x04	/* LU: Component Present */
   1212 #define   PCIE_DSCOMPN_UP_PRES_DRS	0x05	/* LU: Comp Pres and DRS RCV */
   1213 #define PCIE_LCSR2_DRSRCV	__BIT(15 + 16) /* DRS Message Received */
   1214 
   1215 #define PCIE_SLCAP2	0x34	/* Slot Capabilities 2 Register */
   1216 #define PCIE_SLCSR2	0x38	/* Slot Control & Status 2 Register */
   1217 
   1218 /*
   1219  * Other than Root Complex Integrated Endpoint and Root Complex Event Collector
   1220  * have link related registers.
   1221  */
   1222 #define PCIE_HAS_LINKREGS(type) (((type) != PCIE_XCAP_TYPE_RCIEP) &&	\
   1223 	    ((type) != PCIE_XCAP_TYPE_RC_EVNTC))
   1224 
   1225 /* Only root port and root complex event collector have PCIE_RCR & PCIE_RSR */
   1226 #define PCIE_HAS_ROOTREGS(type) (((type) == PCIE_XCAP_TYPE_RP) || \
   1227 	    ((type) == PCIE_XCAP_TYPE_RC_EVNTC))
   1228 
   1229 
   1230 /*
   1231  * Capability ID: 0x11
   1232  * MSIX
   1233  */
   1234 
   1235 #define PCI_MSIX_CTL	0x00
   1236 #define	PCI_MSIX_CTL_ENABLE	0x80000000
   1237 #define	PCI_MSIX_CTL_FUNCMASK	0x40000000
   1238 #define	PCI_MSIX_CTL_TBLSIZE_MASK 0x07ff0000
   1239 #define	PCI_MSIX_CTL_TBLSIZE_SHIFT 16
   1240 #define	PCI_MSIX_CTL_TBLSIZE(ofs)	((((ofs) & PCI_MSIX_CTL_TBLSIZE_MASK) \
   1241 		>> PCI_MSIX_CTL_TBLSIZE_SHIFT) + 1)
   1242 /*
   1243  * 2nd DWORD is the Table Offset
   1244  */
   1245 #define	PCI_MSIX_TBLOFFSET	0x04
   1246 #define	PCI_MSIX_TBLOFFSET_MASK	__BITS(31, 3)
   1247 #define	PCI_MSIX_TBLBIR_MASK	__BITS(2, 0)
   1248 /*
   1249  * 3rd DWORD is the Pending Bitmap Array Offset
   1250  */
   1251 #define	PCI_MSIX_PBAOFFSET	0x08
   1252 #define	PCI_MSIX_PBAOFFSET_MASK	__BITS(31, 3)
   1253 #define	PCI_MSIX_PBABIR_MASK	__BITS(2, 0)
   1254 
   1255 #define PCI_MSIX_TABLE_ENTRY_SIZE	16
   1256 #define PCI_MSIX_TABLE_ENTRY_ADDR_LO	0x0
   1257 #define PCI_MSIX_TABLE_ENTRY_ADDR_HI	0x4
   1258 #define PCI_MSIX_TABLE_ENTRY_DATA	0x8
   1259 #define PCI_MSIX_TABLE_ENTRY_VECTCTL	0xc
   1260 struct pci_msix_table_entry {
   1261 	uint32_t pci_msix_addr_lo;
   1262 	uint32_t pci_msix_addr_hi;
   1263 	uint32_t pci_msix_value;
   1264 	uint32_t pci_msix_vector_control;
   1265 };
   1266 #define	PCI_MSIX_VECTCTL_MASK	__BIT(0)
   1267 #define	PCI_MSIX_VECTCTL_STLO	__BITS(23, 16)	/* ST lower */
   1268 #define	PCI_MSIX_VECTCTL_STUP	__BITS(31, 24)	/* ST upper */
   1269 
   1270  /* Max number of MSI-X vectors. See PCI-SIG specification. */
   1271 #define	PCI_MSIX_MAX_VECTORS	2048
   1272 
   1273 /*
   1274  * Capability ID: 0x12
   1275  * SATA
   1276  */
   1277 #define	PCI_SATA_REV	0x00	/* Revision Register */
   1278 #define	PCI_SATA_REV_MINOR	__BITS(19, 16)	/* Minor Revision */
   1279 #define	PCI_SATA_REV_MAJOR	__BITS(23, 20)	/* Major Revision */
   1280 #define	PCI_SATA_BAR	0x04	/* BAR Register */
   1281 #define	PCI_SATA_BAR_SPEC	__BITS(3, 0)	/* BAR Specifier */
   1282 #define	PCI_SATA_BAR_INCONF	__BITS(3, 0)	/* All 1 = in config space */
   1283 #define	PCI_SATA_BAR_NUM(x)	(__SHIFTOUT((x), PCI_SATA_BAR_SPEC) - 4)
   1284 #define	PCI_SATA_BAR_OFFSET	__BITS(23, 4)	/* BAR Offset */
   1285 
   1286 /*
   1287  * Capability ID: 0x13
   1288  * Advanced Feature
   1289  */
   1290 #define PCI_AFCAPR	0x00	/* Capabilities */
   1291 #define	PCI_AFCAPR_MASK		__BITS(31, 24)
   1292 #define	PCI_AF_LENGTH		__BITS(23, 16)	/* Structure Length */
   1293 #define	PCI_AF_TP_CAP		__BIT(24)	/* Transaction Pending */
   1294 #define	PCI_AF_FLR_CAP		__BIT(25)	/* Function Level Reset */
   1295 #define PCI_AFCSR	0x04	/* Control & Status register */
   1296 #define PCI_AFCR_INITIATE_FLR	__BIT(0)	/* Initiate Function LVL RST */
   1297 #define PCI_AFSR_TP		__BIT(8)	/* Transaction Pending */
   1298 
   1299 
   1300 /*
   1301  * Interrupt Configuration Register; contains interrupt pin and line.
   1302  */
   1303 #define	PCI_INTERRUPT_REG	0x3c
   1304 
   1305 typedef uint8_t pci_intr_latency_t;
   1306 typedef uint8_t pci_intr_grant_t;
   1307 typedef uint8_t pci_intr_pin_t;
   1308 typedef uint8_t pci_intr_line_t;
   1309 
   1310 #define PCI_MAX_LAT_SHIFT		24
   1311 #define	PCI_MAX_LAT_MASK		0xff
   1312 #define	PCI_MAX_LAT(icr) \
   1313 	    (((icr) >> PCI_MAX_LAT_SHIFT) & PCI_MAX_LAT_MASK)
   1314 
   1315 #define PCI_MIN_GNT_SHIFT		16
   1316 #define	PCI_MIN_GNT_MASK		0xff
   1317 #define	PCI_MIN_GNT(icr) \
   1318 	    (((icr) >> PCI_MIN_GNT_SHIFT) & PCI_MIN_GNT_MASK)
   1319 
   1320 #define	PCI_INTERRUPT_GRANT_SHIFT	24
   1321 #define	PCI_INTERRUPT_GRANT_MASK	0xff
   1322 #define	PCI_INTERRUPT_GRANT(icr) \
   1323 	    (((icr) >> PCI_INTERRUPT_GRANT_SHIFT) & PCI_INTERRUPT_GRANT_MASK)
   1324 
   1325 #define	PCI_INTERRUPT_LATENCY_SHIFT	16
   1326 #define	PCI_INTERRUPT_LATENCY_MASK	0xff
   1327 #define	PCI_INTERRUPT_LATENCY(icr) \
   1328 	    (((icr) >> PCI_INTERRUPT_LATENCY_SHIFT) & PCI_INTERRUPT_LATENCY_MASK)
   1329 
   1330 #define	PCI_INTERRUPT_PIN_SHIFT		8
   1331 #define	PCI_INTERRUPT_PIN_MASK		0xff
   1332 #define	PCI_INTERRUPT_PIN(icr) \
   1333 	    (((icr) >> PCI_INTERRUPT_PIN_SHIFT) & PCI_INTERRUPT_PIN_MASK)
   1334 
   1335 #define	PCI_INTERRUPT_LINE_SHIFT	0
   1336 #define	PCI_INTERRUPT_LINE_MASK		0xff
   1337 #define	PCI_INTERRUPT_LINE(icr) \
   1338 	    (((icr) >> PCI_INTERRUPT_LINE_SHIFT) & PCI_INTERRUPT_LINE_MASK)
   1339 
   1340 #define PCI_INTERRUPT_CODE(lat,gnt,pin,line)		\
   1341 	  ((((lat)&PCI_INTERRUPT_LATENCY_MASK)<<PCI_INTERRUPT_LATENCY_SHIFT)| \
   1342 	   (((gnt)&PCI_INTERRUPT_GRANT_MASK)  <<PCI_INTERRUPT_GRANT_SHIFT)  | \
   1343 	   (((pin)&PCI_INTERRUPT_PIN_MASK)    <<PCI_INTERRUPT_PIN_SHIFT)    | \
   1344 	   (((line)&PCI_INTERRUPT_LINE_MASK)  <<PCI_INTERRUPT_LINE_SHIFT))
   1345 
   1346 #define	PCI_INTERRUPT_PIN_NONE		0x00
   1347 #define	PCI_INTERRUPT_PIN_A		0x01
   1348 #define	PCI_INTERRUPT_PIN_B		0x02
   1349 #define	PCI_INTERRUPT_PIN_C		0x03
   1350 #define	PCI_INTERRUPT_PIN_D		0x04
   1351 #define	PCI_INTERRUPT_PIN_MAX		0x04
   1352 
   1353 /* Header Type 1 (Bridge) configuration registers */
   1354 #define PCI_BRIDGE_BUS_REG		0x18
   1355 #define   PCI_BRIDGE_BUS_PRIMARY	__BITS(0, 7)
   1356 #define   PCI_BRIDGE_BUS_SECONDARY	__BITS(8, 15)
   1357 #define   PCI_BRIDGE_BUS_SUBORDINATE	__BITS(16, 23)
   1358 #define   PCI_BRIDGE_BUS_SEC_LATTIMER	__BITS(24, 31)
   1359 #define   PCI_BRIDGE_BUS_NUM_PRIMARY(reg)			\
   1360 	((uint32_t)__SHIFTOUT((reg), PCI_BRIDGE_BUS_PRIMARY))
   1361 #define   PCI_BRIDGE_BUS_NUM_SECONDARY(reg)			\
   1362 	((uint32_t)__SHIFTOUT((reg), PCI_BRIDGE_BUS_SECONDARY))
   1363 #define   PCI_BRIDGE_BUS_NUM_SUBORDINATE(reg)				\
   1364 	((uint32_t)__SHIFTOUT((reg), PCI_BRIDGE_BUS_SUBORDINATE))
   1365 #define   PCI_BRIDGE_BUS_SEC_LATTIMER_VAL(reg)				\
   1366 	((uint32_t)__SHIFTOUT((reg), PCI_BRIDGE_BUS_SEC_LATTIMER))
   1367 
   1368 /* Minimum size of the window */
   1369 #define  PCI_BRIDGE_IO_MIN	0x00001000UL
   1370 #define  PCI_BRIDGE_MEM_MIN	0x00100000UL
   1371 
   1372 #define PCI_BRIDGE_STATIO_REG		0x1c
   1373 #define	  PCI_BRIDGE_STATIO_IOBASE	__BITS(0, 7)
   1374 #define	  PCI_BRIDGE_STATIO_IOLIMIT	__BITS(8, 15)
   1375 #define	  PCI_BRIDGE_STATIO_STATUS	__BITS(16, 31)
   1376 #define	  PCI_BRIDGE_STATIO_IOADDR	0xf0
   1377 #define	  PCI_BRIDGE_STATIO_IOADDR_TYPE	0x0f	/* Read only */
   1378 #define	  PCI_BRIDGE_STATIO_IOADDR_32	0x01
   1379 #define	  PCI_BRIDGE_STATIO_IOBASE_ADDR(reg)		\
   1380 	((__SHIFTOUT((reg), PCI_BRIDGE_STATIO_IOBASE)	\
   1381 	    & PCI_BRIDGE_STATIO_IOADDR) << 8)
   1382 #define	  PCI_BRIDGE_STATIO_IOLIMIT_ADDR(reg)				\
   1383 	(((__SHIFTOUT((reg), PCI_BRIDGE_STATIO_IOLIMIT)			\
   1384 		& PCI_BRIDGE_STATIO_IOADDR) << 8) | (PCI_BRIDGE_IO_MIN - 1))
   1385 #define	  PCI_BRIDGE_IO_32BITS(reg)	\
   1386 	(((reg) & PCI_BRIDGE_STATIO_IOADDR_TYPE) == PCI_BRIDGE_STATIO_IOADDR_32)
   1387 
   1388 #define PCI_BRIDGE_MEMORY_REG		0x20
   1389 #define	  PCI_BRIDGE_MEMORY_BASE		__BITS(0, 15)
   1390 #define	  PCI_BRIDGE_MEMORY_LIMIT		__BITS(16, 31)
   1391 #define	  PCI_BRIDGE_MEMORY_ADDR		0xfff0
   1392 #define	  PCI_BRIDGE_MEMORY_BASE_ADDR(reg)		\
   1393 	((__SHIFTOUT((reg), PCI_BRIDGE_MEMORY_BASE)	\
   1394 	    & PCI_BRIDGE_MEMORY_ADDR) << 16)
   1395 #define	  PCI_BRIDGE_MEMORY_LIMIT_ADDR(reg)			\
   1396 	(((__SHIFTOUT((reg), PCI_BRIDGE_MEMORY_LIMIT)		\
   1397 		& PCI_BRIDGE_MEMORY_ADDR) << 16) | 0x000fffff)
   1398 
   1399 #define PCI_BRIDGE_PREFETCHMEM_REG	0x24
   1400 #define	  PCI_BRIDGE_PREFETCHMEM_BASE		__BITS(0, 15)
   1401 #define	  PCI_BRIDGE_PREFETCHMEM_LIMIT		__BITS(16, 31)
   1402 #define	  PCI_BRIDGE_PREFETCHMEM_ADDR		0xfff0
   1403 #define	  PCI_BRIDGE_PREFETCHMEM_BASE_ADDR(reg)		\
   1404 	((__SHIFTOUT((reg), PCI_BRIDGE_PREFETCHMEM_BASE)	\
   1405 	    & PCI_BRIDGE_PREFETCHMEM_ADDR) << 16)
   1406 #define	  PCI_BRIDGE_PREFETCHMEM_LIMIT_ADDR(reg)		\
   1407 	(((__SHIFTOUT((reg), PCI_BRIDGE_PREFETCHMEM_LIMIT)	\
   1408 		& PCI_BRIDGE_PREFETCHMEM_ADDR) << 16) | 0x000fffff)
   1409 #define	  PCI_BRIDGE_PREFETCHMEM_64BITS(reg)	((reg) & 0xf)
   1410 
   1411 #define PCI_BRIDGE_PREFETCHBASEUP32_REG	0x28
   1412 #define PCI_BRIDGE_PREFETCHLIMITUP32_REG 0x2c
   1413 
   1414 #define PCI_BRIDGE_IOHIGH_REG		0x30
   1415 #define	  PCI_BRIDGE_IOHIGH_BASE	__BITS(0, 15)
   1416 #define	  PCI_BRIDGE_IOHIGH_LIMIT	__BITS(16, 31)
   1417 
   1418 #define PCI_BRIDGE_EXPROMADDR_REG	0x38
   1419 
   1420 #define PCI_BRIDGE_CONTROL_REG		0x3c /* Upper 16 bit */
   1421 #define	  PCI_BRIDGE_CONTROL		__BITS(16, 31)
   1422 #define   PCI_BRIDGE_CONTROL_PERE		__BIT(16)
   1423 #define   PCI_BRIDGE_CONTROL_SERR		__BIT(17)
   1424 #define   PCI_BRIDGE_CONTROL_ISA		__BIT(18)
   1425 #define   PCI_BRIDGE_CONTROL_VGA		__BIT(19)
   1426 #define   PCI_BRIDGE_CONTROL_VGA16		__BIT(20)
   1427 #define   PCI_BRIDGE_CONTROL_MABRT		__BIT(21)
   1428 #define   PCI_BRIDGE_CONTROL_SECBR		__BIT(22)
   1429 #define   PCI_BRIDGE_CONTROL_SECFASTB2B		__BIT(23)
   1430 #define   PCI_BRIDGE_CONTROL_PRI_DISC_TIMER	__BIT(24)
   1431 #define   PCI_BRIDGE_CONTROL_SEC_DISC_TIMER	__BIT(25)
   1432 #define   PCI_BRIDGE_CONTROL_DISC_TIMER_STAT	__BIT(26)
   1433 #define   PCI_BRIDGE_CONTROL_DISC_TIMER_SERR	__BIT(27)
   1434 /* Reserved					(1 << 12) - (1 << 15) */
   1435 
   1436 /*
   1437  * Vital Product Data resource tags.
   1438  */
   1439 struct pci_vpd_smallres {
   1440 	uint8_t		vpdres_byte0;		/* length of data + tag */
   1441 	/* Actual data. */
   1442 } __packed;
   1443 
   1444 struct pci_vpd_largeres {
   1445 	uint8_t		vpdres_byte0;
   1446 	uint8_t		vpdres_len_lsb;		/* length of data only */
   1447 	uint8_t		vpdres_len_msb;
   1448 	/* Actual data. */
   1449 } __packed;
   1450 
   1451 #define	PCI_VPDRES_ISLARGE(x)			((x) & 0x80)
   1452 
   1453 #define	PCI_VPDRES_SMALL_LENGTH(x)		((x) & 0x7)
   1454 #define	PCI_VPDRES_SMALL_NAME(x)		(((x) >> 3) & 0xf)
   1455 
   1456 #define	PCI_VPDRES_LARGE_NAME(x)		((x) & 0x7f)
   1457 
   1458 #define	PCI_VPDRES_TYPE_COMPATIBLE_DEVICE_ID	0x3	/* small */
   1459 #define	PCI_VPDRES_TYPE_VENDOR_DEFINED		0xe	/* small */
   1460 #define	PCI_VPDRES_TYPE_END_TAG			0xf	/* small */
   1461 
   1462 #define	PCI_VPDRES_TYPE_IDENTIFIER_STRING	0x02	/* large */
   1463 #define	PCI_VPDRES_TYPE_VPD			0x10	/* large */
   1464 
   1465 struct pci_vpd {
   1466 	uint8_t		vpd_key0;
   1467 	uint8_t		vpd_key1;
   1468 	uint8_t		vpd_len;		/* length of data only */
   1469 	/* Actual data. */
   1470 } __packed;
   1471 
   1472 /*
   1473  * Recommended VPD fields:
   1474  *
   1475  *	PN		Part number of assembly
   1476  *	FN		FRU part number
   1477  *	EC		EC level of assembly
   1478  *	MN		Manufacture ID
   1479  *	SN		Serial Number
   1480  *
   1481  * Conditionally recommended VPD fields:
   1482  *
   1483  *	LI		Load ID
   1484  *	RL		ROM Level
   1485  *	RM		Alterable ROM Level
   1486  *	NA		Network Address
   1487  *	DD		Device Driver Level
   1488  *	DG		Diagnostic Level
   1489  *	LL		Loadable Microcode Level
   1490  *	VI		Vendor ID/Device ID
   1491  *	FU		Function Number
   1492  *	SI		Subsystem Vendor ID/Subsystem ID
   1493  *
   1494  * Additional VPD fields:
   1495  *
   1496  *	Z0-ZZ		User/Product Specific
   1497  */
   1498 
   1499 /*
   1500  * PCI Expansion Rom
   1501  */
   1502 
   1503 struct pci_rom_header {
   1504 	uint16_t		romh_magic;	/* 0xAA55 little endian */
   1505 	uint8_t			romh_reserved[22];
   1506 	uint16_t		romh_data_ptr;	/* pointer to pci_rom struct */
   1507 } __packed;
   1508 
   1509 #define	PCI_ROM_HEADER_MAGIC	0xAA55		/* little endian */
   1510 
   1511 struct pci_rom {
   1512 	uint32_t		rom_signature;
   1513 	pci_vendor_id_t		rom_vendor;
   1514 	pci_product_id_t	rom_product;
   1515 	uint16_t		rom_vpd_ptr;	/* reserved in PCI 2.2 */
   1516 	uint16_t		rom_data_len;
   1517 	uint8_t			rom_data_rev;
   1518 	pci_interface_t		rom_interface;	/* the class reg is 24-bits */
   1519 	pci_subclass_t		rom_subclass;	/* in little endian */
   1520 	pci_class_t		rom_class;
   1521 	uint16_t		rom_len;	/* code length / 512 byte */
   1522 	uint16_t		rom_rev;	/* code revision level */
   1523 	uint8_t			rom_code_type;	/* type of code */
   1524 	uint8_t			rom_indicator;
   1525 	uint16_t		rom_reserved;
   1526 	/* Actual data. */
   1527 } __packed;
   1528 
   1529 #define	PCI_ROM_SIGNATURE	0x52494350	/* "PCIR", endian reversed */
   1530 #define	PCI_ROM_CODE_TYPE_X86	0		/* Intel x86 BIOS */
   1531 #define	PCI_ROM_CODE_TYPE_OFW	1		/* Open Firmware */
   1532 #define	PCI_ROM_CODE_TYPE_HPPA	2		/* HP PA/RISC */
   1533 #define	PCI_ROM_CODE_TYPE_EFI	3		/* EFI Image */
   1534 
   1535 #define	PCI_ROM_INDICATOR_LAST	0x80
   1536 
   1537 /*
   1538  * Threshold below which 32bit PCI DMA needs bouncing.
   1539  */
   1540 #define PCI32_DMA_BOUNCE_THRESHOLD	0x100000000ULL
   1541 
   1542 /*
   1543  * PCI-X 2.0/ PCI-express Extended Capability List
   1544  */
   1545 
   1546 #define	PCI_EXTCAPLIST_BASE	0x100
   1547 
   1548 #define	PCI_EXTCAPLIST_CAP(ecr)		((ecr) & 0xffff)
   1549 #define	PCI_EXTCAPLIST_VERSION(ecr)	(((ecr) >> 16) & 0xf)
   1550 #define	PCI_EXTCAPLIST_NEXT(ecr)	(((ecr) >> 20) & 0xfff)
   1551 
   1552 /* Extended Capability Identification Numbers */
   1553 
   1554 #define	PCI_EXTCAP_AER		0x0001	/* Advanced Error Reporting */
   1555 #define	PCI_EXTCAP_VC		0x0002	/* Virtual Channel if MFVC Ext Cap not set */
   1556 #define	PCI_EXTCAP_SERNUM	0x0003	/* Device Serial Number */
   1557 #define	PCI_EXTCAP_PWRBDGT	0x0004	/* Power Budgeting */
   1558 #define	PCI_EXTCAP_RCLINK_DCL	0x0005	/* Root Complex Link Declaration */
   1559 #define	PCI_EXTCAP_RCLINK_CTL	0x0006	/* Root Complex Internal Link Control */
   1560 #define	PCI_EXTCAP_RCEC_ASSOC	0x0007	/* Root Complex Event Collector Association */
   1561 #define	PCI_EXTCAP_MFVC		0x0008	/* Multi-Function Virtual Channel */
   1562 #define	PCI_EXTCAP_VC2		0x0009	/* Virtual Channel if MFVC Ext Cap set */
   1563 #define	PCI_EXTCAP_RCRB		0x000a	/* RCRB Header */
   1564 #define	PCI_EXTCAP_VENDOR	0x000b	/* Vendor Unique */
   1565 #define	PCI_EXTCAP_CAC		0x000c	/* Configuration Access Correction -- obsolete */
   1566 #define	PCI_EXTCAP_ACS		0x000d	/* Access Control Services */
   1567 #define	PCI_EXTCAP_ARI		0x000e	/* Alternative Routing-ID Interpretation */
   1568 #define	PCI_EXTCAP_ATS		0x000f	/* Address Translation Services */
   1569 #define	PCI_EXTCAP_SRIOV	0x0010	/* Single Root IO Virtualization */
   1570 #define	PCI_EXTCAP_MRIOV	0x0011	/* Multiple Root IO Virtualization */
   1571 #define	PCI_EXTCAP_MCAST	0x0012	/* Multicast */
   1572 #define	PCI_EXTCAP_PAGE_REQ	0x0013	/* Page Request */
   1573 #define	PCI_EXTCAP_AMD		0x0014	/* Reserved for AMD */
   1574 #define	PCI_EXTCAP_RESIZBAR	0x0015	/* Resizable BAR */
   1575 #define	PCI_EXTCAP_DPA		0x0016	/* Dynamic Power Allocation */
   1576 #define	PCI_EXTCAP_TPH_REQ	0x0017	/* TPH Requester */
   1577 #define	PCI_EXTCAP_LTR		0x0018	/* Latency Tolerance Reporting */
   1578 #define	PCI_EXTCAP_SEC_PCIE	0x0019	/* Secondary PCI Express */
   1579 #define	PCI_EXTCAP_PMUX		0x001a	/* Protocol Multiplexing */
   1580 #define	PCI_EXTCAP_PASID	0x001b	/* Process Address Space ID */
   1581 #define	PCI_EXTCAP_LNR		0x001c	/* LN Requester */
   1582 #define	PCI_EXTCAP_DPC		0x001d	/* Downstream Port Containment */
   1583 #define	PCI_EXTCAP_L1PM		0x001e	/* L1 PM Substates */
   1584 #define	PCI_EXTCAP_PTM		0x001f	/* Precision Time Management */
   1585 #define	PCI_EXTCAP_MPCIE	0x0020	/* M-PCIe */
   1586 #define	PCI_EXTCAP_FRSQ		0x0021	/* Function Reading Status Queueing */
   1587 #define	PCI_EXTCAP_RTR		0x0022	/* Readiness Time Reporting */
   1588 #define	PCI_EXTCAP_DESIGVNDSP	0x0023	/* Designated Vendor-Specific */
   1589 #define	PCI_EXTCAP_VF_RESIZBAR	0x0024	/* VF Resizable BAR */
   1590 #define	PCI_EXTCAP_DLF		0x0025	/* Data link Feature */
   1591 #define	PCI_EXTCAP_PL16G	0x0026	/* Physical Layer 16.0 GT/s */
   1592 #define	PCI_EXTCAP_LMR		0x0027	/* Lane Margining at the Receiver */
   1593 #define	PCI_EXTCAP_HIERARCHYID	0x0028	/* Hierarchy ID */
   1594 #define	PCI_EXTCAP_NPEM		0x0029	/* Native PCIe Enclosure Management */
   1595 #define	PCI_EXTCAP_PL32G	0x002a	/* Physical Layer 32.0 GT/s */
   1596 #define	PCI_EXTCAP_AP		0x002b	/* Alternate Protocol */
   1597 #define	PCI_EXTCAP_SFI		0x002c	/* System Firmware Intermediary */
   1598 
   1599 /*
   1600  * Extended capability ID: 0x0001
   1601  * Advanced Error Reporting
   1602  */
   1603 #define	PCI_AER_UC_STATUS	0x04	/* Uncorrectable Error Status Reg. */
   1604 #define	  PCI_AER_UC_UNDEFINED			__BIT(0)
   1605 #define	  PCI_AER_UC_DL_PROTOCOL_ERROR		__BIT(4)
   1606 #define	  PCI_AER_UC_SURPRISE_DOWN_ERROR	__BIT(5)
   1607 #define	  PCI_AER_UC_POISONED_TLP		__BIT(12)
   1608 #define	  PCI_AER_UC_FC_PROTOCOL_ERROR		__BIT(13)
   1609 #define	  PCI_AER_UC_COMPLETION_TIMEOUT		__BIT(14)
   1610 #define	  PCI_AER_UC_COMPLETER_ABORT		__BIT(15)
   1611 #define	  PCI_AER_UC_UNEXPECTED_COMPLETION	__BIT(16)
   1612 #define	  PCI_AER_UC_RECEIVER_OVERFLOW		__BIT(17)
   1613 #define	  PCI_AER_UC_MALFORMED_TLP		__BIT(18)
   1614 #define	  PCI_AER_UC_ECRC_ERROR			__BIT(19)
   1615 #define	  PCI_AER_UC_UNSUPPORTED_REQUEST_ERROR	__BIT(20)
   1616 #define	  PCI_AER_UC_ACS_VIOLATION		__BIT(21)
   1617 #define	  PCI_AER_UC_INTERNAL_ERROR		__BIT(22)
   1618 #define	  PCI_AER_UC_MC_BLOCKED_TLP		__BIT(23)
   1619 #define	  PCI_AER_UC_ATOMIC_OP_EGRESS_BLOCKED	__BIT(24)
   1620 #define	  PCI_AER_UC_TLP_PREFIX_BLOCKED_ERROR	__BIT(25)
   1621 #define	  PCI_AER_UC_POISONTLP_EGRESS_BLOCKED	__BIT(26)
   1622 #define	PCI_AER_UC_MASK		0x08	/* Uncorrectable Error Mask Register */
   1623 	  /* Shares bits with UC_STATUS */
   1624 #define	PCI_AER_UC_SEVERITY	0x0c	/* Uncorrectable Error Severity Reg. */
   1625 	  /* Shares bits with UC_STATUS */
   1626 #define	PCI_AER_COR_STATUS	0x10	/* Correctable Error Status Register */
   1627 #define	  PCI_AER_COR_RECEIVER_ERROR		__BIT(0)
   1628 #define	  PCI_AER_COR_BAD_TLP			__BIT(6)
   1629 #define	  PCI_AER_COR_BAD_DLLP			__BIT(7)
   1630 #define	  PCI_AER_COR_REPLAY_NUM_ROLLOVER	__BIT(8)
   1631 #define	  PCI_AER_COR_REPLAY_TIMER_TIMEOUT	__BIT(12)
   1632 #define	  PCI_AER_COR_ADVISORY_NF_ERROR		__BIT(13)
   1633 #define	  PCI_AER_COR_INTERNAL_ERROR		__BIT(14)
   1634 #define	  PCI_AER_COR_HEADER_LOG_OVERFLOW	__BIT(15)
   1635 #define	PCI_AER_COR_MASK	0x14	/* Correctable Error Mask Register */
   1636 	  /* Shares bits with COR_STATUS */
   1637 #define	PCI_AER_CAP_CONTROL	0x18	/* AE Capabilities and Control Reg. */
   1638 #define	  PCI_AER_FIRST_ERROR_PTR		__BITS(4, 0)
   1639 #define	  PCI_AER_ECRC_GEN_CAPABLE		__BIT(5)
   1640 #define	  PCI_AER_ECRC_GEN_ENABLE		__BIT(6)
   1641 #define	  PCI_AER_ECRC_CHECK_CAPABLE		__BIT(7)
   1642 #define	  PCI_AER_ECRC_CHECK_ENABLE		__BIT(8)
   1643 #define	  PCI_AER_MULT_HDR_CAPABLE		__BIT(9)
   1644 #define	  PCI_AER_MULT_HDR_ENABLE		__BIT(10)
   1645 #define	  PCI_AER_TLP_PREFIX_LOG_PRESENT	__BIT(11)
   1646 #define	  PCI_AER_COMPTOUTPRFXHDRLOG_CAP	__BIT(12)
   1647 #define	PCI_AER_HEADER_LOG	0x1c	/* Header Log Register */
   1648 #define	PCI_AER_ROOTERR_CMD	0x2c	/* Root Error Command Register */
   1649 					/* Only for root complex ports */
   1650 #define	  PCI_AER_ROOTERR_COR_ENABLE		__BIT(0)
   1651 #define	  PCI_AER_ROOTERR_NF_ENABLE		__BIT(1)
   1652 #define	  PCI_AER_ROOTERR_F_ENABLE		__BIT(2)
   1653 #define	PCI_AER_ROOTERR_STATUS	0x30	/* Root Error Status Register */
   1654 					/* Only for root complex ports */
   1655 #define	  PCI_AER_ROOTERR_COR_ERR		__BIT(0)
   1656 #define	  PCI_AER_ROOTERR_MULTI_COR_ERR		__BIT(1)
   1657 #define	  PCI_AER_ROOTERR_UC_ERR		__BIT(2)
   1658 #define	  PCI_AER_ROOTERR_MULTI_UC_ERR		__BIT(3)
   1659 #define	  PCI_AER_ROOTERR_FIRST_UC_FATAL	__BIT(4)
   1660 #define	  PCI_AER_ROOTERR_NF_ERR		__BIT(5)
   1661 #define	  PCI_AER_ROOTERR_F_ERR			__BIT(6)
   1662 #define	  PCI_AER_ROOTERR_INT_MESSAGE		__BITS(31, 27)
   1663 #define	PCI_AER_ERRSRC_ID	0x34	/* Error Source Identification Reg. */
   1664 #define	  PCI_AER_ERRSRC_ID_ERR_COR		__BITS(15, 0)
   1665 #define	  PCI_AER_ERRSRC_ID_ERR_UC		__BITS(31, 16)
   1666 					/* Only for root complex ports */
   1667 #define	PCI_AER_TLP_PREFIX_LOG	0x38	/*TLP Prefix Log Register */
   1668 					/* Only for TLP prefix functions */
   1669 
   1670 /*
   1671  * Extended capability ID: 0x0002, 0x0009
   1672  * Virtual Channel
   1673  */
   1674 #define	PCI_VC_CAP1		0x04	/* Port VC Capability Register 1 */
   1675 #define	  PCI_VC_CAP1_EXT_COUNT			__BITS(2, 0)
   1676 #define	  PCI_VC_CAP1_LOWPRI_EXT_COUNT		__BITS(6, 4)
   1677 #define	  PCI_VC_CAP1_REFCLK			__BITS(9, 8)
   1678 #define	  PCI_VC_CAP1_REFCLK_100NS		0x0
   1679 #define	  PCI_VC_CAP1_PORT_ARB_TABLE_SIZE	__BITS(11, 10)
   1680 #define	PCI_VC_CAP2		0x08	/* Port VC Capability Register 2 */
   1681 #define	  PCI_VC_CAP2_ARB_CAP_HW_FIXED_SCHEME	__BIT(0)
   1682 #define	  PCI_VC_CAP2_ARB_CAP_WRR_32		__BIT(1)
   1683 #define	  PCI_VC_CAP2_ARB_CAP_WRR_64		__BIT(2)
   1684 #define	  PCI_VC_CAP2_ARB_CAP_WRR_128		__BIT(3)
   1685 #define	  PCI_VC_CAP2_ARB_TABLE_OFFSET		__BITS(31, 24)
   1686 #define	PCI_VC_CONTROL		0x0c	/* Port VC Control Register (16bit) */
   1687 #define	  PCI_VC_CONTROL_LOAD_VC_ARB_TABLE	__BIT(0)
   1688 #define	  PCI_VC_CONTROL_VC_ARB_SELECT		__BITS(3, 1)
   1689 #define	PCI_VC_STATUS		0x0e	/* Port VC Status Register (16bit) */
   1690 #define	  PCI_VC_STATUS_LOAD_VC_ARB_TABLE	__BIT(0)
   1691 #define	PCI_VC_RESOURCE_CAP(n)	(0x10 + ((n) * 0x0c))	/* VC Resource Capability Register */
   1692 #define	  PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_HW_FIXED_SCHEME __BIT(0)
   1693 #define	  PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_32          __BIT(1)
   1694 #define	  PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_64          __BIT(2)
   1695 #define	  PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_128         __BIT(3)
   1696 #define	  PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_TWRR_128        __BIT(4)
   1697 #define	  PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_256         __BIT(5)
   1698 #define	  PCI_VC_RESOURCE_CAP_ADV_PKT_SWITCH	__BIT(14)
   1699 #define	  PCI_VC_RESOURCE_CAP_REJCT_SNOOP_TRANS	__BIT(15)
   1700 #define	  PCI_VC_RESOURCE_CAP_MAX_TIME_SLOTS	__BITS(22, 16)
   1701 #define	  PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET   __BITS(31, 24)
   1702 #define	PCI_VC_RESOURCE_CTL(n)	(0x14 + ((n) * 0x0c))	/* VC Resource Control Register */
   1703 #define	  PCI_VC_RESOURCE_CTL_TCVC_MAP		__BITS(7, 0)
   1704 #define	  PCI_VC_RESOURCE_CTL_LOAD_PORT_ARB_TABLE __BIT(16)
   1705 #define	  PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT	__BITS(19, 17)
   1706 #define	  PCI_VC_RESOURCE_CTL_VC_ID		__BITS(26, 24)
   1707 #define	  PCI_VC_RESOURCE_CTL_VC_ENABLE		__BIT(31)
   1708 #define	PCI_VC_RESOURCE_STA(n)	(0x18 + ((n) * 0x0c))	/* VC Resource Status Register */
   1709 #define	  PCI_VC_RESOURCE_STA_PORT_ARB_TABLE	__BIT(0)
   1710 #define	  PCI_VC_RESOURCE_STA_VC_NEG_PENDING	__BIT(1)
   1711 
   1712 /*
   1713  * Extended capability ID: 0x0003
   1714  * Serial Number
   1715  */
   1716 #define	PCI_SERIAL_LOW		0x04
   1717 #define	PCI_SERIAL_HIGH		0x08
   1718 
   1719 /*
   1720  * Extended capability ID: 0x0004
   1721  * Power Budgeting
   1722  */
   1723 #define	PCI_PWRBDGT_DSEL	0x04	/* Data Select */
   1724 #define	PCI_PWRBDGT_DATA	0x08	/* Data */
   1725 #define	PCI_PWRBDGT_DATA_BASEPWR	__BITS(7, 0)	/* Base Power */
   1726 #define	PCI_PWRBDGT_DATA_SCALE		__BITS(9, 8)	/* Data Scale */
   1727 #define	PCI_PWRBDGT_PM_SUBSTAT		__BITS(12, 10)	/* PM Sub State */
   1728 #define	PCI_PWRBDGT_PM_STAT		__BITS(14, 13)	/* PM State */
   1729 #define	PCI_PWRBDGT_TYPE		__BITS(17, 15)	/* Type */
   1730 #define	PCI_PWRBDGT_PWRRAIL		__BITS(20, 18)	/* Power Rail */
   1731 #define	PCI_PWRBDGT_CAP		0x0c	/* Capability */
   1732 #define	PCI_PWRBDGT_CAP_SYSALLOC	__BIT(0)	/* System Allocated */
   1733 
   1734 /*
   1735  * Extended capability ID: 0x0005
   1736  * Root Complex Link Declaration
   1737  */
   1738 #define	PCI_RCLINK_DCL_ESDESC	0x04	/* Element Self Description */
   1739 #define	PCI_RCLINK_DCL_ESDESC_ELMTYPE __BITS(3, 0)	/* Element Type */
   1740 #define	PCI_RCLINK_DCL_ESDESC_NUMLINKENT __BITS(15, 8) /* Num of Link Entries*/
   1741 #define	PCI_RCLINK_DCL_ESDESC_COMPID  __BITS(23, 16)	/* Component ID */
   1742 #define	PCI_RCLINK_DCL_ESDESC_PORTNUM __BITS(31, 24)	/* Port Number */
   1743 #define	PCI_RCLINK_DCL_LINKENTS	0x10	/* Link Entries */
   1744 #define	PCI_RCLINK_DCL_LINKDESC(x)	/* Link Description */	\
   1745 	(PCI_RCLINK_DCL_LINKENTS + ((x) * 16))
   1746 #define	PCI_RCLINK_DCL_LINKDESC_LVALID	__BIT(0)	/* Link Valid */
   1747 #define	PCI_RCLINK_DCL_LINKDESC_LTYPE	__BIT(1)	/* Link Type */
   1748 #define	PCI_RCLINK_DCL_LINKDESC_ARCRBH	__BIT(2)    /* Associate RCRB Header */
   1749 #define	PCI_RCLINK_DCL_LINKDESC_TCOMPID	__BITS(23, 16) /* Target Component ID*/
   1750 #define	PCI_RCLINK_DCL_LINKDESC_TPNUM	__BITS(31, 24) /* Target Port Number */
   1751 #define	PCI_RCLINK_DCL_LINKADDR_LT0_LO(x) /* LT0: Link Address Low */	\
   1752 	(PCI_RCLINK_DCL_LINKENTS + ((x) * 16) + 0x08)
   1753 #define	PCI_RCLINK_DCL_LINKADDR_LT0_HI(x) /* LT0: Link Address High */	\
   1754 	(PCI_RCLINK_DCL_LINKENTS + ((x) * 16) + 0x0c)
   1755 #define	PCI_RCLINK_DCL_LINKADDR_LT1_LO(x) /* LT1: Config Space (low) */	\
   1756 	(PCI_RCLINK_DCL_LINKENTS + ((x) * 16) + 0x08)
   1757 #define	PCI_RCLINK_DCL_LINKADDR_LT1_N	__BITS(2, 0)	/* N */
   1758 #define	PCI_RCLINK_DCL_LINKADDR_LT1_FUNC __BITS(14, 12)	/* Function Number */
   1759 #define	PCI_RCLINK_DCL_LINKADDR_LT1_DEV	__BITS(19, 15)	/* Device Number */
   1760 #define	PCI_RCLINK_DCL_LINKADDR_LT1_BUS(N) __BITS(19 + (N), 20) /* Bus Number*/
   1761 #define	PCI_RCLINK_DCL_LINKADDR_LT1_BAL(N) __BITS(31, 20 + (N)) /* BAddr(L) */
   1762 #define	PCI_RCLINK_DCL_LINKADDR_LT1_HI(x) /* LT1: Config Space Base Addr(H) */\
   1763 	(PCI_RCLINK_DCL_LINKENTS + ((x) * 16) + 0x0c)
   1764 
   1765 /*
   1766  * Extended capability ID: 0x0006
   1767  * Root Complex Internal Link Control
   1768  */
   1769 
   1770 /*
   1771  * Extended capability ID: 0x0007
   1772  * Root Complex Event Collector Association
   1773  */
   1774 #define	PCI_RCEC_ASSOC_ASSOCBITMAP 0x04	/* Association Bitmap */
   1775 #define	PCI_RCEC_ASSOC_ASSOCBUSNUM 0x08	/* Associcated Bus Number */
   1776 #define	PCI_RCEC_ASSOCBUSNUM_RCECNEXT __BITS(15, 8)	/* RCEC Next Bus */
   1777 #define	PCI_RCEC_ASSOCBUSNUM_RCECLAST __BITS(23, 16)	/* RCEC Last Bus */
   1778 
   1779 /*
   1780  * Extended capability ID: 0x0008
   1781  * Multi-Function Virtual Channel
   1782  */
   1783 
   1784 /*
   1785  * Extended capability ID: 0x0009
   1786  * Virtual Channel if MFVC Ext Cap set
   1787  */
   1788 
   1789 /*
   1790  * Extended capability ID: 0x000a
   1791  * RCRB Header
   1792  */
   1793 
   1794 /*
   1795  * Extended capability ID: 0x000b
   1796  * Vendor Unique
   1797  */
   1798 
   1799 /*
   1800  * Extended capability ID: 0x000c
   1801  * Configuration Access Correction
   1802  */
   1803 
   1804 /*
   1805  * Extended capability ID: 0x000d
   1806  * Access Control Services
   1807  */
   1808 #define	PCI_ACS_CAP	0x04	/* Capability Register */
   1809 #define PCI_ACS_CAP_V	__BIT(0)	/* Source Validation */
   1810 #define PCI_ACS_CAP_B	__BIT(1)	/* Transaction Blocking */
   1811 #define PCI_ACS_CAP_R	__BIT(2)	/* P2P Request Redirect */
   1812 #define PCI_ACS_CAP_C	__BIT(3)	/* P2P Completion Redirect */
   1813 #define PCI_ACS_CAP_U	__BIT(4)	/* Upstream Forwarding */
   1814 #define PCI_ACS_CAP_E	__BIT(5)	/* Egress Control */
   1815 #define PCI_ACS_CAP_T	__BIT(6)	/* Direct Translated P2P */
   1816 #define PCI_ACS_CAP_ECVSIZE __BITS(15, 8) /* Egress Control Vector Size */
   1817 #define	PCI_ACS_CTL	0x04	/* Control Register */
   1818 #define PCI_ACS_CTL_V	__BIT(0 + 16)	/* Source Validation Enable */
   1819 #define PCI_ACS_CTL_B	__BIT(1 + 16)	/* Transaction Blocking Enable */
   1820 #define PCI_ACS_CTL_R	__BIT(2 + 16)	/* P2P Request Redirect Enable */
   1821 #define PCI_ACS_CTL_C	__BIT(3 + 16)	/* P2P Completion Redirect Enable */
   1822 #define PCI_ACS_CTL_U	__BIT(4 + 16)	/* Upstream Forwarding Enable */
   1823 #define PCI_ACS_CTL_E	__BIT(5 + 16)	/* Egress Control Enable */
   1824 #define PCI_ACS_CTL_T	__BIT(6 + 16)	/* Direct Translated P2P Enable */
   1825 #define	PCI_ACS_ECV	0x08	/* Egress Control Vector */
   1826 
   1827 /*
   1828  * Extended capability ID: 0x000e
   1829  * ARI
   1830  */
   1831 #define PCI_ARI_CAP	0x04	/* Capability Register */
   1832 #define PCI_ARI_CAP_M		__BIT(0)	/* MFVC Function Groups Cap. */
   1833 #define PCI_ARI_CAP_A		__BIT(1)	/* ACS Function Groups Cap. */
   1834 #define PCI_ARI_CAP_NXTFN	__BITS(15, 8)	/* Next Function Number */
   1835 #define PCI_ARI_CTL	0x04	/* Control Register */
   1836 #define PCI_ARI_CTL_M		__BIT(16)	/* MFVC Function Groups Ena. */
   1837 #define PCI_ARI_CTL_A		__BIT(17)	/* ACS Function Groups Ena. */
   1838 #define PCI_ARI_CTL_FUNCGRP	__BITS(22, 20)	/* Function Group */
   1839 
   1840 /*
   1841  * Extended capability ID: 0x000f
   1842  * Address Translation Services
   1843  */
   1844 #define	PCI_ATS_CAP	0x04	/* Capability Register */
   1845 #define	PCI_ATS_CAP_INVQDEPTH	__BITS(4, 0)	/* Invalidate Queue Depth */
   1846 #define	PCI_ATS_CAP_PALIGNREQ	__BIT(5)	/* Page Aligned Request */
   1847 #define	PCI_ATS_CAP_GLOBALINVL	__BIT(6)	/* Global Invalidate Support */
   1848 #define	PCI_ATS_CAP_RELAXORD	__BIT(7)	/* Relaxed Ordering */
   1849 #define	PCI_ATS_CTL	0x04	/* Control Register */
   1850 #define	PCI_ATS_CTL_STU		__BITS(20, 16)	/* Smallest Translation Unit */
   1851 #define	PCI_ATS_CTL_EN		__BIT(31)	/* Enable */
   1852 
   1853 /*
   1854  * Extended capability ID: 0x0010
   1855  * SR-IOV
   1856  */
   1857 #define	PCI_SRIOV_CAP		0x04	/* SR-IOV Capabilities */
   1858 #define	  PCI_SRIOV_CAP_VF_MIGRATION		__BIT(0)
   1859 #define	  PCI_SRIOV_CAP_ARI_CAP_HIER_PRESERVED	__BIT(1)
   1860 #define	  PCI_SRIOV_CAP_VF_MIGRATION_INTMSG_N	__BITS(31, 21)
   1861 #define	PCI_SRIOV_CTL		0x08	/* SR-IOV Control (16bit) */
   1862 #define	  PCI_SRIOV_CTL_VF_ENABLE		__BIT(0)
   1863 #define	  PCI_SRIOV_CTL_VF_MIGRATION_SUPPORT	__BIT(1)
   1864 #define	  PCI_SRIOV_CTL_VF_MIGRATION_INT_ENABLE	__BIT(2)
   1865 #define	  PCI_SRIOV_CTL_VF_MSE			__BIT(3)
   1866 #define	  PCI_SRIOV_CTL_ARI_CAP_HIER		__BIT(4)
   1867 #define	PCI_SRIOV_STA		0x0a	/* SR-IOV Status (16bit) */
   1868 #define	  PCI_SRIOV_STA_VF_MIGRATION		__BIT(0)
   1869 #define	PCI_SRIOV_INITIAL_VFS	0x0c	/* InitialVFs (16bit) */
   1870 #define	PCI_SRIOV_TOTAL_VFS	0x0e	/* TotalVFs (16bit) */
   1871 #define	PCI_SRIOV_NUM_VFS	0x10	/* NumVFs (16bit) */
   1872 #define	PCI_SRIOV_FUNC_DEP_LINK	0x12	/* Function Dependency Link (16bit) */
   1873 #define	PCI_SRIOV_VF_OFF	0x14	/* First VF Offset (16bit) */
   1874 #define	PCI_SRIOV_VF_STRIDE	0x16	/* VF Stride (16bit) */
   1875 #define	PCI_SRIOV_VF_DID	0x1a	/* VF Device ID (16bit) */
   1876 #define	PCI_SRIOV_PAGE_CAP	0x1c	/* Supported Page Sizes */
   1877 #define	PCI_SRIOV_PAGE_SIZE	0x20	/* System Page Size */
   1878 #define	  PCI_SRIOV_BASE_PAGE_SHIFT	12
   1879 #define	PCI_SRIOV_BARS		0x24	/* VF BAR0-5 */
   1880 #define	PCI_SRIOV_BAR(x)	(PCI_SRIOV_BARS + ((x) * 4))
   1881 #define	PCI_SRIOV_VF_MIG_STA_AR	0x3c	/* VF Migration State Array Offset */
   1882 #define	  PCI_SRIOV_VF_MIG_STA_OFFSET	__BITS(31, 3)
   1883 #define	  PCI_SRIOV_VF_MIG_STA_BIR	__BITS(2, 0)
   1884 
   1885 /*
   1886  * Extended capability ID: 0x0011
   1887  * Multiple Root IO Virtualization
   1888  */
   1889 
   1890 /*
   1891  * Extended capability ID: 0x0012
   1892  * Multicast
   1893  */
   1894 #define	PCI_MCAST_CAP	0x04	/* Capability Register */
   1895 #define	PCI_MCAST_CAP_MAXGRP	__BITS(5, 0)	/* Max Group */
   1896 #define	PCI_MCAST_CAP_WINSIZEREQ __BITS(13, 8)	/* Window Size Requested  */
   1897 #define	PCI_MCAST_CAP_ECRCREGEN	__BIT(15)	/* ECRC Regen. Supported */
   1898 #define	PCI_MCAST_CTL	0x04	/* Control Register */
   1899 #define	PCI_MCAST_CTL_NUMGRP	__BITS(5+16, 16) /* Num Group */
   1900 #define	PCI_MCAST_CTL_ENA	__BIT(15+16)	/* Enable */
   1901 #define	PCI_MCAST_BARL	0x08	/* Base Address Register (low) */
   1902 #define	PCI_MCAST_BARL_INDPOS	__BITS(5, 0)	/* Index Position */
   1903 #define	PCI_MCAST_BARL_ADDR	__BITS(31, 12)	/* Base Address Register(low)*/
   1904 #define	PCI_MCAST_BARH	0x0c	/* Base Address Register (high) */
   1905 #define	PCI_MCAST_RECVL	0x10	/* Receive Register (low) */
   1906 #define	PCI_MCAST_RECVH	0x14	/* Receive Register (high) */
   1907 #define	PCI_MCAST_BLOCKALLL 0x18 /* Block All Register (low) */
   1908 #define	PCI_MCAST_BLOCKALLH 0x1c /* Block All Register (high) */
   1909 #define	PCI_MCAST_BLOCKUNTRNSL 0x20 /* Block Untranslated Register (low) */
   1910 #define	PCI_MCAST_BLOCKUNTRNSH 0x24 /* Block Untranslated Register (high) */
   1911 #define	PCI_MCAST_OVERLAYL 0x28 /* Overlay BAR (low) */
   1912 #define	PCI_MCAST_OVERLAYL_SIZE	__BITS(5, 0)	/* Overlay Size */
   1913 #define	PCI_MCAST_OVERLAYL_ADDR	__BITS(31, 6)	/* Overlay BAR (low) */
   1914 #define	PCI_MCAST_OVERLAYH 0x2c /* Overlay BAR (high) */
   1915 
   1916 /*
   1917  * Extended capability ID: 0x0013
   1918  * Page Request
   1919  */
   1920 #define	PCI_PAGE_REQ_CTL	0x04	/* Control Register */
   1921 #define	PCI_PAGE_REQ_CTL_E	__BIT(0)	/* Enable */
   1922 #define	PCI_PAGE_REQ_CTL_R	__BIT(1)	/* Reset */
   1923 #define	PCI_PAGE_REQ_STA	0x04	/* Status Register */
   1924 #define	PCI_PAGE_REQ_STA_RF	__BIT(0+16)	/* Response Failure */
   1925 #define	PCI_PAGE_REQ_STA_UPRGI	__BIT(1+16)   /* Unexpected Page Req Grp Idx */
   1926 #define	PCI_PAGE_REQ_STA_S	__BIT(8+16)	/* Stopped */
   1927 #define	PCI_PAGE_REQ_STA_PASIDR	__BIT(15+16)  /* PRG Response PASID Required */
   1928 #define	PCI_PAGE_REQ_OUTSTCAPA	0x08	/* Outstanding Page Request Capacity */
   1929 #define	PCI_PAGE_REQ_OUTSTALLOC	0x0c  /* Outstanding Page Request Allocation */
   1930 
   1931 /*
   1932  * Extended capability ID: 0x0014
   1933  * Enhanced Allocation
   1934  */
   1935 #define	PCI_EA_CAP1	0x00	/* Capability First */
   1936 #define	PCI_EA_CAP1_NUMENTRIES	__BITS(21, 16)	/* Num Entries */
   1937 #define	PCI_EA_CAP2	0x04	/* Capability Second (for type1) */
   1938 #define	PCI_EA_CAP2_SECONDARY	__BITS(7, 0)   /* Fixed Secondary Bus No. */
   1939 #define	PCI_EA_CAP2_SUBORDINATE	__BITS(15, 8)  /* Fixed Subordinate Bus No. */
   1940 
   1941 /* Bit definitions for the first DW of each entry */
   1942 #define PCI_EA_ES	__BITS(2, 0)	/* Entry Size */
   1943 #define PCI_EA_BEI	__BITS(7, 4)	/* BAR Equivalent Indicator */
   1944 #define  PCI_EA_BEI_BAR0	0	/* BAR0 (10h) */
   1945 #define  PCI_EA_BEI_BAR1	1	/* BAR1 (14h) */
   1946 #define  PCI_EA_BEI_BAR2	2	/* BAR2 (18h) */
   1947 #define  PCI_EA_BEI_BAR3	3	/* BAR3 (1ch) */
   1948 #define  PCI_EA_BEI_BAR4	4	/* BAR4 (20h) */
   1949 #define  PCI_EA_BEI_BAR5	5	/* BAR5 (24h) */
   1950 #define  PCI_EA_BEI_BEHIND	6	/* Behind the function (for type1) */
   1951 #define  PCI_EA_BEI_NOTIND	7	/* Not Indicated */
   1952 #define  PCI_EA_BEI_EXPROM	8	/* Expansion ROM */
   1953 #define  PCI_EA_BEI_VFBAR0	9	/* VF BAR0 */
   1954 #define  PCI_EA_BEI_VFBAR1	10	/* VF BAR1 */
   1955 #define  PCI_EA_BEI_VFBAR2	11	/* VF BAR2 */
   1956 #define  PCI_EA_BEI_VFBAR3	12	/* VF BAR3 */
   1957 #define  PCI_EA_BEI_VFBAR4	13	/* VF BAR4 */
   1958 #define  PCI_EA_BEI_VFBAR5	14	/* VF BAR5 */
   1959 #define  PCI_EA_BEI_RESERVED	15	/* Reserved (treat as Not Indicated) */
   1960 #define PCI_EA_PP	__BITS(15, 8)	/* Primary Properties */
   1961 #define PCI_EA_SP	__BITS(23, 16)	/* Secondary Properties */
   1962 /* PP and SP's values */
   1963 #define  PCI_EA_PROP_MEM_NONPREF	0x00	/* Memory Space, Non-Prefetchable */
   1964 #define  PCI_EA_PROP_MEM_PREF		0x01	/* Memory Space, Prefetchable */
   1965 #define  PCI_EA_PROP_IO			0x02	/* I/O Space */
   1966 #define  PCI_EA_PROP_VF_MEM_NONPREF	0x03	/* Resource for VF use. Mem. Non-Pref */
   1967 #define  PCI_EA_PROP_VF_MEM_PREF	0x04	/* Resource for VF use. Mem. Prefetch */
   1968 #define  PCI_EA_PROP_BB_MEM_NONPREF	0x05	/* Behind Bridge: MEM. Non-Pref */
   1969 #define  PCI_EA_PROP_BB_MEM_PREF	0x06	/* Behind Bridge: MEM. Prefetch */
   1970 #define  PCI_EA_PROP_BB_IO		0x07	/* Behind Bridge: I/O Space */
   1971 #define  PCI_EA_PROP_MEM_UNAVAIL	0xfd	/* Memory Space Unavailable */
   1972 #define  PCI_EA_PROP_IO_UNAVAIL		0xfe	/* IO Space Unavailable */
   1973 #define  PCI_EA_PROP_UNAVAIL		0xff	/* Entry Unavailable for use */
   1974 #define PCI_EA_W	__BIT(30)	/* Writable */
   1975 #define PCI_EA_E	__BIT(31)	/* Enable for this entry */
   1976 
   1977 #define PCI_EA_LOWMASK	__BITS(31, 2)	/* Low register's mask */
   1978 #define PCI_EA_BASEMAXOFFSET_S	__BIT(1)	/* Field Size */
   1979 #define PCI_EA_BASEMAXOFFSET_64BIT __BIT(1)	/* 64bit */
   1980 #define PCI_EA_BASEMAXOFFSET_32BIT 0		/* 32bit */
   1981 
   1982 /*
   1983  * Extended capability ID: 0x0015
   1984  * Resizable BAR
   1985  */
   1986 #define	PCI_RESIZBAR_CAP0	0x04	/* Capability Register(0) */
   1987 #define	PCI_RESIZBAR_CAP(x)	(PCI_RESIZBAR_CAP0 + ((x) * 8))
   1988 #define	PCI_RESIZBAR_CAP_SIZEMASK __BITS(23, 4)	/* BAR size bitmask */
   1989 #define	PCI_RESIZBAR_CTL0	0x08	/* Control Register(0) */
   1990 #define	PCI_RESIZBAR_CTL(x)	(PCI_RESIZBAR_CTL0 + ((x) * 8))
   1991 #define	PCI_RESIZBAR_CTL_BARIDX __BITS(2, 0)
   1992 #define	PCI_RESIZBAR_CTL_NUMBAR	__BITS(7, 5)
   1993 #define	PCI_RESIZBAR_CTL_BARSIZ	__BITS(12, 8)
   1994 
   1995 /*
   1996  * Extended capability ID: 0x0016
   1997  * Dynamic Power Allocation
   1998  */
   1999 #define	PCI_DPA_CAP	0x04	/* Capability */
   2000 #define	PCI_DPA_CAP_SUBSTMAX	__BITS(4, 0)	/* Substate Max */
   2001 #define	PCI_DPA_CAP_TLUINT	__BITS(9, 8)	/* Transition Latency Unit */
   2002 #define	PCI_DPA_CAP_PAS		__BITS(13, 12)	/* Power Allocation Scale */
   2003 #define	PCI_DPA_CAP_XLCY0	__BITS(23, 16)	/* Transition Latency Value0 */
   2004 #define	PCI_DPA_CAP_XLCY1	__BITS(31, 24)	/* Transition Latency Value1 */
   2005 #define	PCI_DPA_LATIND	0x08	/* Latency Indicator */
   2006 #define	PCI_DPA_CS	0x0c	/* Control and Status */
   2007 #define	PCI_DPA_CS_SUBSTSTAT	__BITS(4, 0)	/* Substate Status */
   2008 #define	PCI_DPA_CS_SUBSTCTLEN	__BIT(8)	/* Substate Control Enabled */
   2009 #define	PCI_DPA_CS_SUBSTCTL	__BITS(20, 16)	/* Substate Control */
   2010 #define	PCI_DPA_PWRALLOC 0x10	/* Start address of Power Allocation Array */
   2011 #define	PCI_DPA_SUBST_MAXNUM	32	/* Max number of Substates (0 to 31) */
   2012 
   2013 /*
   2014  * Extended capability ID: 0x0017
   2015  * TPH Requester
   2016  */
   2017 #define	PCI_TPH_REQ_CAP	0x04	/* TPH Requester Capability */
   2018 #define	PCI_TPH_REQ_CAP_NOST	__BIT(0)	/* No ST Mode Supported */
   2019 #define	PCI_TPH_REQ_CAP_INTVEC	__BIT(1)	/* Intr Vec Mode Supported */
   2020 #define	PCI_TPH_REQ_CAP_DEVSPEC	__BIT(2)   /* Device Specific Mode Supported */
   2021 #define	PCI_TPH_REQ_CAP_XTPHREQ	__BIT(8)    /* Extend TPH Requester Supported */
   2022 #define	PCI_TPH_REQ_CAP_STTBLLOC __BITS(10, 9)	/* ST Table Location */
   2023 #define	PCI_TPH_REQ_STTBLLOC_NONE	0	 /* not present */
   2024 #define	PCI_TPH_REQ_STTBLLOC_TPHREQ	1	 /* in the TPHREQ cap */
   2025 #define	PCI_TPH_REQ_STTBLLOC_MSIX	2	 /* in the MSI-X table */
   2026 #define	PCI_TPH_REQ_CAP_STTBLSIZ __BITS(26, 16)	/* ST Table Size */
   2027 #define	PCI_TPH_REQ_CTL	0x08	/* TPH Requester Control */
   2028 #define	PCI_TPH_REQ_CTL_STSEL	__BITS(2, 0)	/* ST Mode Select */
   2029 #define	PCI_TPH_REQ_CTL_STSEL_NO	0	 /* No ST Mode */
   2030 #define	PCI_TPH_REQ_CTL_STSEL_IV	1	 /* Interrupt Vector Mode */
   2031 #define	PCI_TPH_REQ_CTL_STSEL_DS	2	 /* Device Specific Mode */
   2032 #define	PCI_TPH_REQ_CTL_TPHREQEN __BITS(9, 8)	/* TPH Requester Enable */
   2033 #define	PCI_TPH_REQ_CTL_TPHREQEN_NO	0	 /* Not permitted */
   2034 #define	PCI_TPH_REQ_CTL_TPHREQEN_TPH	1	 /* TPH and no extended TPH */
   2035 #define	PCI_TPH_REQ_CTL_TPHREQEN_RSVD	2	 /* Reserved */
   2036 #define	PCI_TPH_REQ_CTL_TPHREQEN_ETPH	3	 /* TPH and Extended TPH */
   2037 #define	PCI_TPH_REQ_STTBL 0x0c	/* TPH ST Table */
   2038 
   2039 /*
   2040  * Extended capability ID: 0x0018
   2041  * Latency Tolerance Reporting
   2042  */
   2043 #define	PCI_LTR_MAXSNOOPLAT	0x04	/* Max Snoop Latency */
   2044 #define	PCI_LTR_MAXSNOOPLAT_VAL	__BITS(9, 0)	/* Max Snoop LatencyValue */
   2045 #define	PCI_LTR_MAXSNOOPLAT_SCALE __BITS(12, 10) /* Max Snoop LatencyScale */
   2046 #define	PCI_LTR_MAXNOSNOOPLAT	0x04	/* Max No-Snoop Latency */
   2047 #define	PCI_LTR_MAXNOSNOOPLAT_VAL __BITS(25, 16) /* Max No-Snoop LatencyValue*/
   2048 #define	PCI_LTR_MAXNOSNOOPLAT_SCALE __BITS(28, 26) /*Max NoSnoop LatencyScale*/
   2049 #define	PCI_LTR_SCALETONS(x) (1 << ((x) * 5))
   2050 
   2051 /*
   2052  * Extended capability ID: 0x0019
   2053  * Seconday PCI Express Extended Capability
   2054  */
   2055 #define PCI_SECPCIE_LCTL3	0x04	/* Link Control 3 */
   2056 #define PCI_SECPCIE_LCTL3_PERFEQ	__BIT(0) /* Perform Equalization */
   2057 #define PCI_SECPCIE_LCTL3_LINKEQREQ_IE	__BIT(1) /* Link Eq. Req. Int. Ena. */
   2058 #define PCI_SECPCIE_LCTL3_ELSKPOSGENV	__BITS(15, 9) /* En. Lo. SKP OS Gen V*/
   2059 #define PCI_SECPCIE_LANEERR_STA 0x08	/* Lane Error Status */
   2060 #define PCI_SECPCIE_EQCTLS	0x0c	/* Equalization Control [0-maxlane] */
   2061 #define	PCI_SECPCIE_EQCTL(x)	(PCI_SECPCIE_EQCTLS + ((x) * 2))
   2062 #define	PCI_SECPCIE_EQCTL_DP_XMIT_PRESET __BITS(3, 0) /* DwnStPort Xmit Pres */
   2063 #define	PCI_SECPCIE_EQCTL_DP_RCV_HINT	__BITS(6, 4) /* DwnStPort Rcv PreHnt */
   2064 #define	PCI_SECPCIE_EQCTL_UP_XMIT_PRESET __BITS(11, 8) /* UpStPort Xmit Pres */
   2065 #define	PCI_SECPCIE_EQCTL_UP_RCV_HINT	__BITS(14, 12) /* UpStPort Rcv PreHnt*/
   2066 
   2067 /*
   2068  * Extended capability ID: 0x001a
   2069  * Protocol Multiplexing
   2070  */
   2071 
   2072 /*
   2073  * Extended capability ID: 0x001b
   2074  * Process Address Space ID
   2075  */
   2076 #define	PCI_PASID_CAP	0x04	/* Capability Register */
   2077 #define	PCI_PASID_CAP_XPERM	__BIT(1)     /* Execute Permission Supported */
   2078 #define	PCI_PASID_CAP_PRIVMODE	__BIT(2)	/* Privileged Mode Supported */
   2079 #define	PCI_PASID_CAP_MAXPASIDW	__BITS(12, 8)	/* Max PASID Width */
   2080 #define	PCI_PASID_CTL	0x04	/* Control Register */
   2081 #define	PCI_PASID_CTL_PASID_EN	__BIT(0+16)	/* PASID Enable */
   2082 #define	PCI_PASID_CTL_XPERM_EN	__BIT(1+16)	/* Execute Permission Enable */
   2083 #define	PCI_PASID_CTL_PRIVMODE_EN __BIT(2+16)	/* Privileged Mode Enable */
   2084 
   2085 /*
   2086  * Extended capability ID: 0x001c
   2087  * LN Requester
   2088  */
   2089 #define	PCI_LNR_CAP	0x04	/* Capability Register */
   2090 #define	PCI_LNR_CAP_64		__BIT(0)	/* LNR-64 Supported */
   2091 #define	PCI_LNR_CAP_128		__BIT(1)	/* LNR-128 Supported */
   2092 #define	PCI_LNR_CAP_REGISTMAX	__BITS(12, 8)	/* LNR Registration MAX */
   2093 #define	PCI_LNR_CTL	0x04	/* Control Register */
   2094 #define	PCI_LNR_CTL_EN		__BIT(0+16)	/* LNR Enable */
   2095 #define	PCI_LNR_CTL_CLS		__BIT(1+16)	/* LNR CLS */
   2096 #define	PCI_LNR_CTL_REGISTLIM	__BITS(28, 24)	/* LNR Registration Limit */
   2097 
   2098 /*
   2099  * Extended capability ID: 0x001d
   2100  * Downstream Port Containment
   2101  */
   2102 
   2103 #define	PCI_DPC_CCR	0x04	/* Capability and Control Register */
   2104 #define	PCI_DPCCAP_IMSGN	__BITS(4, 0)   /* Interrupt Message Number */
   2105 #define	PCI_DPCCAP_RPEXT	__BIT(5)       /* RP Extensions for DPC */
   2106 #define	PCI_DPCCAP_POISONTLPEB	__BIT(6)       /* Poisoned TLP Egress Blckng.*/
   2107 #define	PCI_DPCCAP_SWTRIG	__BIT(7)       /* DPC Software Triggering */
   2108 #define	PCI_DPCCAP_RPPIOLOGSZ	__BITS(11, 8)  /* RP PIO Log Size */
   2109 #define	PCI_DPCCAP_DLACTECORS	__BIT(12)      /* DL_Active ERR_COR Signaling*/
   2110 #define	PCI_DPCCTL_TIRGEN	__BITS(17, 16) /* DPC Trigger Enable */
   2111 #define	PCI_DPCCTL_COMPCTL	__BIT(18)      /* DPC Completion Control */
   2112 #define	PCI_DPCCTL_IE		__BIT(19)      /* DPC Interrupt Enable */
   2113 #define	PCI_DPCCTL_ERRCOREN	__BIT(20)      /* DPC ERR_COR enable */
   2114 #define	PCI_DPCCTL_POISONTLPEB	__BIT(21)      /* Poisoned TLP Egress Blckng.*/
   2115 #define	PCI_DPCCTL_SWTRIG	__BIT(22)      /* DPC Software Trigger */
   2116 #define	PCI_DPCCTL_DLACTECOR	__BIT(23)      /* DL_Active ERR_COR Enable */
   2117 
   2118 #define	PCI_DPC_STATESID 0x08	/* Status and Error Source ID Register */
   2119 #define	PCI_DPCSTAT_TSTAT	__BIT(0)       /* DPC Trigger Status */
   2120 #define	PCI_DPCSTAT_TREASON	__BITS(2, 1)   /* DPC Trigger Reason */
   2121 #define	PCI_DPCSTAT_ISTAT	__BIT(3)       /* DPC Interrupt Status */
   2122 #define	PCI_DPCSTAT_RPBUSY	__BIT(4)       /* DPC RP Busy */
   2123 #define	PCI_DPCSTAT_TRIGREXT	__BITS(6, 5)   /* DPC Trigger Reason Extntn. */
   2124 #define	PCI_DPCSTAT_RPPIOFEP	__BITS(12, 8)  /* RP PIO First Error Pointer */
   2125 #define	PCI_DPCESID		__BITS(31, 16) /* DPC Error Source ID */
   2126 
   2127 #define	PCI_DPC_RPPIO_STAT 0x0c	/* RP PIO Status Register */
   2128 #define	PCI_DPC_RPPIO_CFGUR_CPL	__BIT(0)       /* CfgReq received UR Complt. */
   2129 #define	PCI_DPC_RPPIO_CFGCA_CPL	__BIT(1)       /* CfgReq received CA Complt. */
   2130 #define	PCI_DPC_RPPIO_CFG_CTO	__BIT(2)       /* CfgReq Completion Timeout */
   2131 #define	PCI_DPC_RPPIO_IOUR_CPL	__BIT(8)       /* I/OReq received UR Complt. */
   2132 #define	PCI_DPC_RPPIO_IOCA_CPL	__BIT(9)       /* I/OReq received CA Complt. */
   2133 #define	PCI_DPC_RPPIO_IO_CTO	__BIT(10)      /* I/OReq Completion Timeout */
   2134 #define	PCI_DPC_RPPIO_MEMUR_CPL	__BIT(16)      /* MemReq received UR Complt. */
   2135 #define	PCI_DPC_RPPIO_MEMCA_CPL	__BIT(17)      /* MemReq received CA Complt. */
   2136 #define	PCI_DPC_RPPIO_MEM_CTO	__BIT(18)      /* MemReq Completion Timeout */
   2137 
   2138 #define	PCI_DPC_RPPIO_MASK 0x10	/* RP PIO Mask Register */
   2139   /* Bits are the same as RP PIO Status Register */
   2140 #define	PCI_DPC_RPPIO_SEVE 0x14	/* RP PIO Severity Register */
   2141   /* Same */
   2142 #define	PCI_DPC_RPPIO_SYSERR 0x18 /* RP PIO SysError Register */
   2143   /* Same */
   2144 #define	PCI_DPC_RPPIO_EXCPT 0x1c /* RP PIO Exception Register */
   2145   /* Same */
   2146 #define	PCI_DPC_RPPIO_HLOG 0x20	/* RP PIO Header Log Register */
   2147 #define	PCI_DPC_RPPIO_IMPSLOG 0x30 /* RP PIO ImpSpec Log Register */
   2148 #define	PCI_DPC_RPPIO_TLPPLOG 0x34 /* RP PIO TLP Prefix Log Register */
   2149 
   2150 /*
   2151  * Extended capability ID: 0x001e
   2152  * L1 PM Substates
   2153  */
   2154 #define	PCI_L1PM_CAP	0x04	/* Capabilities Register */
   2155 #define	PCI_L1PM_CAP_PCIPM12	__BIT(0)	/* PCI-PM L1.2 Supported */
   2156 #define	PCI_L1PM_CAP_PCIPM11	__BIT(1)	/* PCI-PM L1.1 Supported */
   2157 #define	PCI_L1PM_CAP_ASPM12	__BIT(2)	/* ASPM L1.2 Supported */
   2158 #define	PCI_L1PM_CAP_ASPM11	__BIT(3)	/* ASPM L1.1 Supported */
   2159 #define	PCI_L1PM_CAP_L1PM	__BIT(4)	/* L1 PM Substates Supported */
   2160 #define	PCI_L1PM_CAP_LA	__BIT(5)		/* Link Activation Supported */
   2161 #define	PCI_L1PM_CAP_PCMRT	__BITS(15, 8) /*Port Common Mode Restore Time*/
   2162 #define	PCI_L1PM_CAP_PTPOSCALE	__BITS(17, 16)	/* Port T_POWER_ON Scale */
   2163 #define	PCI_L1PM_CAP_PTPOVAL	__BITS(23, 19)	/* Port T_POWER_ON Value */
   2164 #define	PCI_L1PM_CTL1	0x08	/* Control Register 1 */
   2165 #define	PCI_L1PM_CTL1_PCIPM12_EN __BIT(0)	/* PCI-PM L1.2 Enable */
   2166 #define	PCI_L1PM_CTL1_PCIPM11_EN __BIT(1)	/* PCI-PM L1.1 Enable */
   2167 #define	PCI_L1PM_CTL1_ASPM12_EN	__BIT(2)	/* ASPM L1.2 Enable */
   2168 #define	PCI_L1PM_CTL1_ASPM11_EN	__BIT(3)	/* ASPM L1.1 Enable */
   2169 #define	PCI_L1PM_CTL1_LAIE	__BIT(4)	/* Link Activation Int. En. */
   2170 #define	PCI_L1PM_CTL1_LA	__BIT(5)	/* Link Activation Control */
   2171 #define	PCI_L1PM_CTL1_CMRT	__BITS(15, 8)	/* Common Mode Restore Time */
   2172 #define	PCI_L1PM_CTL1_LTRTHVAL	__BITS(25, 16)	/* LTR L1.2 THRESHOLD Value */
   2173 #define	PCI_L1PM_CTL1_LTRTHSCALE __BITS(31, 29)	/* LTR L1.2 THRESHOLD Scale */
   2174 #define	PCI_L1PM_CTL2	0x0c	/* Control Register 2 */
   2175 #define	PCI_L1PM_CTL2_TPOSCALE	__BITS(1, 0)	/* T_POWER_ON Scale */
   2176 #define	PCI_L1PM_CTL2_TPOVAL	__BITS(7, 3)	/* T_POWER_ON Value */
   2177 #define	PCI_L1PM_STAT	0x10	/* Status Register */
   2178 #define	PCI_L1PM_STAT_LA	__BIT(0)	/* Link Activation Status */
   2179 
   2180 /*
   2181  * Extended capability ID: 0x001f
   2182  * Precision Time Management
   2183  */
   2184 #define	PCI_PTM_CAP	0x04	/* Capabilities Register */
   2185 #define	PCI_PTM_CAP_REQ		__BIT(0)	/* PTM Requester Capable */
   2186 #define	PCI_PTM_CAP_RESP	__BIT(1)	/* PTM Responder Capable */
   2187 #define	PCI_PTM_CAP_ROOT	__BIT(2)	/* PTM Root Capable */
   2188 #define	PCI_PTM_CAP_LCLCLKGRNL	__BITS(15, 8)	/* Local Clock Granularity */
   2189 #define	PCI_PTM_CTL	0x08	/* Control Register */
   2190 #define	PCI_PTM_CTL_EN		__BIT(0)	/* PTM Enable */
   2191 #define	PCI_PTM_CTL_ROOTSEL	__BIT(1)	/* Root Select */
   2192 #define	PCI_PTM_CTL_EFCTGRNL	__BITS(15, 8)	/* Effective Granularity */
   2193 
   2194 /*
   2195  * Extended capability ID: 0x0020
   2196  * M-PCIe
   2197  */
   2198 
   2199 /*
   2200  * Extended capability ID: 0x0021
   2201  * Function Reading Status Queueing
   2202  */
   2203 
   2204 /*
   2205  * Extended capability ID: 0x0022
   2206  * Readiness Time Reporting
   2207  */
   2208 
   2209 /*
   2210  * Extended capability ID: 0x0023
   2211  * Designated Vendor-Specific
   2212  */
   2213 
   2214 /*
   2215  * Extended capability ID: 0x0024
   2216  * VF Resizable BAR
   2217  */
   2218 
   2219 /*
   2220  * Extended capability ID: 0x0025
   2221  * Data link Feature
   2222  */
   2223 #define	PCI_DLF_CAP	0x04	/* Capability register */
   2224 #define	PCI_DLF_LFEAT         __BITS(22, 0)  /* Local DLF supported */
   2225 #define	PCI_DLF_LFEAT_SCLFCTL __BIT(0)	     /* Scaled Flow Control */
   2226 #define	PCI_DLF_CAP_XCHG      __BIT(31)	     /* DLF Exchange enable */
   2227 #define	PCI_DLF_STAT	0x08	/* Status register */
   2228 	/* Bit 22:0 is the same as PCI_DLF_CAP_LINKFEAT */
   2229 #define	PCI_DLF_STAT_RMTVALID __BIT(31)	     /* Remote DLF supported Valid */
   2230 
   2231 /*
   2232  * Extended capability ID: 0x0026
   2233  * Physical Layer 16.0 GT/s
   2234  */
   2235 #define	PCI_PL16G_CAP	0x04	/* Capabilities Register */
   2236 #define	PCI_PL16G_CTL	0x08	/* Control Register */
   2237 #define	PCI_PL16G_STAT	0x0c	/* Status Register */
   2238 #define	PCI_PL16G_STAT_EQ_COMPL __BIT(0) /* Equalization 16.0 GT/s Complete */
   2239 #define	PCI_PL16G_STAT_EQ_P1S	__BIT(1) /* Eq. 16.0 GT/s Phase 1 Successful */
   2240 #define	PCI_PL16G_STAT_EQ_P2S	__BIT(2) /* Eq. 16.0 GT/s Phase 2 Successful */
   2241 #define	PCI_PL16G_STAT_EQ_P3S	__BIT(3) /* Eq. 16.0 GT/s Phase 3 Successful */
   2242 #define	PCI_PL16G_STAT_LEQR	__BIT(4) /* Link Eq. Request 16.0 GT/s */
   2243 #define	PCI_PL16G_LDPMS	0x10	/* Local Data Parity Mismatch Status reg. */
   2244 #define	PCI_PL16G_FRDPMS 0x14	/* First Retimer Data Parity Mismatch Status */
   2245 #define	PCI_PL16G_SRDPMS 0x18  /* Second Retimer Data Parity Mismatch Status */
   2246   /* 0x1c reserved */
   2247 #define	PCI_PL16G_LEC	0x20	/* Lane Equalization Control Register */
   2248 
   2249 /*
   2250  * Extended capability ID: 0x0027
   2251  * Lane Margining at the Receiver
   2252  */
   2253 #define	PCI_LMR_PCAPSTAT 0x04	/* Port Capabilities and Status Register */
   2254 #define	PCI_LMR_PCAP_MUDS	__BIT(0)   /* Margining uses Driver Software */
   2255 #define	PCI_LMR_PSTAT_MR	__BIT(16)  /* Margining Ready */
   2256 #define	PCI_LMR_PSTAT_MSR	__BIT(17)  /* Margining Software Ready */
   2257 #define	PCI_LMR_LANECSR	0x08	/* Lane Control and Status Register */
   2258 #define	PCI_LMR_LCTL_RNUM	__BITS(2, 0)	/* Receive Number */
   2259 #define	PCI_LMR_LCTL_MTYPE	__BITS(5, 3)	/* Margin Type */
   2260 #define	PCI_LMR_LCTL_UMODEL	__BIT(6)	/* Usage Model */
   2261 #define	PCI_LMR_LCTL_MPAYLOAD	__BITS(15, 8)	/* Margin Payload */
   2262 #define	PCI_LMR_LSTAT_RNUM	__BITS(18, 16)	/* Receive Number */
   2263 #define	PCI_LMR_LSTAT_MTYPE	__BITS(21, 19)	/* Margin Type */
   2264 #define	PCI_LMR_LSTAT_UMODEL	__BIT(22)	/* Usage Model */
   2265 #define	PCI_LMR_LSTAT_MPAYLOAD	__BITS(31, 24)	/* Margin Payload */
   2266 
   2267 /*
   2268  * Extended capability ID: 0x0028
   2269  * Hierarchy ID
   2270  */
   2271 
   2272 /*
   2273  * Extended capability ID: 0x0029
   2274  * Native PCIe Enclosure Management
   2275  */
   2276 
   2277 #endif /* _DEV_PCI_PCIREG_H_ */
   2278