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    Searched defs:PCLK (Results 1 - 24 of 24) sorted by relevancy

  /src/sys/arch/sun2/dev/
zsreg.h 35 #define PCLK (9600 * 512) /* PCLK pin input clock rate */
  /src/sys/arch/ews4800mips/sbd/
zs_sbdio.c 58 #define PCLK (9600 * 512) /* 4.915200MHz */
87 BPS_TO_TCONST((PCLK/16), ZS_DEFSPEED), /* 12: BAUDLO (default=9600) */
156 cs->cs_brg_clk = PCLK / 16;
250 cs->cs_brg_clk = PCLK / 16;
  /src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
s3c2410.h 28 #define PCLK 6
32 /* pclk-gates */
s3c2412.h 30 #define PCLK 8
42 /* pclk-gates */
s3c2443.h 27 #define PCLK 6
69 /* pclk-gates */
samsung,s3c64xx-clock.h 30 #define PCLK 9
64 /* PCLK bus clocks. */
  /src/sys/arch/next68k/dev/
zs_kgdb.c 67 #define PCLK (9600 * 384) /* PCLK pin input clock rate */
93 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */
157 cs.cs_brg_clk = PCLK / 16;
zs.c 96 #define PCLK (9600 * 384) /* PCLK pin input clock rate */
130 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */
224 cs->cs_brg_clk = PCLK / 16;
622 cs->cs_brg_clk = PCLK / 16;
  /src/sys/arch/mac68k/dev/
zs_kgdb.c 66 #define PCLK (9600 * 384) /* PCLK pin input clock rate */
167 cs.cs_brg_clk = PCLK / 16;
zs.c 85 #define PCLK (9600 * 384)
164 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */
276 cs->cs_brg_clk = PCLK / 16; /* RTxC is 230400*16, so use 230400 */
291 xcs->cs_clocks[0].clk = PCLK;
478 tc = BPS_TO_TCONST(PCLK / 16, bps);
481 rate = TCONST_TO_BPS(PCLK / 16, tc);
593 cs->cs_brg_clk = PCLK / 16;
828 cs->cs_brg_clk = PCLK / 16;
  /src/sys/arch/sun3/dev/
zs_kgdb.c 63 #define PCLK (9600 * 512) /* PCLK pin input clock rate */
158 cs.cs_brg_clk = PCLK / 16;
zs.c 97 #define PCLK (9600 * 512) /* PCLK pin input clock rate */
153 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */
286 cs->cs_brg_clk = PCLK / 16;
  /src/sys/arch/macppc/include/
z8530var.h 95 (RTxC divided, RTxC BRG, PCLK BRG, TRxC divided)
179 #define PCLK (9600 * 384) /* PCLK pin input clock rate */
  /src/sys/arch/cobalt/dev/
zs.c 72 #define PCLK (115200 * 96) /* 11.0592MHz */
122 BPS_TO_TCONST((PCLK/16), ZS_DEFSPEED), /*12: BAUDLO */
202 cs->cs_brg_clk = PCLK / 16;
527 cs->cs_preg[12] = BPS_TO_TCONST(PCLK / 16, ZS_DEFSPEED);
  /src/sys/arch/x68k/dev/
zs.c 87 #define PCLK (5 * 1000 * 1000) /* PCLK pin input clock rate */
113 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */
210 cs->cs_brg_clk = PCLK / 16;
378 * Since our PCLK has somewhat strange value,
584 zscn_cs.cs_brg_clk = PCLK / 16;
  /src/sys/dev/tc/
zs_ioasic.c 112 #define PCLK (9600 * 768) /* PCLK pin input clock rate */
268 cs->cs_brg_clk = PCLK / 16;
735 cs->cs_brg_clk = PCLK / 16;
  /src/sys/arch/sparc/dev/
zs_kgdb.c 65 #define PCLK (9600 * 512) /* PCLK pin input clock rate */
165 cs.cs_brg_clk = PCLK / 16;
zs.c 89 #define PCLK (9600 * 512) /* PCLK pin input clock rate */
122 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */
430 cs->cs_brg_clk = PCLK / 16;
  /src/sys/arch/newsmips/dev/
zs_hb.c 75 #define PCLK (9600 * 512) /* PCLK pin input clock rate */
119 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */
235 cs->cs_brg_clk = PCLK / 16;
  /src/sys/arch/mipsco/obio/
zs.c 85 #define PCLK 10000000 /* PCLK pin input clock rate */
96 /* Register recovery time is 3.5 to 4 PCLK Cycles */
97 #define ZS_RECOVERY 1 /* 1us = 10 PCLK Cycles */
142 BPS_TO_TCONST(PCLK/16, ZS_DEFSPEED), /*12: BAUDLO (default=9600) */
232 cs->cs_brg_clk = PCLK / 16;
  /src/sys/arch/sgimips/dev/
zs.c 81 #define PCLK 3672000 /* PCLK pin input clock rate */
162 BPS_TO_TCONST(PCLK/16, ZS_DEFSPEED), /*12: BAUDLO (default=9600) */
254 cs->cs_brg_clk = PCLK / 16;
  /src/sys/arch/sparc64/dev/
zs.c 98 #define PCLK (9600 * 512) /* PCLK pin input clock rate */
134 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */
361 cs->cs_brg_clk = PCLK / 16;
  /src/sys/arch/newsmips/apbus/
zs_ap.c 127 #define PCLK (9600 * 1024) /* PCLK pin input clock rate */
162 BPS_TO_TCONST(PCLK/16,9600), /*12: BAUDLO (default=9600) */
346 cs->cs_brg_clk = PCLK / 16;
562 cs->cs_brg_clk = PCLK / 16;
  /src/sys/arch/atari/dev/
zs.c 116 #define PCLK (8053976) /* PCLK pin input clock rate */
117 #define PCLK_HD (9600 * 1536) /* PCLK on Hades pin input clock rate */
166 PCLK/16, /* BRgen, PCLK, divisor 16 */
171 PCLK/16, /* BRgen, PCLK, divisor 16 */
181 PCLK/16, /* BRgen, PCLK, divisor 16 */
186 PCLK/16, /* BRgen, PCLK, divisor 16 *
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