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      1 /*	$NetBSD: s3c2412.h,v 1.1.1.2 2019/01/22 14:57:01 jmcneill Exp $	*/
      2 
      3 /* SPDX-License-Identifier: GPL-2.0 */
      4 /*
      5  * Copyright (c) 2013 Heiko Stuebner <heiko (at) sntech.de>
      6  *
      7  * Device Tree binding constants clock controllers of Samsung S3C2412.
      8  */
      9 
     10 #ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C2412_CLOCK_H
     11 #define _DT_BINDINGS_CLOCK_SAMSUNG_S3C2412_CLOCK_H
     12 
     13 /*
     14  * Let each exported clock get a unique index, which is used on DT-enabled
     15  * platforms to lookup the clock from a clock specifier. These indices are
     16  * therefore considered an ABI and so must not be changed. This implies
     17  * that new clocks should be added either in free spaces between clock groups
     18  * or at the end.
     19  */
     20 
     21 /* Core clocks. */
     22 
     23 /* id 1 is reserved */
     24 #define MPLL			2
     25 #define UPLL			3
     26 #define MDIVCLK			4
     27 #define MSYSCLK			5
     28 #define USYSCLK			6
     29 #define HCLK			7
     30 #define PCLK			8
     31 #define ARMDIV			9
     32 #define ARMCLK			10
     33 
     34 
     35 /* Special clocks */
     36 #define SCLK_CAM		16
     37 #define SCLK_UART		17
     38 #define SCLK_I2S		18
     39 #define SCLK_USBD		19
     40 #define SCLK_USBH		20
     41 
     42 /* pclk-gates */
     43 #define PCLK_WDT		32
     44 #define PCLK_SPI		33
     45 #define PCLK_I2S		34
     46 #define PCLK_I2C		35
     47 #define PCLK_ADC		36
     48 #define PCLK_RTC		37
     49 #define PCLK_GPIO		38
     50 #define PCLK_UART2		39
     51 #define PCLK_UART1		40
     52 #define PCLK_UART0		41
     53 #define PCLK_SDI		42
     54 #define PCLK_PWM		43
     55 #define PCLK_USBD		44
     56 
     57 /* hclk-gates */
     58 #define HCLK_HALF		48
     59 #define HCLK_X2			49
     60 #define HCLK_SDRAM		50
     61 #define HCLK_USBH		51
     62 #define HCLK_LCD		52
     63 #define HCLK_NAND		53
     64 #define HCLK_DMA3		54
     65 #define HCLK_DMA2		55
     66 #define HCLK_DMA1		56
     67 #define HCLK_DMA0		57
     68 
     69 /* Total number of clocks. */
     70 #define NR_CLKS			(HCLK_DMA0 + 1)
     71 
     72 #endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C2412_CLOCK_H */
     73