Home | History | Annotate | Line # | Download | only in mainbus
      1 /*	$NetBSD: piocreg.h,v 1.1 2001/10/05 22:27:53 reinoud Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 1997 Mark Brinicombe.
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  * 3. All advertising materials mentioning features or use of this software
     16  *    must display the following acknowledgement:
     17  *	This product includes software developed by Mark Brinicombe.
     18  * 4. The name of the company nor the name of the author may be used to
     19  *    endorse or promote products derived from this software without specific
     20  *    prior written permission.
     21  *
     22  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
     23  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
     24  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     25  * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
     26  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
     27  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
     28  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     29  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     30  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     31  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     32  * SUCH DAMAGE.
     33  *
     34  * Peripheral I/O controller registers
     35  */
     36 
     37 /*
     38  *
     39  */
     40 
     41 #define PIOC_SIZE		(0x1000 + 0x2000)	/* XXX */
     42 
     43 /*
     44  * I/O registers for managing PIOC configuration
     45  */
     46 
     47 #define PIOC_CM_SELECT_REG	0x3f0
     48 #define PIOC_CM_DATA_REG	0x3f1
     49 
     50 /*
     51  * Bytes to write to the select register to switch in and out for config mode
     52  */
     53 
     54 #define PIOC_CM_ENTER_665	0x55	/* SMC FDC37GT665 */
     55 #define PIOC_CM_ENTER_666	0x44	/* SMC FDC37GT666 */
     56 #define PIOC_CM_EXIT		0xaa
     57 
     58 /*
     59  * Configuration register selection codes
     60  */
     61 
     62 #define PIOC_CM_CR0		0x0	/* IDE and floppy setup */
     63 #define  PIOC_WDC_ENABLE	0x01	/* wdc enable */
     64 #define  PIOC_FDC_ENABLE	0x10	/* fdc enable */
     65 #define PIOC_CM_CR1		0x1	/* parallel and serial setup */
     66 #define  PIOC_LPT_ADDR_MASK	0x03	/* lpt address mask */
     67 #define  PIOC_LPT_ADDR_DISABLE	0x00	/* lpt disabled */
     68 #define  PIOC_LPT_ADDR_1	0x01	/* lpt address 1 */
     69 #define  PIOC_LPT_ADDR_2	0x02	/* lpt address 2 */
     70 #define  PIOC_LPT_ADDR_3	0x03	/* lpt address 3 */
     71 #define PIOC_CM_CR2		0x2	/* serial setup */
     72 #define  PIOC_UART1_ADDR_MASK	0x03	/* uart1 address mask */
     73 #define  PIOC_UART1_ADDR_COM1	0x00	/* uart1 address com1 */
     74 #define  PIOC_UART1_ADDR_COM2	0x01	/* uart1 address com2 */
     75 #define  PIOC_UART1_ADDR_COM3	0x02	/* uart1 address com3 */
     76 #define  PIOC_UART1_ADDR_COM4	0x03	/* uart1 address com4 */
     77 #define  PIOC_UART1_ENABLE	0x04	/* uart1 enable */
     78 #define  PIOC_UART2_ADDR_MASK	0x30	/* uart2 address mask */
     79 #define  PIOC_UART2_ADDR_COM1	0x00	/* uart2 address com1 */
     80 #define  PIOC_UART2_ADDR_COM2	0x10	/* uart2 address com2 */
     81 #define  PIOC_UART2_ADDR_COM3	0x20	/* uart2 address com3 */
     82 #define  PIOC_UART2_ADDR_COM4	0x30	/* uart2 address com4 */
     83 #define  PIOC_UART2_ENABLE	0x40	/* uart2 enable */
     84 #define PIOC_CM_CR3		0x3	/* parallel setup */
     85 #define PIOC_CM_CR4		0x4	/* parallel and serial extended setup */
     86 #define PIOC_CM_CR5		0x5	/* floppy & IDE extended setup */
     87 #define  PIOC_FDC_SECONDARY	0x01	/* fdc secondary address enable */
     88 #define  PIOC_WDC_SECONDARY	0x02	/* wdc secondary address enable */
     89 #define PIOC_CM_CR6		0x6	/* floppy drive types */
     90 #define PIOC_CM_CR7		0x7	/* media ID & boot drive */
     91 #define PIOC_CM_CR8		0x8	/* PIOC address low */
     92 #define PIOC_CM_CR9		0x9	/* PIOC address high */
     93 #define PIOC_CM_CRA		0xa	/* ECP FIFO threshold */
     94 #define PIOC_CM_CRB		0xb	/* reserved */
     95 #define PIOC_CM_CRC		0xc	/* reserved */
     96 #define PIOC_CM_CRD		0xd	/* PIOC ID */
     97 #define PIOC_CM_CRE		0xe	/* PIOC revision */
     98 #define PIOC_CM_CRF		0xf	/* reserve for testing */
     99 #define PIOC_CM_REGS		0x10	/* number of registers */
    100 
    101 /*
    102  * PIOC ID values
    103  */
    104 
    105 #define PIOC_CM_ID_665		0x65
    106 #define PIOC_CM_ID_666		0x66
    107 
    108 /*
    109  * PIOC offsets
    110  */
    111 
    112 #define PIOC_FDC_PRIMARY_OFFSET		0x3f0
    113 #define PIOC_FDC_SECONDARY_OFFSET	0x370
    114 #define PIOC_WDC_PRIMARY_OFFSET		0x1f0
    115 #define PIOC_WDC_SECONDARY_OFFSET	0x170
    116 #define PIOC_LPT1_OFFSET		0x3bc
    117 #define PIOC_LPT2_OFFSET		0x378
    118 #define PIOC_LPT3_OFFSET		0x278
    119 #define PIOC_COM1_OFFSET		0x3f8
    120 #define PIOC_COM2_OFFSET		0x2f8
    121 #define PIOC_COM3_OFFSET		0x338
    122 #define PIOC_COM4_OFFSET		0x238
    123 
    124 /* End of piocreg.h */
    125