1 /* $NetBSD: pmap.h,v 1.62 2026/05/21 10:07:02 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _AARCH64_PMAP_H_ 33 #define _AARCH64_PMAP_H_ 34 35 #ifdef __aarch64__ 36 37 #ifdef _KERNEL 38 #ifdef _KERNEL_OPT 39 #include "opt_kasan.h" 40 #include "opt_pmap.h" 41 #endif 42 43 #include <sys/types.h> 44 #include <sys/pool.h> 45 #include <sys/queue.h> 46 47 #include <uvm/uvm_pglist.h> 48 49 #include <arm/cpufunc.h> 50 51 #include <aarch64/armreg.h> 52 #include <aarch64/cpufunc.h> 53 #include <aarch64/pte.h> 54 55 #define PMAP_TLB_MAX 1 56 #if PMAP_TLB_MAX > 1 57 #define PMAP_TLB_NEED_SHOOTDOWN 1 58 #endif 59 60 #define PMAP_TLB_FLUSH_ASID_ON_RESET true 61 62 /* Maximum number of ASIDs. Some CPUs have less.*/ 63 #define PMAP_TLB_NUM_PIDS 65536 64 #define PMAP_TLB_BITMAP_LENGTH PMAP_TLB_NUM_PIDS 65 66 static inline tlb_asid_t 67 pmap_md_tlb_asid_max(void) 68 { 69 switch (__SHIFTOUT(reg_id_aa64mmfr0_el1_read(), ID_AA64MMFR0_EL1_ASIDBITS)) { 70 case ID_AA64MMFR0_EL1_ASIDBITS_8BIT: 71 return (1U << 8) - 1; 72 case ID_AA64MMFR0_EL1_ASIDBITS_16BIT: 73 return (1U << 16) - 1; 74 default: 75 return 0; 76 } 77 } 78 79 #include <uvm/pmap/tlb.h> 80 #include <uvm/pmap/pmap_devmap.h> 81 #include <uvm/pmap/pmap_tlb.h> 82 83 #define KERNEL_PID 0 /* The kernel uses ASID 0 */ 84 85 86 /* memory attributes are configured MAIR_EL1 in locore */ 87 #define LX_BLKPAG_ATTR_NORMAL_WB __SHIFTIN(0, LX_BLKPAG_ATTR_INDX) 88 #define LX_BLKPAG_ATTR_NORMAL_NC __SHIFTIN(1, LX_BLKPAG_ATTR_INDX) 89 #define LX_BLKPAG_ATTR_NORMAL_WT __SHIFTIN(2, LX_BLKPAG_ATTR_INDX) 90 #define LX_BLKPAG_ATTR_DEVICE_MEM __SHIFTIN(3, LX_BLKPAG_ATTR_INDX) 91 #define LX_BLKPAG_ATTR_DEVICE_MEM_NP __SHIFTIN(4, LX_BLKPAG_ATTR_INDX) 92 #define LX_BLKPAG_ATTR_MASK LX_BLKPAG_ATTR_INDX 93 94 #define lxpde_pa(pde) ((paddr_t)((pde) & LX_TBL_PA)) 95 #define lxpde_valid(pde) (((pde) & LX_VALID) == LX_VALID) 96 #define l0pde_pa(pde) lxpde_pa(pde) 97 #define l0pde_index(v) (((vaddr_t)(v) & L0_ADDR_BITS) >> L0_SHIFT) 98 #define l0pde_valid(pde) lxpde_valid(pde) 99 /* l0pte always contains table entries */ 100 101 #define l1pde_pa(pde) lxpde_pa(pde) 102 #define l1pde_index(v) (((vaddr_t)(v) & L1_ADDR_BITS) >> L1_SHIFT) 103 #define l1pde_valid(pde) lxpde_valid(pde) 104 #define l1pde_is_block(pde) (((pde) & LX_TYPE) == LX_TYPE_BLK) 105 #define l1pde_is_table(pde) (((pde) & LX_TYPE) == LX_TYPE_TBL) 106 107 #define l2pde_pa(pde) lxpde_pa(pde) 108 #define l2pde_index(v) (((vaddr_t)(v) & L2_ADDR_BITS) >> L2_SHIFT) 109 #define l2pde_valid(pde) lxpde_valid(pde) 110 #define l2pde_is_block(pde) (((pde) & LX_TYPE) == LX_TYPE_BLK) 111 #define l2pde_is_table(pde) (((pde) & LX_TYPE) == LX_TYPE_TBL) 112 113 #define l3pte_pa(pde) lxpde_pa(pde) 114 #define l3pte_executable(pde,user) \ 115 (((pde) & ((user) ? LX_BLKPAG_UXN : LX_BLKPAG_PXN)) == 0) 116 #define l3pte_readable(pde) ((pde) & LX_BLKPAG_AF) 117 #define l3pte_writable(pde) \ 118 (((pde) & (LX_BLKPAG_AF | LX_BLKPAG_AP)) == (LX_BLKPAG_AF | LX_BLKPAG_AP_RW)) 119 #define l3pte_index(v) (((vaddr_t)(v) & L3_ADDR_BITS) >> L3_SHIFT) 120 #define l3pte_valid(pde) lxpde_valid(pde) 121 #define l3pte_is_page(pde) (((pde) & LX_TYPE) == L3_TYPE_PAG) 122 123 pd_entry_t *pmap_l0table(struct pmap *); 124 void pmap_bootstrap(vaddr_t, vaddr_t); 125 bool pmap_fault_fixup(struct pmap *, vaddr_t, vm_prot_t, bool user); 126 127 bool pmap_extract_coherency(pmap_t, vaddr_t, paddr_t *, bool *); 128 129 130 /* change attribute of kernel segment */ 131 static inline pt_entry_t 132 pmap_kvattr(pt_entry_t *ptep, vm_prot_t prot) 133 { 134 pt_entry_t pte = *ptep; 135 const pt_entry_t opte = pte; 136 137 pte &= ~(LX_BLKPAG_AF | LX_BLKPAG_AP); 138 switch (prot & (VM_PROT_READ | VM_PROT_WRITE)) { 139 case 0: 140 break; 141 case VM_PROT_READ: 142 pte |= LX_BLKPAG_AF | LX_BLKPAG_AP_RO; 143 break; 144 case VM_PROT_WRITE: 145 case VM_PROT_READ | VM_PROT_WRITE: 146 pte |= LX_BLKPAG_AF | LX_BLKPAG_AP_RW; 147 break; 148 } 149 150 if ((prot & VM_PROT_EXECUTE) == 0) { 151 pte |= LX_BLKPAG_PXN; 152 } else { 153 pte |= LX_BLKPAG_AF; 154 pte &= ~LX_BLKPAG_PXN; 155 } 156 157 *ptep = pte; 158 159 return opte; 160 } 161 162 #define L1_TRUNC_BLOCK(x) ((x) & L1_FRAME) 163 #define L1_ROUND_BLOCK(x) L1_TRUNC_BLOCK((x) + L1_SIZE - 1) 164 #define L2_TRUNC_BLOCK(x) ((x) & L2_FRAME) 165 #define L2_ROUND_BLOCK(x) L2_TRUNC_BLOCK((x) + L2_SIZE - 1) 166 #define L3_TRUNC_BLOCK(x) ((x) & L3_FRAME) 167 #define L3_ROUND_BLOCK(x) L3_TRUNC_BLOCK((x) + L3_SIZE - 1) 168 169 #define DEVMAP_ALIGN(x) L3_TRUNC_BLOCK((x)) 170 #define DEVMAP_SIZE(x) L3_ROUND_BLOCK((x)) 171 #define DEVMAP_FLAGS PMAP_DEV 172 173 /* Hooks for the pool allocator */ 174 paddr_t vtophys(vaddr_t); 175 176 /* mmap cookie and flags */ 177 #define AARCH64_MMAP_FLAG_SHIFT (64 - PGSHIFT) 178 #define AARCH64_MMAP_FLAG_MASK 0xf 179 #define AARCH64_MMAP_WRITEBACK 0UL 180 #define AARCH64_MMAP_NOCACHE 1UL 181 #define AARCH64_MMAP_WRITECOMBINE 2UL 182 #define AARCH64_MMAP_DEVICE 3UL 183 184 #define ARM_MMAP_MASK __BITS(63, AARCH64_MMAP_FLAG_SHIFT) 185 #define ARM_MMAP_WRITECOMBINE __SHIFTIN(AARCH64_MMAP_WRITECOMBINE, ARM_MMAP_MASK) 186 #define ARM_MMAP_WRITEBACK __SHIFTIN(AARCH64_MMAP_WRITEBACK, ARM_MMAP_MASK) 187 #define ARM_MMAP_NOCACHE __SHIFTIN(AARCH64_MMAP_NOCACHE, ARM_MMAP_MASK) 188 #define ARM_MMAP_DEVICE __SHIFTIN(AARCH64_MMAP_DEVICE, ARM_MMAP_MASK) 189 190 #define PMAP_PTE 0x10000000 /* kenter_pa */ 191 #define PMAP_DEV 0x20000000 /* kenter_pa */ 192 #define PMAP_DEV_NP 0x40000000 /* kenter_pa */ 193 #define PMAP_DEV_MASK (PMAP_DEV | PMAP_DEV_NP) 194 195 static inline u_int 196 aarch64_mmap_flags(paddr_t mdpgno) 197 { 198 u_int nflag, pflag; 199 200 /* 201 * aarch64 arch has 5 memory attributes defined: 202 * 203 * WriteBack - write back cache 204 * WriteThru - write through cache 205 * NoCache - no cache 206 * Device(nGnRE) - no Gathering, no Reordering, Early write ack 207 * Device(nGnRnE) - no Gathering, no Reordering, no Early write ack 208 * 209 * but pmap has PMAP_{NOCACHE,WRITE_COMBINE,WRITE_BACK} flags. 210 */ 211 212 nflag = (mdpgno >> AARCH64_MMAP_FLAG_SHIFT) & AARCH64_MMAP_FLAG_MASK; 213 switch (nflag) { 214 case AARCH64_MMAP_DEVICE: 215 pflag = PMAP_DEV; 216 break; 217 case AARCH64_MMAP_WRITECOMBINE: 218 pflag = PMAP_WRITE_COMBINE; 219 break; 220 case AARCH64_MMAP_WRITEBACK: 221 pflag = PMAP_WRITE_BACK; 222 break; 223 case AARCH64_MMAP_NOCACHE: 224 default: 225 pflag = PMAP_NOCACHE; 226 break; 227 } 228 return pflag; 229 } 230 231 #define pmap_phys_address(pa) aarch64_ptob((pa)) 232 #define pmap_mmap_flags(ppn) aarch64_mmap_flags((ppn)) 233 234 void pmap_bootstrap(vaddr_t, vaddr_t); 235 bool pmap_fault_fixup(struct pmap *, vaddr_t, vm_prot_t, bool user); 236 237 pd_entry_t *pmapboot_pagealloc(void); 238 void pmapboot_enter(vaddr_t, paddr_t, psize_t, psize_t, pt_entry_t, 239 void (*pr)(const char *, ...) __printflike(1, 2)); 240 void pmapboot_enter_range(vaddr_t, paddr_t, psize_t, pt_entry_t, 241 void (*)(const char *, ...) __printflike(1, 2)); 242 int pmapboot_protect(vaddr_t, vaddr_t, vm_prot_t); 243 244 vsize_t pmap_map_chunk(vaddr_t, vaddr_t, paddr_t, vsize_t, vm_prot_t, u_int); 245 246 #if defined(DDB) 247 void pmap_db_pte_print(pt_entry_t, int, void (*)(const char *, ...) __printflike(1, 2)); 248 void pmap_db_pteinfo(vaddr_t, void (*)(const char *, ...) __printflike(1, 2)); 249 void pmap_db_ttbrdump(bool, vaddr_t, void (*)(const char *, ...) __printflike(1, 2)); 250 #endif 251 252 #define LX_BLKPAG_OS_WIRED LX_BLKPAG_OS_2 253 #define LX_BLKPAG_OS_BOOT LX_BLKPAG_OS_3 254 255 #define PMAP_PTE_OS2 "wired" 256 #define PMAP_PTE_OS3 "boot" 257 258 #if defined(PMAP_MI) 259 #include <aarch64/pmap_machdep.h> 260 #else 261 262 #define PMAP_NEED_PROCWR 263 #define PMAP_GROWKERNEL 264 #define PMAP_STEAL_MEMORY 265 266 #define __HAVE_VM_PAGE_MD 267 #define __HAVE_PMAP_PV_TRACK 1 268 269 struct pmap { 270 kmutex_t pm_lock; 271 struct pool *pm_pvpool; 272 pd_entry_t *pm_l0table; /* L0 table: 512G*512 */ 273 paddr_t pm_l0table_pa; 274 275 LIST_HEAD(, vm_page) pm_vmlist; /* for L[0123] tables */ 276 LIST_HEAD(, pv_entry) pm_pvlist; /* all pv of this process */ 277 278 struct pmap_statistics pm_stats; 279 unsigned int pm_refcnt; 280 unsigned int pm_idlepdp; 281 282 kcpuset_t *pm_onproc; 283 kcpuset_t *pm_active; 284 285 struct pmap_asid_info pm_pai[PMAP_TLB_MAX]; 286 bool pm_activated; 287 }; 288 289 static inline paddr_t 290 pmap_l0pa(struct pmap *pm) 291 { 292 return pm->pm_l0table_pa; 293 } 294 295 296 /* 297 * should be kept <=32 bytes sized to reduce memory consumption & cache misses, 298 * but it doesn't... 299 */ 300 struct pv_entry { 301 struct pv_entry *pv_next; 302 struct pmap *pv_pmap; 303 vaddr_t pv_va; /* for embedded entry (pp_pv) also includes flags */ 304 void *pv_ptep; /* pointer for fast pte lookup */ 305 LIST_ENTRY(pv_entry) pv_proc; /* belonging to the process */ 306 }; 307 308 struct pmap_page { 309 kmutex_t pp_pvlock; 310 struct pv_entry pp_pv; 311 }; 312 313 /* try to keep vm_page at or under 128 bytes to reduce cache misses */ 314 struct vm_page_md { 315 struct pmap_page mdpg_pp; 316 }; 317 /* for page descriptor page only */ 318 #define mdpg_ptep_parent mdpg_pp.pp_pv.pv_ptep 319 320 #define VM_MDPAGE_INIT(pg) \ 321 do { \ 322 PMAP_PAGE_INIT(&(pg)->mdpage.mdpg_pp); \ 323 } while (/*CONSTCOND*/ 0) 324 325 #define PMAP_PAGE_INIT(pp) \ 326 do { \ 327 mutex_init(&(pp)->pp_pvlock, MUTEX_NODEBUG, IPL_NONE); \ 328 (pp)->pp_pv.pv_next = NULL; \ 329 (pp)->pp_pv.pv_pmap = NULL; \ 330 (pp)->pp_pv.pv_va = 0; \ 331 (pp)->pp_pv.pv_ptep = NULL; \ 332 } while (/*CONSTCOND*/ 0) 333 334 /* saved permission bit for referenced/modified emulation */ 335 #define LX_BLKPAG_OS_READ LX_BLKPAG_OS_0 336 #define LX_BLKPAG_OS_WRITE LX_BLKPAG_OS_1 337 #define LX_BLKPAG_OS_RWMASK (LX_BLKPAG_OS_WRITE | LX_BLKPAG_OS_READ) 338 339 #define PMAP_PTE_OS0 "read" 340 #define PMAP_PTE_OS1 "write" 341 342 #define VTOPHYS_FAILED ((paddr_t)-1L) /* POOL_PADDR_INVALID */ 343 #define POOL_VTOPHYS(va) vtophys((vaddr_t) (va)) 344 345 #ifndef KASAN 346 #define PMAP_MAP_POOLPAGE(pa) AARCH64_PA_TO_KVA(pa) 347 #define PMAP_UNMAP_POOLPAGE(va) AARCH64_KVA_TO_PA(va) 348 349 #define PMAP_DIRECT 350 static __inline int 351 pmap_direct_process(paddr_t pa, voff_t pgoff, size_t len, 352 int (*process)(void *, size_t, void *), void *arg) 353 { 354 vaddr_t va = AARCH64_PA_TO_KVA(pa); 355 356 return process((void *)(va + pgoff), len, arg); 357 } 358 #endif 359 360 /* l3pte contains always page entries */ 361 static inline uint64_t 362 pte_value(pt_entry_t pte) 363 { 364 return pte; 365 } 366 367 static inline bool 368 pte_valid_p(pt_entry_t pte) 369 { 370 return l3pte_valid(pte); 371 } 372 373 pt_entry_t *kvtopte(vaddr_t); 374 375 #define pmap_update(pmap) ((void)0) 376 #define pmap_copy(dp,sp,d,l,s) ((void)0) 377 #define pmap_wired_count(pmap) ((pmap)->pm_stats.wired_count) 378 #define pmap_resident_count(pmap) ((pmap)->pm_stats.resident_count) 379 380 struct pmap * 381 pmap_efirt(void); 382 void pmap_activate_efirt(void); 383 void pmap_deactivate_efirt(void); 384 385 void pmap_procwr(struct proc *, vaddr_t, int); 386 void pmap_icache_sync_range(pmap_t, vaddr_t, vaddr_t); 387 388 void pmap_pv_init(void); 389 void pmap_pv_track(paddr_t, psize_t); 390 void pmap_pv_untrack(paddr_t, psize_t); 391 void pmap_pv_protect(paddr_t, vm_prot_t); 392 393 vsize_t pmap_kenter_range(vaddr_t, paddr_t, vsize_t, vm_prot_t, u_int); 394 395 #define PMAP_MAPSIZE1 L2_SIZE 396 397 /* for ddb */ 398 void pmap_db_pmap_print(struct pmap *, void (*)(const char *, ...) __printflike(1, 2)); 399 void pmap_db_mdpg_print(struct vm_page *, void (*)(const char *, ...) __printflike(1, 2)); 400 401 #endif /* !PMAP_MI */ 402 403 static inline void 404 pmap_md_asid_activate(tlb_asid_t asid, pmap_t pm, struct lwp *l) 405 { 406 407 KASSERT(kpreempt_disabled()); 408 409 // struct cpu_info * const ci = curcpu(); 410 411 /* 412 * Assume that TTBR1 has only global mappings and TTBR0 only 413 * has non-global mappings. To prevent speculation from doing 414 * evil things we disable translation table walks using TTBR0 415 * whilst there is no active userland pmap. Assert this here. 416 */ 417 KASSERT((reg_tcr_el1_read() & TCR_EPD0) != 0); 418 419 if (pm == pmap_kernel()) 420 return; 421 422 const uint64_t ttbr = 423 __SHIFTIN(asid, TTBR_ASID) | 424 __SHIFTIN(pmap_l0pa(pm), TTBR_BADDR); 425 426 cpu_set_ttbr0(ttbr); 427 428 const uint64_t tcr_el1 = reg_tcr_el1_read(); 429 reg_tcr_el1_write(tcr_el1 & ~TCR_EPD0); 430 isb(); 431 } 432 433 static inline void 434 pmap_md_asid_deactivate(pmap_t pm) 435 { 436 KASSERT(kpreempt_disabled()); 437 438 /* 439 * Disable translation table walks from TTBR0 while no userland 440 * pmap is active. 441 */ 442 const uint64_t tcr_el1 = reg_tcr_el1_read(); 443 reg_tcr_el1_write(tcr_el1 | TCR_EPD0); 444 isb(); 445 } 446 447 #endif /* _KERNEL */ 448 449 #elif defined(__arm__) 450 451 #include <arm/pmap.h> 452 453 #endif /* __arm__/__aarch64__ */ 454 455 #endif /* !_AARCH64_PMAP_ */ 456
Indexes created Wed Oct 14 00:28:03 UTC 2026