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      1 /*      $NetBSD: qv_ic.h,v 1.1 2015/07/05 03:07:21 matt Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2015 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Charles H. Dickman
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  * POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 /* registers */
     33 #define QV_IC_DR        0            /* data register */
     34 #define QV_IC_SR        2            /* status register */
     35 
     36 /* commands */
     37 #define QV_IC_RESET     0x00
     38 #define QV_IC_CIMR      0x28
     39 #define QV_IC_SIMR      0x38
     40 #define QV_IC_CLRIRR    0x40
     41 #define QV_IC_SIRR      0x58
     42 #define QV_IC_MODE      0x80
     43 #define QV_IC_ARM       0xa1
     44 #define QV_IC_DISARM    0xa2
     45 #define QV_IC_ACREG     0xc0
     46 #define QV_IC_RMEM      0xe0
     47 #define   RMEM_BC_1     0x00
     48 #define   RMEM_BC_2     0x08
     49 #define   RMEM_BC_3     0x10
     50 #define   RMEM_BC_4     0x18
     51 
     52 
     53 /* vectors */
     54 #define QV_DUART_VEC    0
     55 #define QV_SYNC_VEC     1
     56 #define QV_MOUSE_VEC    2
     57 #define QV_CURS_VEC     3
     58 #define QV_MBA_VEC      4
     59 #define QV_MBB_VEC      5
     60 #define QV_MBC_VEC      6
     61 
     62 #define QV_IC_ENA       1
     63 #define QV_IC_DIS       0
     64 
     65 void    qv_ic_init(struct uba_attach_args *, bus_size_t);
     66 void    qv_ic_setvec(struct uba_attach_args *, bus_size_t, int, int);
     67 void    qv_ic_enable(struct uba_attach_args *, bus_size_t, int, int);
     68 void    qv_ic_arm(struct uba_attach_args *, bus_size_t, int);
     69 void    qv_ic_force(struct uba_attach_args *, bus_size_t, int);
     70 
     71