| /src/external/gpl3/gdb/dist/sim/testsuite/bfin/ |
| s20.s | 13 R2 = ALIGN8 ( R1 , R0 );
14 DBGA ( R2.L , 0x34ab );
15 DBGA ( R2.H , 0x6712 );
17 R2 = ALIGN16 ( R1 , R0 );
18 DBGA ( R2.L , 0x1234 );
19 DBGA ( R2.H , 0x4567 );
21 R2 = ALIGN24 ( R1 , R0 );
22 DBGA ( R2.L , 0x6712 );
23 DBGA ( R2.H , 0xad45 );
|
| a30.s | 12 R2 = R0 +|+ R1, R3 = R0 -|- R1 (S , ASR);
13 _DBGCMPLX R2;
16 DBGA ( R2.L , 0.5 );
17 DBGA ( R2.H , 0.5 );
24 R2 = R0 +|+ R1, R3 = R0 -|- R1 (S , ASR);
25 _DBGCMPLX R2;
27 DBGA ( R2.L , 0.3125 );
28 DBGA ( R2.H , 0.3125 );
32 R0 = R2 +|+ R3, R1 = R2 -|- R3 (S , ASR)
[all...] |
| brevadd.s | 13 R2 = I2;
15 CC = R2 == R0
|
| cli-sti.s | 13 R2 = 0x1f;
14 CC = R1 == R2;
|
| issue119.s | 8 R2 = 0;
14 R2.H = (A1 = R0.L * R1.H) (M), R2.L = (A0 = R0.L * R1.L) (TFU);
16 _DBG R2;
17 DBGA ( R2.L , 0x3fff );
18 DBGA ( R2.H , 0xc000 );
20 R3 = ( A1 = R0.L * R1.H ) (M), R2 = ( A0 = R0.L * R1.L ) (FU);
|
| random_0009.S | 20 imm32 R2, 0x80008000;
21 A0 -= R2.H * R2.L (W32);
39 imm32 R2, 0xffffb33a;
41 R2 = (A0 -= R0.L * R3.H) (FU);
42 checkreg R2, 0x00000000;
72 imm32 R2, 0xf62c7780;
74 R2.L = (A0 -= R3.L * R0.L) (IH);
75 checkreg R2, 0xf62c8000;
|
| se_all64bitg1opcodes.S | 19 R2 = W[P5 + 4];
20 R0 = R2;
25 R0 = R2;
|
| se_all64bitg2opcodes.S | 19 R2 = W[P5 + 6];
20 R0 = R2;
25 R0 = R2;
|
| testset.s | 17 imm32 R2, 0xdeadbeef
35 R2 = [P4];
39 CC = R2 == R1;
|
| acc-rot.s | 9 R2 = \cc;
13 CC = R2;
20 R2 = \acc\().W;
21 CHECKREG R2, \exp_w;
|
| issue257.s | 9 R2 = 0;
13 R2.H = R0 - R1 (RND20);
15 _DBG R2;
17 DBGA ( R2.H , 0 );
|
| l2_loop.s | 9 R2 = i0;
21 R0 = R0 - R2;
|
| se_all32bitopcodes.S | 25 R2 = [P5];
26 R0 = R2 << 16;
27 R1 = R2 >> 16;
33 R0 = R2;
71 R2 = R0 & R1;
73 CC = R1 == R2;
[all...] |
| se_all64bitg0opcodes.S | 24 R2 = [P5];
25 R0 = R2 << 16;
26 R1 = R2 >> 16;
32 R0 = R2;
60 R2 = R0;
62 R2.L = 0xe802;
64 IF CC R0 = R2;
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/testsuite/bfin/ |
| s20.s | 13 R2 = ALIGN8 ( R1 , R0 );
14 DBGA ( R2.L , 0x34ab );
15 DBGA ( R2.H , 0x6712 );
17 R2 = ALIGN16 ( R1 , R0 );
18 DBGA ( R2.L , 0x1234 );
19 DBGA ( R2.H , 0x4567 );
21 R2 = ALIGN24 ( R1 , R0 );
22 DBGA ( R2.L , 0x6712 );
23 DBGA ( R2.H , 0xad45 );
|
| a30.s | 12 R2 = R0 +|+ R1, R3 = R0 -|- R1 (S , ASR);
13 _DBGCMPLX R2;
16 DBGA ( R2.L , 0.5 );
17 DBGA ( R2.H , 0.5 );
24 R2 = R0 +|+ R1, R3 = R0 -|- R1 (S , ASR);
25 _DBGCMPLX R2;
27 DBGA ( R2.L , 0.3125 );
28 DBGA ( R2.H , 0.3125 );
32 R0 = R2 +|+ R3, R1 = R2 -|- R3 (S , ASR)
[all...] |
| brevadd.s | 13 R2 = I2;
15 CC = R2 == R0
|
| cli-sti.s | 13 R2 = 0x1f;
14 CC = R1 == R2;
|
| issue119.s | 8 R2 = 0;
14 R2.H = (A1 = R0.L * R1.H) (M), R2.L = (A0 = R0.L * R1.L) (TFU);
16 _DBG R2;
17 DBGA ( R2.L , 0x3fff );
18 DBGA ( R2.H , 0xc000 );
20 R3 = ( A1 = R0.L * R1.H ) (M), R2 = ( A0 = R0.L * R1.L ) (FU);
|
| random_0009.S | 20 imm32 R2, 0x80008000;
21 A0 -= R2.H * R2.L (W32);
39 imm32 R2, 0xffffb33a;
41 R2 = (A0 -= R0.L * R3.H) (FU);
42 checkreg R2, 0x00000000;
72 imm32 R2, 0xf62c7780;
74 R2.L = (A0 -= R3.L * R0.L) (IH);
75 checkreg R2, 0xf62c8000;
|
| se_all64bitg1opcodes.S | 19 R2 = W[P5 + 4];
20 R0 = R2;
25 R0 = R2;
|
| se_all64bitg2opcodes.S | 19 R2 = W[P5 + 6];
20 R0 = R2;
25 R0 = R2;
|
| testset.s | 17 imm32 R2, 0xdeadbeef
35 R2 = [P4];
39 CC = R2 == R1;
|
| acc-rot.s | 9 R2 = \cc;
13 CC = R2;
20 R2 = \acc\().W;
21 CHECKREG R2, \exp_w;
|
| issue257.s | 9 R2 = 0;
13 R2.H = R0 - R1 (RND20);
15 _DBG R2;
17 DBGA ( R2.H , 0 );
|
