1 /* $NetBSD: wstsc.c,v 1.37 2021/08/07 16:18:41 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1982, 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of the University nor the names of its contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * @(#)supradma.c 32 */ 33 34 /* 35 * Copyright (c) 1994 Michael L. Hitch 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 46 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 47 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 48 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 49 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 50 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 51 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 52 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 53 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 54 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 55 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 56 * 57 * @(#)supradma.c 58 */ 59 60 #include <sys/cdefs.h> 61 __KERNEL_RCSID(0, "$NetBSD: wstsc.c,v 1.37 2021/08/07 16:18:41 thorpej Exp $"); 62 63 #include <sys/param.h> 64 #include <sys/systm.h> 65 #include <sys/kernel.h> 66 #include <sys/device.h> 67 #include <dev/scsipi/scsi_all.h> 68 #include <dev/scsipi/scsipi_all.h> 69 #include <dev/scsipi/scsiconf.h> 70 #include <amiga/amiga/device.h> 71 #include <amiga/amiga/isr.h> 72 #include <amiga/dev/scireg.h> 73 #include <amiga/dev/scivar.h> 74 #include <amiga/dev/zbusvar.h> 75 76 void wstscattach(device_t, device_t, void *); 77 int wstscmatch(device_t, cfdata_t, void *); 78 79 int wstsc_dma_xfer_in(struct sci_softc *dev, int len, 80 register u_char *buf, int phase); 81 int wstsc_dma_xfer_out(struct sci_softc *dev, int len, 82 register u_char *buf, int phase); 83 int wstsc_dma_xfer_in2(struct sci_softc *dev, int len, 84 register u_short *buf, int phase); 85 int wstsc_dma_xfer_out2(struct sci_softc *dev, int len, 86 register u_short *buf, int phase); 87 int wstsc_intr(void *); 88 89 #ifdef DEBUG 90 extern int sci_debug; 91 #define QPRINTF(a) if (sci_debug > 1) printf a 92 #else 93 #define QPRINTF(a) 94 #endif 95 96 extern int sci_data_wait; 97 98 int supradma_pseudo = 0; /* 0=none, 1=byte, 2=word */ 99 100 CFATTACH_DECL_NEW(wstsc, sizeof(struct sci_softc), 101 wstscmatch, wstscattach, NULL, NULL); 102 103 /* 104 * if this a Supra WordSync board 105 */ 106 int 107 wstscmatch(device_t parent, cfdata_t cf, void *aux) 108 { 109 struct zbus_args *zap; 110 111 zap = aux; 112 113 /* 114 * Check manufacturer and product id. 115 */ 116 if (zap->manid == 1056 && ( 117 zap->prodid == 12 || /* WordSync */ 118 zap->prodid == 13)) /* ByteSync */ 119 return(1); 120 else 121 return(0); 122 } 123 124 void 125 wstscattach(device_t parent, device_t self, void *aux) 126 { 127 volatile u_char *rp; 128 struct sci_softc *sc = device_private(self); 129 struct zbus_args *zap; 130 struct scsipi_adapter *adapt = &sc->sc_adapter; 131 struct scsipi_channel *chan = &sc->sc_channel; 132 133 sc->sc_dev = self; 134 135 printf("\n"); 136 137 zap = aux; 138 139 rp = zap->va; 140 /* 141 * set up 5380 register pointers 142 * (Needs check on which Supra board this is - for now, 143 * just do the WordSync) 144 */ 145 sc->sci_data = rp + 0; 146 sc->sci_odata = rp + 0; 147 sc->sci_icmd = rp + 2; 148 sc->sci_mode = rp + 4; 149 sc->sci_tcmd = rp + 6; 150 sc->sci_bus_csr = rp + 8; 151 sc->sci_sel_enb = rp + 8; 152 sc->sci_csr = rp + 10; 153 sc->sci_dma_send = rp + 10; 154 sc->sci_idata = rp + 12; 155 sc->sci_trecv = rp + 12; 156 sc->sci_iack = rp + 14; 157 sc->sci_irecv = rp + 14; 158 159 if (supradma_pseudo == 2) { 160 sc->dma_xfer_in = (int(*)(struct sci_softc *, int, u_char *, int))wstsc_dma_xfer_in2; 161 sc->dma_xfer_out = (int(*)(struct sci_softc *, int, u_char *, int))wstsc_dma_xfer_out2; 162 } 163 else if (supradma_pseudo == 1) { 164 sc->dma_xfer_in = wstsc_dma_xfer_in; 165 sc->dma_xfer_out = wstsc_dma_xfer_out; 166 } 167 168 sc->sc_isr.isr_intr = wstsc_intr; 169 sc->sc_isr.isr_arg = sc; 170 sc->sc_isr.isr_ipl = 2; 171 add_isr(&sc->sc_isr); 172 173 scireset(sc); 174 175 /* 176 * Fill in the scsipi_adapter. 177 */ 178 memset(adapt, 0, sizeof(*adapt)); 179 adapt->adapt_dev = self; 180 adapt->adapt_nchannels = 1; 181 adapt->adapt_openings = 7; 182 adapt->adapt_max_periph = 1; 183 adapt->adapt_request = sci_scsipi_request; 184 adapt->adapt_minphys = sci_minphys; 185 186 /* 187 * Fill in the scsipi_channel. 188 */ 189 memset(chan, 0, sizeof(*chan)); 190 chan->chan_adapter = adapt; 191 chan->chan_bustype = &scsi_bustype; 192 chan->chan_channel = 0; 193 chan->chan_ntargets = 8; 194 chan->chan_nluns = 8; 195 chan->chan_id = 7; 196 197 /* 198 * attach all scsi units on us 199 */ 200 config_found(self, chan, scsiprint, CFARGS_NONE); 201 } 202 203 int 204 wstsc_dma_xfer_in(struct sci_softc *dev, int len, register u_char *buf, 205 int phase) 206 { 207 int wait = sci_data_wait; 208 volatile register u_char *sci_dma = dev->sci_idata; 209 volatile register u_char *sci_csr = dev->sci_csr; 210 #ifdef DEBUG 211 u_char *obp = (u_char *) buf; 212 #endif 213 214 QPRINTF(("supradma_in %d, csr=%02x\n", len, *dev->sci_bus_csr)); 215 216 *dev->sci_tcmd = phase; 217 *dev->sci_icmd = 0; 218 *dev->sci_mode = SCI_MODE_DMA; 219 *dev->sci_irecv = 0; 220 221 while (len >= 128) { 222 wait = sci_data_wait; 223 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 224 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 225 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 226 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 227 || --wait < 0) { 228 #ifdef DEBUG 229 if (sci_debug | 1) 230 printf("supradma2_in fail: l%d i%x w%d\n", 231 len, *dev->sci_bus_csr, wait); 232 #endif 233 *dev->sci_mode = 0; 234 return 0; 235 } 236 } 237 238 #define R1 (*buf++ = *sci_dma) 239 R1; R1; R1; R1; R1; R1; R1; R1; 240 R1; R1; R1; R1; R1; R1; R1; R1; 241 R1; R1; R1; R1; R1; R1; R1; R1; 242 R1; R1; R1; R1; R1; R1; R1; R1; 243 R1; R1; R1; R1; R1; R1; R1; R1; 244 R1; R1; R1; R1; R1; R1; R1; R1; 245 R1; R1; R1; R1; R1; R1; R1; R1; 246 R1; R1; R1; R1; R1; R1; R1; R1; 247 R1; R1; R1; R1; R1; R1; R1; R1; 248 R1; R1; R1; R1; R1; R1; R1; R1; 249 R1; R1; R1; R1; R1; R1; R1; R1; 250 R1; R1; R1; R1; R1; R1; R1; R1; 251 R1; R1; R1; R1; R1; R1; R1; R1; 252 R1; R1; R1; R1; R1; R1; R1; R1; 253 R1; R1; R1; R1; R1; R1; R1; R1; 254 R1; R1; R1; R1; R1; R1; R1; R1; 255 len -= 128; 256 } 257 258 while (len > 0) { 259 wait = sci_data_wait; 260 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 261 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 262 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 263 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 264 || --wait < 0) { 265 #ifdef DEBUG 266 if (sci_debug | 1) 267 printf("supradma1_in fail: l%d i%x w%d\n", 268 len, *dev->sci_bus_csr, wait); 269 #endif 270 *dev->sci_mode = 0; 271 return 0; 272 } 273 } 274 275 *buf++ = *sci_dma; 276 len--; 277 } 278 279 QPRINTF(("supradma_in {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 280 len, obp[0], obp[1], obp[2], obp[3], obp[4], obp[5], 281 obp[6], obp[7], obp[8], obp[9])); 282 283 *dev->sci_mode = 0; 284 return 0; 285 } 286 287 int 288 wstsc_dma_xfer_out(struct sci_softc *dev, int len, register u_char *buf, 289 int phase) 290 { 291 int wait = sci_data_wait; 292 volatile register u_char *sci_dma = dev->sci_data; 293 volatile register u_char *sci_csr = dev->sci_csr; 294 295 QPRINTF(("supradma_out %d, csr=%02x\n", len, *dev->sci_bus_csr)); 296 297 QPRINTF(("supradma_out {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 298 len, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], 299 buf[6], buf[7], buf[8], buf[9])); 300 301 *dev->sci_tcmd = phase; 302 *dev->sci_mode = SCI_MODE_DMA; 303 *dev->sci_icmd = SCI_ICMD_DATA; 304 *dev->sci_dma_send = 0; 305 while (len > 0) { 306 wait = sci_data_wait; 307 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 308 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 309 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 310 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 311 || --wait < 0) { 312 #ifdef DEBUG 313 if (sci_debug) 314 printf("supradma_out fail: l%d i%x w%d\n", 315 len, *dev->sci_bus_csr, wait); 316 #endif 317 *dev->sci_mode = 0; 318 return 0; 319 } 320 } 321 322 *sci_dma = *buf++; 323 len--; 324 } 325 326 wait = sci_data_wait; 327 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) == 328 SCI_CSR_PHASE_MATCH && --wait); 329 330 331 *dev->sci_mode = 0; 332 *dev->sci_icmd = 0; 333 return 0; 334 } 335 336 337 int 338 wstsc_dma_xfer_in2(struct sci_softc *dev, int len, register u_short *buf, 339 int phase) 340 { 341 volatile register u_short *sci_dma = 342 (volatile u_short *)(dev->sci_idata + 0x10); 343 volatile register u_char *sci_csr = dev->sci_csr + 0x10; 344 #ifdef DEBUG 345 u_char *obp = (u_char *) buf; 346 #endif 347 #if 0 348 int wait = sci_data_wait; 349 #endif 350 351 QPRINTF(("supradma_in2 %d, csr=%02x\n", len, *dev->sci_bus_csr)); 352 353 *dev->sci_tcmd = phase; 354 *dev->sci_mode = SCI_MODE_DMA; 355 *dev->sci_icmd = 0; 356 *(dev->sci_irecv + 16) = 0; 357 while (len >= 128) { 358 #if 0 359 wait = sci_data_wait; 360 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 361 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 362 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 363 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 364 || --wait < 0) { 365 #ifdef DEBUG 366 if (sci_debug | 1) 367 printf("supradma2_in2 fail: l%d i%x w%d\n", 368 len, *dev->sci_bus_csr, wait); 369 #endif 370 *dev->sci_mode &= ~SCI_MODE_DMA; 371 return 0; 372 } 373 } 374 #else 375 while (!(*sci_csr & SCI_CSR_DREQ)) 376 ; 377 #endif 378 379 #define R2 (*buf++ = *sci_dma) 380 R2; R2; R2; R2; R2; R2; R2; R2; 381 R2; R2; R2; R2; R2; R2; R2; R2; 382 R2; R2; R2; R2; R2; R2; R2; R2; 383 R2; R2; R2; R2; R2; R2; R2; R2; 384 R2; R2; R2; R2; R2; R2; R2; R2; 385 R2; R2; R2; R2; R2; R2; R2; R2; 386 R2; R2; R2; R2; R2; R2; R2; R2; 387 R2; R2; R2; R2; R2; R2; R2; R2; 388 len -= 128; 389 } 390 while (len > 0) { 391 #if 0 392 wait = sci_data_wait; 393 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 394 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 395 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 396 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 397 || --wait < 0) { 398 #ifdef DEBUG 399 if (sci_debug | 1) 400 printf("supradma1_in2 fail: l%d i%x w%d\n", 401 len, *dev->sci_bus_csr, wait); 402 #endif 403 *dev->sci_mode &= ~SCI_MODE_DMA; 404 return 0; 405 } 406 } 407 #else 408 while (!(*sci_csr & SCI_CSR_DREQ)) 409 ; 410 #endif 411 412 *buf++ = *sci_dma; 413 len -= 2; 414 } 415 416 QPRINTF(("supradma_in2 {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 417 len, obp[0], obp[1], obp[2], obp[3], obp[4], obp[5], 418 obp[6], obp[7], obp[8], obp[9])); 419 420 *dev->sci_irecv = 0; 421 *dev->sci_mode = 0; 422 return 0; 423 } 424 425 int 426 wstsc_dma_xfer_out2(struct sci_softc *dev, int len, register u_short *buf, 427 int phase) 428 { 429 volatile register u_short *sci_dma = 430 (volatile ushort *)(dev->sci_data + 0x10); 431 volatile register u_char *sci_bus_csr = dev->sci_bus_csr; 432 #ifdef DEBUG 433 u_char *obp = (u_char *) buf; 434 #endif 435 #if 0 436 int wait = sci_data_wait; 437 #endif 438 439 QPRINTF(("supradma_out2 %d, csr=%02x\n", len, *dev->sci_bus_csr)); 440 441 QPRINTF(("supradma_out2 {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 442 len, obp[0], obp[1], obp[2], obp[3], obp[4], obp[5], 443 obp[6], obp[7], obp[8], obp[9])); 444 445 *dev->sci_tcmd = phase; 446 *dev->sci_mode = SCI_MODE_DMA; 447 *dev->sci_icmd = SCI_ICMD_DATA; 448 *dev->sci_dma_send = 0; 449 while (len > 64) { 450 #if 0 451 wait = sci_data_wait; 452 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 453 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 454 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 455 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 456 || --wait < 0) { 457 #ifdef DEBUG 458 if (sci_debug) 459 printf("supradma_out2 fail: l%d i%x w%d\n", 460 len, csr, wait); 461 #endif 462 *dev->sci_mode = 0; 463 return 0; 464 } 465 } 466 #else 467 *dev->sci_mode = 0; 468 *dev->sci_icmd &= ~SCI_ICMD_ACK; 469 while (!(*sci_bus_csr & SCI_BUS_REQ)) 470 ; 471 *dev->sci_mode = SCI_MODE_DMA; 472 *dev->sci_dma_send = 0; 473 #endif 474 475 #define W2 (*sci_dma = *buf++) 476 W2; W2; W2; W2; W2; W2; W2; W2; 477 W2; W2; W2; W2; W2; W2; W2; W2; 478 if (*(sci_bus_csr + 0x10) & SCI_BUS_REQ) 479 ; 480 len -= 64; 481 } 482 483 while (len > 0) { 484 #if 0 485 wait = sci_data_wait; 486 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 487 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 488 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 489 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 490 || --wait < 0) { 491 #ifdef DEBUG 492 if (sci_debug) 493 printf("supradma_out2 fail: l%d i%x w%d\n", 494 len, csr, wait); 495 #endif 496 *dev->sci_mode = 0; 497 return 0; 498 } 499 } 500 #else 501 *dev->sci_mode = 0; 502 *dev->sci_icmd &= ~SCI_ICMD_ACK; 503 while (!(*sci_bus_csr & SCI_BUS_REQ)) 504 ; 505 *dev->sci_mode = SCI_MODE_DMA; 506 *dev->sci_dma_send = 0; 507 #endif 508 509 *sci_dma = *buf++; 510 if (*(sci_bus_csr + 0x10) & SCI_BUS_REQ) 511 ; 512 len -= 2; 513 } 514 515 #if 0 516 wait = sci_data_wait; 517 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) == 518 SCI_CSR_PHASE_MATCH && --wait); 519 #endif 520 521 522 *dev->sci_irecv = 0; 523 *dev->sci_icmd &= ~SCI_ICMD_ACK; 524 *dev->sci_mode = 0; 525 *dev->sci_icmd = 0; 526 return 0; 527 } 528 529 int 530 wstsc_intr(void *arg) 531 { 532 struct sci_softc *dev = arg; 533 u_char stat; 534 535 if ((*(dev->sci_csr + 0x10) & SCI_CSR_INT) == 0) 536 return (0); 537 stat = *(dev->sci_iack + 0x10); 538 __USE(stat); 539 return (1); 540 } 541
Indexes created Sat Sep 20 22:09:52 GMT 2025