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      1 /*	$NetBSD: radeon_drm.h,v 1.2 2021/12/18 23:45:46 riastradh Exp $	*/
      2 
      3 /* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*-
      4  *
      5  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
      6  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
      7  * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
      8  * All rights reserved.
      9  *
     10  * Permission is hereby granted, free of charge, to any person obtaining a
     11  * copy of this software and associated documentation files (the "Software"),
     12  * to deal in the Software without restriction, including without limitation
     13  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     14  * and/or sell copies of the Software, and to permit persons to whom the
     15  * Software is furnished to do so, subject to the following conditions:
     16  *
     17  * The above copyright notice and this permission notice (including the next
     18  * paragraph) shall be included in all copies or substantial portions of the
     19  * Software.
     20  *
     21  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     22  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     23  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     24  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
     25  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     26  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
     27  * DEALINGS IN THE SOFTWARE.
     28  *
     29  * Authors:
     30  *    Kevin E. Martin <martin (at) valinux.com>
     31  *    Gareth Hughes <gareth (at) valinux.com>
     32  *    Keith Whitwell <keith (at) tungstengraphics.com>
     33  */
     34 
     35 #ifndef __RADEON_DRM_H__
     36 #define __RADEON_DRM_H__
     37 
     38 #include "drm.h"
     39 
     40 #if defined(__cplusplus)
     41 extern "C" {
     42 #endif
     43 
     44 /* WARNING: If you change any of these defines, make sure to change the
     45  * defines in the X server file (radeon_sarea.h)
     46  */
     47 #ifndef __RADEON_SAREA_DEFINES__
     48 #define __RADEON_SAREA_DEFINES__
     49 
     50 /* Old style state flags, required for sarea interface (1.1 and 1.2
     51  * clears) and 1.2 drm_vertex2 ioctl.
     52  */
     53 #define RADEON_UPLOAD_CONTEXT		0x00000001
     54 #define RADEON_UPLOAD_VERTFMT		0x00000002
     55 #define RADEON_UPLOAD_LINE		0x00000004
     56 #define RADEON_UPLOAD_BUMPMAP		0x00000008
     57 #define RADEON_UPLOAD_MASKS		0x00000010
     58 #define RADEON_UPLOAD_VIEWPORT		0x00000020
     59 #define RADEON_UPLOAD_SETUP		0x00000040
     60 #define RADEON_UPLOAD_TCL		0x00000080
     61 #define RADEON_UPLOAD_MISC		0x00000100
     62 #define RADEON_UPLOAD_TEX0		0x00000200
     63 #define RADEON_UPLOAD_TEX1		0x00000400
     64 #define RADEON_UPLOAD_TEX2		0x00000800
     65 #define RADEON_UPLOAD_TEX0IMAGES	0x00001000
     66 #define RADEON_UPLOAD_TEX1IMAGES	0x00002000
     67 #define RADEON_UPLOAD_TEX2IMAGES	0x00004000
     68 #define RADEON_UPLOAD_CLIPRECTS		0x00008000	/* handled client-side */
     69 #define RADEON_REQUIRE_QUIESCENCE	0x00010000
     70 #define RADEON_UPLOAD_ZBIAS		0x00020000	/* version 1.2 and newer */
     71 #define RADEON_UPLOAD_ALL		0x003effff
     72 #define RADEON_UPLOAD_CONTEXT_ALL       0x003e01ff
     73 
     74 /* New style per-packet identifiers for use in cmd_buffer ioctl with
     75  * the RADEON_EMIT_PACKET command.  Comments relate new packets to old
     76  * state bits and the packet size:
     77  */
     78 #define RADEON_EMIT_PP_MISC                         0	/* context/7 */
     79 #define RADEON_EMIT_PP_CNTL                         1	/* context/3 */
     80 #define RADEON_EMIT_RB3D_COLORPITCH                 2	/* context/1 */
     81 #define RADEON_EMIT_RE_LINE_PATTERN                 3	/* line/2 */
     82 #define RADEON_EMIT_SE_LINE_WIDTH                   4	/* line/1 */
     83 #define RADEON_EMIT_PP_LUM_MATRIX                   5	/* bumpmap/1 */
     84 #define RADEON_EMIT_PP_ROT_MATRIX_0                 6	/* bumpmap/2 */
     85 #define RADEON_EMIT_RB3D_STENCILREFMASK             7	/* masks/3 */
     86 #define RADEON_EMIT_SE_VPORT_XSCALE                 8	/* viewport/6 */
     87 #define RADEON_EMIT_SE_CNTL                         9	/* setup/2 */
     88 #define RADEON_EMIT_SE_CNTL_STATUS                  10	/* setup/1 */
     89 #define RADEON_EMIT_RE_MISC                         11	/* misc/1 */
     90 #define RADEON_EMIT_PP_TXFILTER_0                   12	/* tex0/6 */
     91 #define RADEON_EMIT_PP_BORDER_COLOR_0               13	/* tex0/1 */
     92 #define RADEON_EMIT_PP_TXFILTER_1                   14	/* tex1/6 */
     93 #define RADEON_EMIT_PP_BORDER_COLOR_1               15	/* tex1/1 */
     94 #define RADEON_EMIT_PP_TXFILTER_2                   16	/* tex2/6 */
     95 #define RADEON_EMIT_PP_BORDER_COLOR_2               17	/* tex2/1 */
     96 #define RADEON_EMIT_SE_ZBIAS_FACTOR                 18	/* zbias/2 */
     97 #define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT           19	/* tcl/11 */
     98 #define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED   20	/* material/17 */
     99 #define R200_EMIT_PP_TXCBLEND_0                     21	/* tex0/4 */
    100 #define R200_EMIT_PP_TXCBLEND_1                     22	/* tex1/4 */
    101 #define R200_EMIT_PP_TXCBLEND_2                     23	/* tex2/4 */
    102 #define R200_EMIT_PP_TXCBLEND_3                     24	/* tex3/4 */
    103 #define R200_EMIT_PP_TXCBLEND_4                     25	/* tex4/4 */
    104 #define R200_EMIT_PP_TXCBLEND_5                     26	/* tex5/4 */
    105 #define R200_EMIT_PP_TXCBLEND_6                     27	/* /4 */
    106 #define R200_EMIT_PP_TXCBLEND_7                     28	/* /4 */
    107 #define R200_EMIT_TCL_LIGHT_MODEL_CTL_0             29	/* tcl/7 */
    108 #define R200_EMIT_TFACTOR_0                         30	/* tf/7 */
    109 #define R200_EMIT_VTX_FMT_0                         31	/* vtx/5 */
    110 #define R200_EMIT_VAP_CTL                           32	/* vap/1 */
    111 #define R200_EMIT_MATRIX_SELECT_0                   33	/* msl/5 */
    112 #define R200_EMIT_TEX_PROC_CTL_2                    34	/* tcg/5 */
    113 #define R200_EMIT_TCL_UCP_VERT_BLEND_CTL            35	/* tcl/1 */
    114 #define R200_EMIT_PP_TXFILTER_0                     36	/* tex0/6 */
    115 #define R200_EMIT_PP_TXFILTER_1                     37	/* tex1/6 */
    116 #define R200_EMIT_PP_TXFILTER_2                     38	/* tex2/6 */
    117 #define R200_EMIT_PP_TXFILTER_3                     39	/* tex3/6 */
    118 #define R200_EMIT_PP_TXFILTER_4                     40	/* tex4/6 */
    119 #define R200_EMIT_PP_TXFILTER_5                     41	/* tex5/6 */
    120 #define R200_EMIT_PP_TXOFFSET_0                     42	/* tex0/1 */
    121 #define R200_EMIT_PP_TXOFFSET_1                     43	/* tex1/1 */
    122 #define R200_EMIT_PP_TXOFFSET_2                     44	/* tex2/1 */
    123 #define R200_EMIT_PP_TXOFFSET_3                     45	/* tex3/1 */
    124 #define R200_EMIT_PP_TXOFFSET_4                     46	/* tex4/1 */
    125 #define R200_EMIT_PP_TXOFFSET_5                     47	/* tex5/1 */
    126 #define R200_EMIT_VTE_CNTL                          48	/* vte/1 */
    127 #define R200_EMIT_OUTPUT_VTX_COMP_SEL               49	/* vtx/1 */
    128 #define R200_EMIT_PP_TAM_DEBUG3                     50	/* tam/1 */
    129 #define R200_EMIT_PP_CNTL_X                         51	/* cst/1 */
    130 #define R200_EMIT_RB3D_DEPTHXY_OFFSET               52	/* cst/1 */
    131 #define R200_EMIT_RE_AUX_SCISSOR_CNTL               53	/* cst/1 */
    132 #define R200_EMIT_RE_SCISSOR_TL_0                   54	/* cst/2 */
    133 #define R200_EMIT_RE_SCISSOR_TL_1                   55	/* cst/2 */
    134 #define R200_EMIT_RE_SCISSOR_TL_2                   56	/* cst/2 */
    135 #define R200_EMIT_SE_VAP_CNTL_STATUS                57	/* cst/1 */
    136 #define R200_EMIT_SE_VTX_STATE_CNTL                 58	/* cst/1 */
    137 #define R200_EMIT_RE_POINTSIZE                      59	/* cst/1 */
    138 #define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0       60	/* cst/4 */
    139 #define R200_EMIT_PP_CUBIC_FACES_0                  61
    140 #define R200_EMIT_PP_CUBIC_OFFSETS_0                62
    141 #define R200_EMIT_PP_CUBIC_FACES_1                  63
    142 #define R200_EMIT_PP_CUBIC_OFFSETS_1                64
    143 #define R200_EMIT_PP_CUBIC_FACES_2                  65
    144 #define R200_EMIT_PP_CUBIC_OFFSETS_2                66
    145 #define R200_EMIT_PP_CUBIC_FACES_3                  67
    146 #define R200_EMIT_PP_CUBIC_OFFSETS_3                68
    147 #define R200_EMIT_PP_CUBIC_FACES_4                  69
    148 #define R200_EMIT_PP_CUBIC_OFFSETS_4                70
    149 #define R200_EMIT_PP_CUBIC_FACES_5                  71
    150 #define R200_EMIT_PP_CUBIC_OFFSETS_5                72
    151 #define RADEON_EMIT_PP_TEX_SIZE_0                   73
    152 #define RADEON_EMIT_PP_TEX_SIZE_1                   74
    153 #define RADEON_EMIT_PP_TEX_SIZE_2                   75
    154 #define R200_EMIT_RB3D_BLENDCOLOR                   76
    155 #define R200_EMIT_TCL_POINT_SPRITE_CNTL             77
    156 #define RADEON_EMIT_PP_CUBIC_FACES_0                78
    157 #define RADEON_EMIT_PP_CUBIC_OFFSETS_T0             79
    158 #define RADEON_EMIT_PP_CUBIC_FACES_1                80
    159 #define RADEON_EMIT_PP_CUBIC_OFFSETS_T1             81
    160 #define RADEON_EMIT_PP_CUBIC_FACES_2                82
    161 #define RADEON_EMIT_PP_CUBIC_OFFSETS_T2             83
    162 #define R200_EMIT_PP_TRI_PERF_CNTL                  84
    163 #define R200_EMIT_PP_AFS_0                          85
    164 #define R200_EMIT_PP_AFS_1                          86
    165 #define R200_EMIT_ATF_TFACTOR                       87
    166 #define R200_EMIT_PP_TXCTLALL_0                     88
    167 #define R200_EMIT_PP_TXCTLALL_1                     89
    168 #define R200_EMIT_PP_TXCTLALL_2                     90
    169 #define R200_EMIT_PP_TXCTLALL_3                     91
    170 #define R200_EMIT_PP_TXCTLALL_4                     92
    171 #define R200_EMIT_PP_TXCTLALL_5                     93
    172 #define R200_EMIT_VAP_PVS_CNTL                      94
    173 #define RADEON_MAX_STATE_PACKETS                    95
    174 
    175 /* Commands understood by cmd_buffer ioctl.  More can be added but
    176  * obviously these can't be removed or changed:
    177  */
    178 #define RADEON_CMD_PACKET      1	/* emit one of the register packets above */
    179 #define RADEON_CMD_SCALARS     2	/* emit scalar data */
    180 #define RADEON_CMD_VECTORS     3	/* emit vector data */
    181 #define RADEON_CMD_DMA_DISCARD 4	/* discard current dma buf */
    182 #define RADEON_CMD_PACKET3     5	/* emit hw packet */
    183 #define RADEON_CMD_PACKET3_CLIP 6	/* emit hw packet wrapped in cliprects */
    184 #define RADEON_CMD_SCALARS2     7	/* r200 stopgap */
    185 #define RADEON_CMD_WAIT         8	/* emit hw wait commands -- note:
    186 					 *  doesn't make the cpu wait, just
    187 					 *  the graphics hardware */
    188 #define RADEON_CMD_VECLINEAR	9       /* another r200 stopgap */
    189 
    190 typedef union {
    191 	int i;
    192 	struct {
    193 		unsigned char cmd_type, pad0, pad1, pad2;
    194 	} header;
    195 	struct {
    196 		unsigned char cmd_type, packet_id, pad0, pad1;
    197 	} packet;
    198 	struct {
    199 		unsigned char cmd_type, offset, stride, count;
    200 	} scalars;
    201 	struct {
    202 		unsigned char cmd_type, offset, stride, count;
    203 	} vectors;
    204 	struct {
    205 		unsigned char cmd_type, addr_lo, addr_hi, count;
    206 	} veclinear;
    207 	struct {
    208 		unsigned char cmd_type, buf_idx, pad0, pad1;
    209 	} dma;
    210 	struct {
    211 		unsigned char cmd_type, flags, pad0, pad1;
    212 	} wait;
    213 } drm_radeon_cmd_header_t;
    214 
    215 #define RADEON_WAIT_2D  0x1
    216 #define RADEON_WAIT_3D  0x2
    217 
    218 /* Allowed parameters for R300_CMD_PACKET3
    219  */
    220 #define R300_CMD_PACKET3_CLEAR		0
    221 #define R300_CMD_PACKET3_RAW		1
    222 
    223 /* Commands understood by cmd_buffer ioctl for R300.
    224  * The interface has not been stabilized, so some of these may be removed
    225  * and eventually reordered before stabilization.
    226  */
    227 #define R300_CMD_PACKET0		1
    228 #define R300_CMD_VPU			2	/* emit vertex program upload */
    229 #define R300_CMD_PACKET3		3	/* emit a packet3 */
    230 #define R300_CMD_END3D			4	/* emit sequence ending 3d rendering */
    231 #define R300_CMD_CP_DELAY		5
    232 #define R300_CMD_DMA_DISCARD		6
    233 #define R300_CMD_WAIT			7
    234 #	define R300_WAIT_2D		0x1
    235 #	define R300_WAIT_3D		0x2
    236 /* these two defines are DOING IT WRONG - however
    237  * we have userspace which relies on using these.
    238  * The wait interface is backwards compat new
    239  * code should use the NEW_WAIT defines below
    240  * THESE ARE NOT BIT FIELDS
    241  */
    242 #	define R300_WAIT_2D_CLEAN	0x3
    243 #	define R300_WAIT_3D_CLEAN	0x4
    244 
    245 #	define R300_NEW_WAIT_2D_3D	0x3
    246 #	define R300_NEW_WAIT_2D_2D_CLEAN	0x4
    247 #	define R300_NEW_WAIT_3D_3D_CLEAN	0x6
    248 #	define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN	0x8
    249 
    250 #define R300_CMD_SCRATCH		8
    251 #define R300_CMD_R500FP                 9
    252 
    253 typedef union {
    254 	unsigned int u;
    255 	struct {
    256 		unsigned char cmd_type, pad0, pad1, pad2;
    257 	} header;
    258 	struct {
    259 		unsigned char cmd_type, count, reglo, reghi;
    260 	} packet0;
    261 	struct {
    262 		unsigned char cmd_type, count, adrlo, adrhi;
    263 	} vpu;
    264 	struct {
    265 		unsigned char cmd_type, packet, pad0, pad1;
    266 	} packet3;
    267 	struct {
    268 		unsigned char cmd_type, packet;
    269 		unsigned short count;	/* amount of packet2 to emit */
    270 	} delay;
    271 	struct {
    272 		unsigned char cmd_type, buf_idx, pad0, pad1;
    273 	} dma;
    274 	struct {
    275 		unsigned char cmd_type, flags, pad0, pad1;
    276 	} wait;
    277 	struct {
    278 		unsigned char cmd_type, reg, n_bufs, flags;
    279 	} scratch;
    280 	struct {
    281 		unsigned char cmd_type, count, adrlo, adrhi_flags;
    282 	} r500fp;
    283 } drm_r300_cmd_header_t;
    284 
    285 #define RADEON_FRONT			0x1
    286 #define RADEON_BACK			0x2
    287 #define RADEON_DEPTH			0x4
    288 #define RADEON_STENCIL			0x8
    289 #define RADEON_CLEAR_FASTZ		0x80000000
    290 #define RADEON_USE_HIERZ		0x40000000
    291 #define RADEON_USE_COMP_ZBUF		0x20000000
    292 
    293 #define R500FP_CONSTANT_TYPE  (1 << 1)
    294 #define R500FP_CONSTANT_CLAMP (1 << 2)
    295 
    296 /* Primitive types
    297  */
    298 #define RADEON_POINTS			0x1
    299 #define RADEON_LINES			0x2
    300 #define RADEON_LINE_STRIP		0x3
    301 #define RADEON_TRIANGLES		0x4
    302 #define RADEON_TRIANGLE_FAN		0x5
    303 #define RADEON_TRIANGLE_STRIP		0x6
    304 
    305 /* Vertex/indirect buffer size
    306  */
    307 #define RADEON_BUFFER_SIZE		65536
    308 
    309 /* Byte offsets for indirect buffer data
    310  */
    311 #define RADEON_INDEX_PRIM_OFFSET	20
    312 
    313 #define RADEON_SCRATCH_REG_OFFSET	32
    314 
    315 #define R600_SCRATCH_REG_OFFSET         256
    316 
    317 #define RADEON_NR_SAREA_CLIPRECTS	12
    318 
    319 /* There are 2 heaps (local/GART).  Each region within a heap is a
    320  * minimum of 64k, and there are at most 64 of them per heap.
    321  */
    322 #define RADEON_LOCAL_TEX_HEAP		0
    323 #define RADEON_GART_TEX_HEAP		1
    324 #define RADEON_NR_TEX_HEAPS		2
    325 #define RADEON_NR_TEX_REGIONS		64
    326 #define RADEON_LOG_TEX_GRANULARITY	16
    327 
    328 #define RADEON_MAX_TEXTURE_LEVELS	12
    329 #define RADEON_MAX_TEXTURE_UNITS	3
    330 
    331 #define RADEON_MAX_SURFACES		8
    332 
    333 /* Blits have strict offset rules.  All blit offset must be aligned on
    334  * a 1K-byte boundary.
    335  */
    336 #define RADEON_OFFSET_SHIFT             10
    337 #define RADEON_OFFSET_ALIGN             (1 << RADEON_OFFSET_SHIFT)
    338 #define RADEON_OFFSET_MASK              (RADEON_OFFSET_ALIGN - 1)
    339 
    340 #endif				/* __RADEON_SAREA_DEFINES__ */
    341 
    342 typedef struct {
    343 	unsigned int red;
    344 	unsigned int green;
    345 	unsigned int blue;
    346 	unsigned int alpha;
    347 } radeon_color_regs_t;
    348 
    349 typedef struct {
    350 	/* Context state */
    351 	unsigned int pp_misc;	/* 0x1c14 */
    352 	unsigned int pp_fog_color;
    353 	unsigned int re_solid_color;
    354 	unsigned int rb3d_blendcntl;
    355 	unsigned int rb3d_depthoffset;
    356 	unsigned int rb3d_depthpitch;
    357 	unsigned int rb3d_zstencilcntl;
    358 
    359 	unsigned int pp_cntl;	/* 0x1c38 */
    360 	unsigned int rb3d_cntl;
    361 	unsigned int rb3d_coloroffset;
    362 	unsigned int re_width_height;
    363 	unsigned int rb3d_colorpitch;
    364 	unsigned int se_cntl;
    365 
    366 	/* Vertex format state */
    367 	unsigned int se_coord_fmt;	/* 0x1c50 */
    368 
    369 	/* Line state */
    370 	unsigned int re_line_pattern;	/* 0x1cd0 */
    371 	unsigned int re_line_state;
    372 
    373 	unsigned int se_line_width;	/* 0x1db8 */
    374 
    375 	/* Bumpmap state */
    376 	unsigned int pp_lum_matrix;	/* 0x1d00 */
    377 
    378 	unsigned int pp_rot_matrix_0;	/* 0x1d58 */
    379 	unsigned int pp_rot_matrix_1;
    380 
    381 	/* Mask state */
    382 	unsigned int rb3d_stencilrefmask;	/* 0x1d7c */
    383 	unsigned int rb3d_ropcntl;
    384 	unsigned int rb3d_planemask;
    385 
    386 	/* Viewport state */
    387 	unsigned int se_vport_xscale;	/* 0x1d98 */
    388 	unsigned int se_vport_xoffset;
    389 	unsigned int se_vport_yscale;
    390 	unsigned int se_vport_yoffset;
    391 	unsigned int se_vport_zscale;
    392 	unsigned int se_vport_zoffset;
    393 
    394 	/* Setup state */
    395 	unsigned int se_cntl_status;	/* 0x2140 */
    396 
    397 	/* Misc state */
    398 	unsigned int re_top_left;	/* 0x26c0 */
    399 	unsigned int re_misc;
    400 } drm_radeon_context_regs_t;
    401 
    402 typedef struct {
    403 	/* Zbias state */
    404 	unsigned int se_zbias_factor;	/* 0x1dac */
    405 	unsigned int se_zbias_constant;
    406 } drm_radeon_context2_regs_t;
    407 
    408 /* Setup registers for each texture unit
    409  */
    410 typedef struct {
    411 	unsigned int pp_txfilter;
    412 	unsigned int pp_txformat;
    413 	unsigned int pp_txoffset;
    414 	unsigned int pp_txcblend;
    415 	unsigned int pp_txablend;
    416 	unsigned int pp_tfactor;
    417 	unsigned int pp_border_color;
    418 } drm_radeon_texture_regs_t;
    419 
    420 typedef struct {
    421 	unsigned int start;
    422 	unsigned int finish;
    423 	unsigned int prim:8;
    424 	unsigned int stateidx:8;
    425 	unsigned int numverts:16;	/* overloaded as offset/64 for elt prims */
    426 	unsigned int vc_format;	/* vertex format */
    427 } drm_radeon_prim_t;
    428 
    429 typedef struct {
    430 	drm_radeon_context_regs_t context;
    431 	drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS];
    432 	drm_radeon_context2_regs_t context2;
    433 	unsigned int dirty;
    434 } drm_radeon_state_t;
    435 
    436 typedef struct {
    437 	/* The channel for communication of state information to the
    438 	 * kernel on firing a vertex buffer with either of the
    439 	 * obsoleted vertex/index ioctls.
    440 	 */
    441 	drm_radeon_context_regs_t context_state;
    442 	drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS];
    443 	unsigned int dirty;
    444 	unsigned int vertsize;
    445 	unsigned int vc_format;
    446 
    447 	/* The current cliprects, or a subset thereof.
    448 	 */
    449 	struct drm_clip_rect boxes[RADEON_NR_SAREA_CLIPRECTS];
    450 	unsigned int nbox;
    451 
    452 	/* Counters for client-side throttling of rendering clients.
    453 	 */
    454 	unsigned int last_frame;
    455 	unsigned int last_dispatch;
    456 	unsigned int last_clear;
    457 
    458 	struct drm_tex_region tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS +
    459 						       1];
    460 	unsigned int tex_age[RADEON_NR_TEX_HEAPS];
    461 	int ctx_owner;
    462 	int pfState;		/* number of 3d windows (0,1,2ormore) */
    463 	int pfCurrentPage;	/* which buffer is being displayed? */
    464 	int crtc2_base;		/* CRTC2 frame offset */
    465 	int tiling_enabled;	/* set by drm, read by 2d + 3d clients */
    466 } drm_radeon_sarea_t;
    467 
    468 /* WARNING: If you change any of these defines, make sure to change the
    469  * defines in the Xserver file (xf86drmRadeon.h)
    470  *
    471  * KW: actually it's illegal to change any of this (backwards compatibility).
    472  */
    473 
    474 /* Radeon specific ioctls
    475  * The device specific ioctl range is 0x40 to 0x79.
    476  */
    477 #define DRM_RADEON_CP_INIT    0x00
    478 #define DRM_RADEON_CP_START   0x01
    479 #define DRM_RADEON_CP_STOP    0x02
    480 #define DRM_RADEON_CP_RESET   0x03
    481 #define DRM_RADEON_CP_IDLE    0x04
    482 #define DRM_RADEON_RESET      0x05
    483 #define DRM_RADEON_FULLSCREEN 0x06
    484 #define DRM_RADEON_SWAP       0x07
    485 #define DRM_RADEON_CLEAR      0x08
    486 #define DRM_RADEON_VERTEX     0x09
    487 #define DRM_RADEON_INDICES    0x0A
    488 #define DRM_RADEON_NOT_USED
    489 #define DRM_RADEON_STIPPLE    0x0C
    490 #define DRM_RADEON_INDIRECT   0x0D
    491 #define DRM_RADEON_TEXTURE    0x0E
    492 #define DRM_RADEON_VERTEX2    0x0F
    493 #define DRM_RADEON_CMDBUF     0x10
    494 #define DRM_RADEON_GETPARAM   0x11
    495 #define DRM_RADEON_FLIP       0x12
    496 #define DRM_RADEON_ALLOC      0x13
    497 #define DRM_RADEON_FREE       0x14
    498 #define DRM_RADEON_INIT_HEAP  0x15
    499 #define DRM_RADEON_IRQ_EMIT   0x16
    500 #define DRM_RADEON_IRQ_WAIT   0x17
    501 #define DRM_RADEON_CP_RESUME  0x18
    502 #define DRM_RADEON_SETPARAM   0x19
    503 #define DRM_RADEON_SURF_ALLOC 0x1a
    504 #define DRM_RADEON_SURF_FREE  0x1b
    505 /* KMS ioctl */
    506 #define DRM_RADEON_GEM_INFO		0x1c
    507 #define DRM_RADEON_GEM_CREATE		0x1d
    508 #define DRM_RADEON_GEM_MMAP		0x1e
    509 #define DRM_RADEON_GEM_PREAD		0x21
    510 #define DRM_RADEON_GEM_PWRITE		0x22
    511 #define DRM_RADEON_GEM_SET_DOMAIN	0x23
    512 #define DRM_RADEON_GEM_WAIT_IDLE	0x24
    513 #define DRM_RADEON_CS			0x26
    514 #define DRM_RADEON_INFO			0x27
    515 #define DRM_RADEON_GEM_SET_TILING	0x28
    516 #define DRM_RADEON_GEM_GET_TILING	0x29
    517 #define DRM_RADEON_GEM_BUSY		0x2a
    518 #define DRM_RADEON_GEM_VA		0x2b
    519 #define DRM_RADEON_GEM_OP		0x2c
    520 #define DRM_RADEON_GEM_USERPTR		0x2d
    521 
    522 #define DRM_IOCTL_RADEON_CP_INIT    DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
    523 #define DRM_IOCTL_RADEON_CP_START   DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_CP_START)
    524 #define DRM_IOCTL_RADEON_CP_STOP    DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t)
    525 #define DRM_IOCTL_RADEON_CP_RESET   DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_CP_RESET)
    526 #define DRM_IOCTL_RADEON_CP_IDLE    DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE)
    527 #define DRM_IOCTL_RADEON_RESET      DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_RESET)
    528 #define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t)
    529 #define DRM_IOCTL_RADEON_SWAP       DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_SWAP)
    530 #define DRM_IOCTL_RADEON_CLEAR      DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t)
    531 #define DRM_IOCTL_RADEON_VERTEX     DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t)
    532 #define DRM_IOCTL_RADEON_INDICES    DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t)
    533 #define DRM_IOCTL_RADEON_STIPPLE    DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t)
    534 #define DRM_IOCTL_RADEON_INDIRECT   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t)
    535 #define DRM_IOCTL_RADEON_TEXTURE    DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t)
    536 #define DRM_IOCTL_RADEON_VERTEX2    DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t)
    537 #define DRM_IOCTL_RADEON_CMDBUF     DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t)
    538 #define DRM_IOCTL_RADEON_GETPARAM   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t)
    539 #define DRM_IOCTL_RADEON_FLIP       DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_FLIP)
    540 #define DRM_IOCTL_RADEON_ALLOC      DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t)
    541 #define DRM_IOCTL_RADEON_FREE       DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t)
    542 #define DRM_IOCTL_RADEON_INIT_HEAP  DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t)
    543 #define DRM_IOCTL_RADEON_IRQ_EMIT   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t)
    544 #define DRM_IOCTL_RADEON_IRQ_WAIT   DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t)
    545 #define DRM_IOCTL_RADEON_CP_RESUME  DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME)
    546 #define DRM_IOCTL_RADEON_SETPARAM   DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t)
    547 #define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t)
    548 #define DRM_IOCTL_RADEON_SURF_FREE  DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t)
    549 /* KMS */
    550 #define DRM_IOCTL_RADEON_GEM_INFO	DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_INFO, struct drm_radeon_gem_info)
    551 #define DRM_IOCTL_RADEON_GEM_CREATE	DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_CREATE, struct drm_radeon_gem_create)
    552 #define DRM_IOCTL_RADEON_GEM_MMAP	DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_MMAP, struct drm_radeon_gem_mmap)
    553 #define DRM_IOCTL_RADEON_GEM_PREAD	DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PREAD, struct drm_radeon_gem_pread)
    554 #define DRM_IOCTL_RADEON_GEM_PWRITE	DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PWRITE, struct drm_radeon_gem_pwrite)
    555 #define DRM_IOCTL_RADEON_GEM_SET_DOMAIN	DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, struct drm_radeon_gem_set_domain)
    556 #define DRM_IOCTL_RADEON_GEM_WAIT_IDLE	DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_IDLE, struct drm_radeon_gem_wait_idle)
    557 #define DRM_IOCTL_RADEON_CS		DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs)
    558 #define DRM_IOCTL_RADEON_INFO		DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INFO, struct drm_radeon_info)
    559 #define DRM_IOCTL_RADEON_GEM_SET_TILING	DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_TILING, struct drm_radeon_gem_set_tiling)
    560 #define DRM_IOCTL_RADEON_GEM_GET_TILING	DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling)
    561 #define DRM_IOCTL_RADEON_GEM_BUSY	DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy)
    562 #define DRM_IOCTL_RADEON_GEM_VA		DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_VA, struct drm_radeon_gem_va)
    563 #define DRM_IOCTL_RADEON_GEM_OP		DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_OP, struct drm_radeon_gem_op)
    564 #define DRM_IOCTL_RADEON_GEM_USERPTR	DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_USERPTR, struct drm_radeon_gem_userptr)
    565 
    566 typedef struct drm_radeon_init {
    567 	enum {
    568 		RADEON_INIT_CP = 0x01,
    569 		RADEON_CLEANUP_CP = 0x02,
    570 		RADEON_INIT_R200_CP = 0x03,
    571 		RADEON_INIT_R300_CP = 0x04,
    572 		RADEON_INIT_R600_CP = 0x05
    573 	} func;
    574 	unsigned long sarea_priv_offset;
    575 	int is_pci;
    576 	int cp_mode;
    577 	int gart_size;
    578 	int ring_size;
    579 	int usec_timeout;
    580 
    581 	unsigned int fb_bpp;
    582 	unsigned int front_offset, front_pitch;
    583 	unsigned int back_offset, back_pitch;
    584 	unsigned int depth_bpp;
    585 	unsigned int depth_offset, depth_pitch;
    586 
    587 	unsigned long fb_offset;
    588 	unsigned long mmio_offset;
    589 	unsigned long ring_offset;
    590 	unsigned long ring_rptr_offset;
    591 	unsigned long buffers_offset;
    592 	unsigned long gart_textures_offset;
    593 } drm_radeon_init_t;
    594 
    595 typedef struct drm_radeon_cp_stop {
    596 	int flush;
    597 	int idle;
    598 } drm_radeon_cp_stop_t;
    599 
    600 typedef struct drm_radeon_fullscreen {
    601 	enum {
    602 		RADEON_INIT_FULLSCREEN = 0x01,
    603 		RADEON_CLEANUP_FULLSCREEN = 0x02
    604 	} func;
    605 } drm_radeon_fullscreen_t;
    606 
    607 #define CLEAR_X1	0
    608 #define CLEAR_Y1	1
    609 #define CLEAR_X2	2
    610 #define CLEAR_Y2	3
    611 #define CLEAR_DEPTH	4
    612 
    613 typedef union drm_radeon_clear_rect {
    614 	float f[5];
    615 	unsigned int ui[5];
    616 } drm_radeon_clear_rect_t;
    617 
    618 typedef struct drm_radeon_clear {
    619 	unsigned int flags;
    620 	unsigned int clear_color;
    621 	unsigned int clear_depth;
    622 	unsigned int color_mask;
    623 	unsigned int depth_mask;	/* misnamed field:  should be stencil */
    624 	drm_radeon_clear_rect_t __user *depth_boxes;
    625 } drm_radeon_clear_t;
    626 
    627 typedef struct drm_radeon_vertex {
    628 	int prim;
    629 	int idx;		/* Index of vertex buffer */
    630 	int count;		/* Number of vertices in buffer */
    631 	int discard;		/* Client finished with buffer? */
    632 } drm_radeon_vertex_t;
    633 
    634 typedef struct drm_radeon_indices {
    635 	int prim;
    636 	int idx;
    637 	int start;
    638 	int end;
    639 	int discard;		/* Client finished with buffer? */
    640 } drm_radeon_indices_t;
    641 
    642 /* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices
    643  *      - allows multiple primitives and state changes in a single ioctl
    644  *      - supports driver change to emit native primitives
    645  */
    646 typedef struct drm_radeon_vertex2 {
    647 	int idx;		/* Index of vertex buffer */
    648 	int discard;		/* Client finished with buffer? */
    649 	int nr_states;
    650 	drm_radeon_state_t __user *state;
    651 	int nr_prims;
    652 	drm_radeon_prim_t __user *prim;
    653 } drm_radeon_vertex2_t;
    654 
    655 /* v1.3 - obsoletes drm_radeon_vertex2
    656  *      - allows arbitrarily large cliprect list
    657  *      - allows updating of tcl packet, vector and scalar state
    658  *      - allows memory-efficient description of state updates
    659  *      - allows state to be emitted without a primitive
    660  *           (for clears, ctx switches)
    661  *      - allows more than one dma buffer to be referenced per ioctl
    662  *      - supports tcl driver
    663  *      - may be extended in future versions with new cmd types, packets
    664  */
    665 typedef struct drm_radeon_cmd_buffer {
    666 	int bufsz;
    667 	char __user *buf;
    668 	int nbox;
    669 	struct drm_clip_rect __user *boxes;
    670 } drm_radeon_cmd_buffer_t;
    671 
    672 typedef struct drm_radeon_tex_image {
    673 	unsigned int x, y;	/* Blit coordinates */
    674 	unsigned int width, height;
    675 	const void __user *data;
    676 } drm_radeon_tex_image_t;
    677 
    678 typedef struct drm_radeon_texture {
    679 	unsigned int offset;
    680 	int pitch;
    681 	int format;
    682 	int width;		/* Texture image coordinates */
    683 	int height;
    684 	drm_radeon_tex_image_t __user *image;
    685 } drm_radeon_texture_t;
    686 
    687 typedef struct drm_radeon_stipple {
    688 	unsigned int __user *mask;
    689 } drm_radeon_stipple_t;
    690 
    691 typedef struct drm_radeon_indirect {
    692 	int idx;
    693 	int start;
    694 	int end;
    695 	int discard;
    696 } drm_radeon_indirect_t;
    697 
    698 /* enum for card type parameters */
    699 #define RADEON_CARD_PCI 0
    700 #define RADEON_CARD_AGP 1
    701 #define RADEON_CARD_PCIE 2
    702 
    703 /* 1.3: An ioctl to get parameters that aren't available to the 3d
    704  * client any other way.
    705  */
    706 #define RADEON_PARAM_GART_BUFFER_OFFSET    1	/* card offset of 1st GART buffer */
    707 #define RADEON_PARAM_LAST_FRAME            2
    708 #define RADEON_PARAM_LAST_DISPATCH         3
    709 #define RADEON_PARAM_LAST_CLEAR            4
    710 /* Added with DRM version 1.6. */
    711 #define RADEON_PARAM_IRQ_NR                5
    712 #define RADEON_PARAM_GART_BASE             6	/* card offset of GART base */
    713 /* Added with DRM version 1.8. */
    714 #define RADEON_PARAM_REGISTER_HANDLE       7	/* for drmMap() */
    715 #define RADEON_PARAM_STATUS_HANDLE         8
    716 #define RADEON_PARAM_SAREA_HANDLE          9
    717 #define RADEON_PARAM_GART_TEX_HANDLE       10
    718 #define RADEON_PARAM_SCRATCH_OFFSET        11
    719 #define RADEON_PARAM_CARD_TYPE             12
    720 #define RADEON_PARAM_VBLANK_CRTC           13   /* VBLANK CRTC */
    721 #define RADEON_PARAM_FB_LOCATION           14   /* FB location */
    722 #define RADEON_PARAM_NUM_GB_PIPES          15   /* num GB pipes */
    723 #define RADEON_PARAM_DEVICE_ID             16
    724 #define RADEON_PARAM_NUM_Z_PIPES           17   /* num Z pipes */
    725 
    726 typedef struct drm_radeon_getparam {
    727 	int param;
    728 	void __user *value;
    729 } drm_radeon_getparam_t;
    730 
    731 /* 1.6: Set up a memory manager for regions of shared memory:
    732  */
    733 #define RADEON_MEM_REGION_GART 1
    734 #define RADEON_MEM_REGION_FB   2
    735 
    736 typedef struct drm_radeon_mem_alloc {
    737 	int region;
    738 	int alignment;
    739 	int size;
    740 	int __user *region_offset;	/* offset from start of fb or GART */
    741 } drm_radeon_mem_alloc_t;
    742 
    743 typedef struct drm_radeon_mem_free {
    744 	int region;
    745 	int region_offset;
    746 } drm_radeon_mem_free_t;
    747 
    748 typedef struct drm_radeon_mem_init_heap {
    749 	int region;
    750 	int size;
    751 	int start;
    752 } drm_radeon_mem_init_heap_t;
    753 
    754 /* 1.6: Userspace can request & wait on irq's:
    755  */
    756 typedef struct drm_radeon_irq_emit {
    757 	int __user *irq_seq;
    758 } drm_radeon_irq_emit_t;
    759 
    760 typedef struct drm_radeon_irq_wait {
    761 	int irq_seq;
    762 } drm_radeon_irq_wait_t;
    763 
    764 /* 1.10: Clients tell the DRM where they think the framebuffer is located in
    765  * the card's address space, via a new generic ioctl to set parameters
    766  */
    767 
    768 typedef struct drm_radeon_setparam {
    769 	unsigned int param;
    770 	__s64 value;
    771 } drm_radeon_setparam_t;
    772 
    773 #define RADEON_SETPARAM_FB_LOCATION    1	/* determined framebuffer location */
    774 #define RADEON_SETPARAM_SWITCH_TILING  2	/* enable/disable color tiling */
    775 #define RADEON_SETPARAM_PCIGART_LOCATION 3	/* PCI Gart Location */
    776 #define RADEON_SETPARAM_NEW_MEMMAP 4		/* Use new memory map */
    777 #define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5    /* PCI GART Table Size */
    778 #define RADEON_SETPARAM_VBLANK_CRTC 6           /* VBLANK CRTC */
    779 /* 1.14: Clients can allocate/free a surface
    780  */
    781 typedef struct drm_radeon_surface_alloc {
    782 	unsigned int address;
    783 	unsigned int size;
    784 	unsigned int flags;
    785 } drm_radeon_surface_alloc_t;
    786 
    787 typedef struct drm_radeon_surface_free {
    788 	unsigned int address;
    789 } drm_radeon_surface_free_t;
    790 
    791 #define	DRM_RADEON_VBLANK_CRTC1		1
    792 #define	DRM_RADEON_VBLANK_CRTC2		2
    793 
    794 /*
    795  * Kernel modesetting world below.
    796  */
    797 #define RADEON_GEM_DOMAIN_CPU		0x1
    798 #define RADEON_GEM_DOMAIN_GTT		0x2
    799 #define RADEON_GEM_DOMAIN_VRAM		0x4
    800 
    801 struct drm_radeon_gem_info {
    802 	__u64	gart_size;
    803 	__u64	vram_size;
    804 	__u64	vram_visible;
    805 };
    806 
    807 #define RADEON_GEM_NO_BACKING_STORE	(1 << 0)
    808 #define RADEON_GEM_GTT_UC		(1 << 1)
    809 #define RADEON_GEM_GTT_WC		(1 << 2)
    810 /* BO is expected to be accessed by the CPU */
    811 #define RADEON_GEM_CPU_ACCESS		(1 << 3)
    812 /* CPU access is not expected to work for this BO */
    813 #define RADEON_GEM_NO_CPU_ACCESS	(1 << 4)
    814 
    815 struct drm_radeon_gem_create {
    816 	__u64	size;
    817 	__u64	alignment;
    818 	__u32	handle;
    819 	__u32	initial_domain;
    820 	__u32	flags;
    821 };
    822 
    823 /*
    824  * This is not a reliable API and you should expect it to fail for any
    825  * number of reasons and have fallback path that do not use userptr to
    826  * perform any operation.
    827  */
    828 #define RADEON_GEM_USERPTR_READONLY	(1 << 0)
    829 #define RADEON_GEM_USERPTR_ANONONLY	(1 << 1)
    830 #define RADEON_GEM_USERPTR_VALIDATE	(1 << 2)
    831 #define RADEON_GEM_USERPTR_REGISTER	(1 << 3)
    832 
    833 struct drm_radeon_gem_userptr {
    834 	__u64		addr;
    835 	__u64		size;
    836 	__u32		flags;
    837 	__u32		handle;
    838 };
    839 
    840 #define RADEON_TILING_MACRO				0x1
    841 #define RADEON_TILING_MICRO				0x2
    842 #define RADEON_TILING_SWAP_16BIT			0x4
    843 #define RADEON_TILING_SWAP_32BIT			0x8
    844 /* this object requires a surface when mapped - i.e. front buffer */
    845 #define RADEON_TILING_SURFACE				0x10
    846 #define RADEON_TILING_MICRO_SQUARE			0x20
    847 #define RADEON_TILING_EG_BANKW_SHIFT			8
    848 #define RADEON_TILING_EG_BANKW_MASK			0xf
    849 #define RADEON_TILING_EG_BANKH_SHIFT			12
    850 #define RADEON_TILING_EG_BANKH_MASK			0xf
    851 #define RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT	16
    852 #define RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK		0xf
    853 #define RADEON_TILING_EG_TILE_SPLIT_SHIFT		24
    854 #define RADEON_TILING_EG_TILE_SPLIT_MASK		0xf
    855 #define RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT	28
    856 #define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK	0xf
    857 
    858 struct drm_radeon_gem_set_tiling {
    859 	__u32	handle;
    860 	__u32	tiling_flags;
    861 	__u32	pitch;
    862 };
    863 
    864 struct drm_radeon_gem_get_tiling {
    865 	__u32	handle;
    866 	__u32	tiling_flags;
    867 	__u32	pitch;
    868 };
    869 
    870 struct drm_radeon_gem_mmap {
    871 	__u32	handle;
    872 	__u32	pad;
    873 	__u64	offset;
    874 	__u64	size;
    875 	__u64	addr_ptr;
    876 };
    877 
    878 struct drm_radeon_gem_set_domain {
    879 	__u32	handle;
    880 	__u32	read_domains;
    881 	__u32	write_domain;
    882 };
    883 
    884 struct drm_radeon_gem_wait_idle {
    885 	__u32	handle;
    886 	__u32	pad;
    887 };
    888 
    889 struct drm_radeon_gem_busy {
    890 	__u32	handle;
    891 	__u32        domain;
    892 };
    893 
    894 struct drm_radeon_gem_pread {
    895 	/** Handle for the object being read. */
    896 	__u32 handle;
    897 	__u32 pad;
    898 	/** Offset into the object to read from */
    899 	__u64 offset;
    900 	/** Length of data to read */
    901 	__u64 size;
    902 	/** Pointer to write the data into. */
    903 	/* void *, but pointers are not 32/64 compatible */
    904 	__u64 data_ptr;
    905 };
    906 
    907 struct drm_radeon_gem_pwrite {
    908 	/** Handle for the object being written to. */
    909 	__u32 handle;
    910 	__u32 pad;
    911 	/** Offset into the object to write to */
    912 	__u64 offset;
    913 	/** Length of data to write */
    914 	__u64 size;
    915 	/** Pointer to read the data from. */
    916 	/* void *, but pointers are not 32/64 compatible */
    917 	__u64 data_ptr;
    918 };
    919 
    920 /* Sets or returns a value associated with a buffer. */
    921 struct drm_radeon_gem_op {
    922 	__u32	handle; /* buffer */
    923 	__u32	op;     /* RADEON_GEM_OP_* */
    924 	__u64	value;  /* input or return value */
    925 };
    926 
    927 #define RADEON_GEM_OP_GET_INITIAL_DOMAIN	0
    928 #define RADEON_GEM_OP_SET_INITIAL_DOMAIN	1
    929 
    930 #define RADEON_VA_MAP			1
    931 #define RADEON_VA_UNMAP			2
    932 
    933 #define RADEON_VA_RESULT_OK		0
    934 #define RADEON_VA_RESULT_ERROR		1
    935 #define RADEON_VA_RESULT_VA_EXIST	2
    936 
    937 #define RADEON_VM_PAGE_VALID		(1 << 0)
    938 #define RADEON_VM_PAGE_READABLE		(1 << 1)
    939 #define RADEON_VM_PAGE_WRITEABLE	(1 << 2)
    940 #define RADEON_VM_PAGE_SYSTEM		(1 << 3)
    941 #define RADEON_VM_PAGE_SNOOPED		(1 << 4)
    942 
    943 struct drm_radeon_gem_va {
    944 	__u32		handle;
    945 	__u32		operation;
    946 	__u32		vm_id;
    947 	__u32		flags;
    948 	__u64		offset;
    949 };
    950 
    951 #define RADEON_CHUNK_ID_RELOCS	0x01
    952 #define RADEON_CHUNK_ID_IB	0x02
    953 #define RADEON_CHUNK_ID_FLAGS	0x03
    954 #define RADEON_CHUNK_ID_CONST_IB	0x04
    955 
    956 /* The first dword of RADEON_CHUNK_ID_FLAGS is a uint32 of these flags: */
    957 #define RADEON_CS_KEEP_TILING_FLAGS 0x01
    958 #define RADEON_CS_USE_VM            0x02
    959 #define RADEON_CS_END_OF_FRAME      0x04 /* a hint from userspace which CS is the last one */
    960 /* The second dword of RADEON_CHUNK_ID_FLAGS is a uint32 that sets the ring type */
    961 #define RADEON_CS_RING_GFX          0
    962 #define RADEON_CS_RING_COMPUTE      1
    963 #define RADEON_CS_RING_DMA          2
    964 #define RADEON_CS_RING_UVD          3
    965 #define RADEON_CS_RING_VCE          4
    966 /* The third dword of RADEON_CHUNK_ID_FLAGS is a sint32 that sets the priority */
    967 /* 0 = normal, + = higher priority, - = lower priority */
    968 
    969 struct drm_radeon_cs_chunk {
    970 	__u32		chunk_id;
    971 	__u32		length_dw;
    972 	__u64		chunk_data;
    973 };
    974 
    975 /* drm_radeon_cs_reloc.flags */
    976 #define RADEON_RELOC_PRIO_MASK		(0xf << 0)
    977 
    978 struct drm_radeon_cs_reloc {
    979 	__u32		handle;
    980 	__u32		read_domains;
    981 	__u32		write_domain;
    982 	__u32		flags;
    983 };
    984 
    985 struct drm_radeon_cs {
    986 	__u32		num_chunks;
    987 	__u32		cs_id;
    988 	/* this points to __u64 * which point to cs chunks */
    989 	__u64		chunks;
    990 	/* updates to the limits after this CS ioctl */
    991 	__u64		gart_limit;
    992 	__u64		vram_limit;
    993 };
    994 
    995 #define RADEON_INFO_DEVICE_ID		0x00
    996 #define RADEON_INFO_NUM_GB_PIPES	0x01
    997 #define RADEON_INFO_NUM_Z_PIPES 	0x02
    998 #define RADEON_INFO_ACCEL_WORKING	0x03
    999 #define RADEON_INFO_CRTC_FROM_ID	0x04
   1000 #define RADEON_INFO_ACCEL_WORKING2	0x05
   1001 #define RADEON_INFO_TILING_CONFIG	0x06
   1002 #define RADEON_INFO_WANT_HYPERZ		0x07
   1003 #define RADEON_INFO_WANT_CMASK		0x08 /* get access to CMASK on r300 */
   1004 #define RADEON_INFO_CLOCK_CRYSTAL_FREQ	0x09 /* clock crystal frequency */
   1005 #define RADEON_INFO_NUM_BACKENDS	0x0a /* DB/backends for r600+ - need for OQ */
   1006 #define RADEON_INFO_NUM_TILE_PIPES	0x0b /* tile pipes for r600+ */
   1007 #define RADEON_INFO_FUSION_GART_WORKING	0x0c /* fusion writes to GTT were broken before this */
   1008 #define RADEON_INFO_BACKEND_MAP		0x0d /* pipe to backend map, needed by mesa */
   1009 /* virtual address start, va < start are reserved by the kernel */
   1010 #define RADEON_INFO_VA_START		0x0e
   1011 /* maximum size of ib using the virtual memory cs */
   1012 #define RADEON_INFO_IB_VM_MAX_SIZE	0x0f
   1013 /* max pipes - needed for compute shaders */
   1014 #define RADEON_INFO_MAX_PIPES		0x10
   1015 /* timestamp for GL_ARB_timer_query (OpenGL), returns the current GPU clock */
   1016 #define RADEON_INFO_TIMESTAMP		0x11
   1017 /* max shader engines (SE) - needed for geometry shaders, etc. */
   1018 #define RADEON_INFO_MAX_SE		0x12
   1019 /* max SH per SE */
   1020 #define RADEON_INFO_MAX_SH_PER_SE	0x13
   1021 /* fast fb access is enabled */
   1022 #define RADEON_INFO_FASTFB_WORKING	0x14
   1023 /* query if a RADEON_CS_RING_* submission is supported */
   1024 #define RADEON_INFO_RING_WORKING	0x15
   1025 /* SI tile mode array */
   1026 #define RADEON_INFO_SI_TILE_MODE_ARRAY	0x16
   1027 /* query if CP DMA is supported on the compute ring */
   1028 #define RADEON_INFO_SI_CP_DMA_COMPUTE	0x17
   1029 /* CIK macrotile mode array */
   1030 #define RADEON_INFO_CIK_MACROTILE_MODE_ARRAY	0x18
   1031 /* query the number of render backends */
   1032 #define RADEON_INFO_SI_BACKEND_ENABLED_MASK	0x19
   1033 /* max engine clock - needed for OpenCL */
   1034 #define RADEON_INFO_MAX_SCLK		0x1a
   1035 /* version of VCE firmware */
   1036 #define RADEON_INFO_VCE_FW_VERSION	0x1b
   1037 /* version of VCE feedback */
   1038 #define RADEON_INFO_VCE_FB_VERSION	0x1c
   1039 #define RADEON_INFO_NUM_BYTES_MOVED	0x1d
   1040 #define RADEON_INFO_VRAM_USAGE		0x1e
   1041 #define RADEON_INFO_GTT_USAGE		0x1f
   1042 #define RADEON_INFO_ACTIVE_CU_COUNT	0x20
   1043 #define RADEON_INFO_CURRENT_GPU_TEMP	0x21
   1044 #define RADEON_INFO_CURRENT_GPU_SCLK	0x22
   1045 #define RADEON_INFO_CURRENT_GPU_MCLK	0x23
   1046 #define RADEON_INFO_READ_REG		0x24
   1047 #define RADEON_INFO_VA_UNMAP_WORKING	0x25
   1048 #define RADEON_INFO_GPU_RESET_COUNTER	0x26
   1049 
   1050 struct drm_radeon_info {
   1051 	__u32		request;
   1052 	__u32		pad;
   1053 	__u64		value;
   1054 };
   1055 
   1056 /* Those correspond to the tile index to use, this is to explicitly state
   1057  * the API that is implicitly defined by the tile mode array.
   1058  */
   1059 #define SI_TILE_MODE_COLOR_LINEAR_ALIGNED	8
   1060 #define SI_TILE_MODE_COLOR_1D			13
   1061 #define SI_TILE_MODE_COLOR_1D_SCANOUT		9
   1062 #define SI_TILE_MODE_COLOR_2D_8BPP		14
   1063 #define SI_TILE_MODE_COLOR_2D_16BPP		15
   1064 #define SI_TILE_MODE_COLOR_2D_32BPP		16
   1065 #define SI_TILE_MODE_COLOR_2D_64BPP		17
   1066 #define SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP	11
   1067 #define SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP	12
   1068 #define SI_TILE_MODE_DEPTH_STENCIL_1D		4
   1069 #define SI_TILE_MODE_DEPTH_STENCIL_2D		0
   1070 #define SI_TILE_MODE_DEPTH_STENCIL_2D_2AA	3
   1071 #define SI_TILE_MODE_DEPTH_STENCIL_2D_4AA	3
   1072 #define SI_TILE_MODE_DEPTH_STENCIL_2D_8AA	2
   1073 
   1074 #define CIK_TILE_MODE_DEPTH_STENCIL_1D		5
   1075 
   1076 #if defined(__cplusplus)
   1077 }
   1078 #endif
   1079 
   1080 #endif
   1081