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Searched
defs:REGVAL
(Results
1 - 19
of
19
) sorted by relevancy
/src/sys/arch/alpha/tlsb/
kftxxreg.h
49
#define
REGVAL
(r) (*(volatile int32_t *)ALPHA_PHYS_TO_K0SEG(r))
/src/sys/arch/alpha/pci/
irongate_pci.c
61
#define
REGVAL
(r) (*(volatile uint32_t *)ALPHA_PHYS_TO_K0SEG(r))
106
REGVAL
(PCI_CONF_ADDR) = (CONFADDR_ENABLE | tag | (offset & 0xff));
108
data =
REGVAL
(PCI_CONF_DATA);
110
REGVAL
(PCI_CONF_ADDR) = 0;
126
REGVAL
(PCI_CONF_ADDR) = (CONFADDR_ENABLE | tag | (offset & 0xff));
128
REGVAL
(PCI_CONF_DATA) = data;
130
REGVAL
(PCI_CONF_ADDR) = 0;
lcareg.h
34
#define
REGVAL
(r) (*(volatile int32_t *)ALPHA_PHYS_TO_K0SEG(r))
ciareg.h
36
#define
REGVAL
(r) (*(volatile int32_t *)ALPHA_PHYS_TO_K0SEG(r))
dwlpxreg.h
45
#define
REGVAL
(r) (*(volatile int32_t *)ALPHA_PHYS_TO_K0SEG(r))
apecsreg.h
37
#define
REGVAL
(r) (*(volatile int32_t *)ALPHA_PHYS_TO_K0SEG(r))
ttwogareg.h
47
#define
REGVAL
(r) (*(volatile uint64_t *) \
178
#define _T2GA(b, r)
REGVAL
((T2_CBUS_TTWOGA_BASE + (T2_SIZE * (b))) + (r))
mcpciareg.h
39
#define
REGVAL
(r) (*(volatile int32_t *)ALPHA_PHYS_TO_K0SEG(r))
/src/sys/arch/mips/alchemy/dev/
aurtc.c
87
#define
REGVAL
(x) (*(volatile uint32_t *)(MIPS_PHYS_TO_KSEG1(PC_BASE + (x))))
88
#define GETREG(x) (
REGVAL
(x))
89
#define PUTREG(x,v) (
REGVAL
(x) = (v))
/src/sys/arch/alpha/jensenio/
jensenioreg.h
36
#define
REGVAL
(r) (*(volatile uint64_t *)ALPHA_PHYS_TO_K0SEG(r))
/src/sys/arch/evbmips/malta/
machdep.c
125
#define
REGVAL
(x) *((volatile u_int32_t *)(MIPS_PHYS_TO_KSEG1((x))))
363
REGVAL
(MALTA_SOFTRES) = MALTA_GORESET;
/src/sys/arch/mips/alchemy/
au_icu.c
88
#define
REGVAL
(x) *((volatile uint32_t *)(MIPS_PHYS_TO_KSEG1((x))))
170
REGVAL
(ic0_base + IC_MASK_CLEAR) = 0xffffffff;
171
REGVAL
(ic0_base + IC_WAKEUP_CLEAR) = 0xffffffff;
172
REGVAL
(ic0_base + IC_SOURCE_SET) = 0xffffffff;
173
REGVAL
(ic0_base + IC_RISING_EDGE) = 0xffffffff;
174
REGVAL
(ic0_base + IC_FALLING_EDGE) = 0xffffffff;
175
REGVAL
(ic0_base + IC_TEST_BIT) = 0;
177
REGVAL
(ic1_base + IC_MASK_CLEAR) = 0xffffffff;
178
REGVAL
(ic1_base + IC_WAKEUP_CLEAR) = 0xffffffff;
179
REGVAL
(ic1_base + IC_SOURCE_SET) = 0xffffffff
[
all
...]
/src/sys/arch/mips/atheros/
ar_intr.c
58
#define
REGVAL
(x) *((volatile uint32_t *)(MIPS_PHYS_TO_KSEG1((x))))
86
return
REGVAL
(platformsw->apsw_misc_intstat);
92
REGVAL
(platformsw->apsw_misc_intstat) = v;
98
return
REGVAL
(platformsw->apsw_misc_intmask);
104
REGVAL
(platformsw->apsw_misc_intmask) = v;
ar5315.c
83
#define
REGVAL
(x) *((volatile uint32_t *)(MIPS_PHYS_TO_KSEG1((x))))
84
#define GETSYSREG(x)
REGVAL
((x) + AR5315_SYSREG_BASE)
85
#define PUTSYSREG(x,v) (
REGVAL
((x) + AR5315_SYSREG_BASE)) = (v)
86
#define GETPCIREG(x)
REGVAL
((x) + AR5315_PCI_BASE)
87
#define PUTPCIREG(x,v) (
REGVAL
((x) + AR5315_PCI_BASE)) = (v)
88
#define GETSDRAMREG(x)
REGVAL
((x) + AR5315_SDRAMCTL_BASE)
/src/sys/arch/algor/algor/
algor_p4032_intr.c
68
#define
REGVAL
(x) *((volatile u_int32_t *)(MIPS_PHYS_TO_KSEG1((x))))
240
REGVAL
(p4032_irqregs[i].addr) = p4032_irqregs[i].val;
260
REGVAL
(p4032_irqsteer[i].addr) = p4032_irqsteer[i].val;
292
REGVAL
(P4032_IRR0) = IRR0_RTC;
306
irr =
REGVAL
(P4032_IRR0);
322
REGVAL
(P4032_IRR0) = 0;
374
REGVAL
(p4032_irqregs[irqmap->irqreg].addr) =
405
REGVAL
(p4032_irqregs[irqmap->irqreg].addr) =
424
irr[IRQREG_ERROR] =
REGVAL
(p4032_irqregs[IRQREG_ERROR].addr);
442
REGVAL
(p4032_irqregs[IRQREG_ERROR].addr) = irr[IRQREG_ERROR]
[
all
...]
algor_p5064_intr.c
72
#define
REGVAL
(x) *((volatile uint32_t *)(MIPS_PHYS_TO_KSEG1((x))))
319
REGVAL
(p5064_irqregs[i].addr) = p5064_irqregs[i].val;
339
REGVAL
(p5064_irqsteer[i].addr) = p5064_irqsteer[i].val;
378
REGVAL
(P5064_LOCINT) = LOCINT_RTC;
392
irr =
REGVAL
(P5064_LOCINT);
408
REGVAL
(P5064_LOCINT) = 0;
467
REGVAL
(p5064_irqregs[irqmap->irqreg].addr) =
498
REGVAL
(p5064_irqregs[irqmap->irqreg].addr) =
517
irr[IRQREG_PANIC] =
REGVAL
(p5064_irqregs[IRQREG_PANIC].addr);
539
REGVAL
(p5064_irqregs[IRQREG_PANIC].addr) = irr[IRQREG_PANIC]
[
all
...]
/src/sys/arch/mips/atheros/include/
ar5312reg.h
172
#define
REGVAL
(x) *((volatile uint32_t *)(MIPS_PHYS_TO_KSEG1((x))))
173
#define GETSYSREG(x)
REGVAL
((x) + AR5312_SYSREG_BASE)
174
#define PUTSYSREG(x,v) (
REGVAL
((x) + AR5312_SYSREG_BASE)) = (v)
175
#define GETSDRAMREG(x)
REGVAL
((x) + AR5312_SDRAMCTL_BASE)
176
#define PUTSDRAMREG(x,v) (
REGVAL
((x) + AR5312_SDRAMCTL_BASE)) = (v)
ar9344reg.h
346
#define
REGVAL
(x) *((volatile uint32_t *)(MIPS_PHYS_TO_KSEG1((x))))
347
#define GETRESETREG(x)
REGVAL
((x) + ARCHIP_RESET_BASE)
348
#define PUTRESETREG(x,v) (
REGVAL
((x) + ARCHIP_RESET_BASE)) = (v)
349
#define GETPLLREG(x)
REGVAL
((x) + ARCHIP_PLL_BASE)
350
#define PUTPLLREG(x,v) (
REGVAL
((x) + ARCHIP_PLL_BASE)) = (v)
351
#define GETDDRREG(x)
REGVAL
((x) + ARCHIP_DDR_BASE)
352
#define PUTDDRREG(x,v) (
REGVAL
((x) + ARCHIP_DDR_BASE)) = (v)
/src/sys/arch/mips/bonito/
bonitoreg.h
27
#define
REGVAL
(x) *((volatile u_int32_t *)MIPS_PHYS_TO_XKPHYS_UNCACHED(x))
30
#define
REGVAL
(x) *((volatile u_int32_t *) MIPS_PHYS_TO_KSEG1(x))
Completed in 82 milliseconds
Indexes created Tue Sep 23 07:09:52 GMT 2025