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      1 /*	$NetBSD: amlogic,meson-g12a-reset.h,v 1.1.1.2 2026/01/18 05:21:54 skrll Exp $	*/
      2 
      3 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
      4 /*
      5  * Copyright (c) 2019 BayLibre, SAS.
      6  * Author: Jerome Brunet <jbrunet (at) baylibre.com>
      7  *
      8  */
      9 
     10 #ifndef _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H
     11 #define _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H
     12 
     13 /*	RESET0					*/
     14 #define RESET_HIU			0
     15 /*					1	*/
     16 #define RESET_DOS			2
     17 /*					3-4	*/
     18 #define RESET_VIU			5
     19 #define RESET_AFIFO			6
     20 #define RESET_VID_PLL_DIV		7
     21 /*					8-9	*/
     22 #define RESET_VENC			10
     23 #define RESET_ASSIST			11
     24 #define RESET_PCIE_CTRL_A		12
     25 #define RESET_VCBUS			13
     26 #define RESET_PCIE_PHY			14
     27 #define RESET_PCIE_APB			15
     28 #define RESET_GIC			16
     29 #define RESET_CAPB3_DECODE		17
     30 /*					18	*/
     31 #define RESET_HDMITX_CAPB3		19
     32 #define RESET_DVALIN_CAPB3		20
     33 #define RESET_DOS_CAPB3			21
     34 /*					22	*/
     35 #define RESET_CBUS_CAPB3		23
     36 #define RESET_AHB_CNTL			24
     37 #define RESET_AHB_DATA			25
     38 #define RESET_VCBUS_CLK81		26
     39 /*					27-31	*/
     40 /*	RESET1					*/
     41 /*					32	*/
     42 #define RESET_DEMUX			33
     43 #define RESET_USB			34
     44 #define RESET_DDR			35
     45 /*					36	*/
     46 #define RESET_BT656			37
     47 #define RESET_AHB_SRAM			38
     48 /*					39	*/
     49 #define RESET_PARSER			40
     50 /*					41	*/
     51 #define RESET_ISA			42
     52 #define RESET_ETHERNET			43
     53 #define RESET_SD_EMMC_A			44
     54 #define RESET_SD_EMMC_B			45
     55 #define RESET_SD_EMMC_C			46
     56 /*					47	*/
     57 #define RESET_USB_PHY20			48
     58 #define RESET_USB_PHY21			49
     59 /*					50-60	*/
     60 #define RESET_AUDIO_CODEC		61
     61 /*					62-63	*/
     62 /*	RESET2					*/
     63 /*					64	*/
     64 #define RESET_AUDIO			65
     65 #define RESET_HDMITX_PHY		66
     66 /*					67	*/
     67 #define RESET_MIPI_DSI_HOST		68
     68 #define RESET_ALOCKER			69
     69 #define RESET_GE2D			70
     70 #define RESET_PARSER_REG		71
     71 #define RESET_PARSER_FETCH		72
     72 #define RESET_CTL			73
     73 #define RESET_PARSER_TOP		74
     74 /*					75	*/
     75 #define RESET_NNA			76
     76 /*					77	*/
     77 #define RESET_DVALIN			78
     78 #define RESET_HDMITX			79
     79 /*					80-95	*/
     80 /*	RESET3					*/
     81 /*					96-95	*/
     82 #define RESET_DEMUX_TOP			105
     83 #define RESET_DEMUX_DES_PL		106
     84 #define RESET_DEMUX_S2P_0		107
     85 #define RESET_DEMUX_S2P_1		108
     86 #define RESET_DEMUX_0			109
     87 #define RESET_DEMUX_1			110
     88 #define RESET_DEMUX_2			111
     89 /*					112-127	*/
     90 /*	RESET4					*/
     91 /*					128-129	*/
     92 #define RESET_MIPI_DSI_PHY		130
     93 /*					131-132	*/
     94 #define RESET_RDMA			133
     95 #define RESET_VENCI			134
     96 #define RESET_VENCP			135
     97 /*					136	*/
     98 #define RESET_VDAC			137
     99 /*					138-139 */
    100 #define RESET_VDI6			140
    101 #define RESET_VENCL			141
    102 #define RESET_I2C_M1			142
    103 #define RESET_I2C_M2			143
    104 /*					144-159	*/
    105 /*	RESET5					*/
    106 /*					160-191	*/
    107 /*	RESET6					*/
    108 #define RESET_GEN			192
    109 #define RESET_SPICC0			193
    110 #define RESET_SC			194
    111 #define RESET_SANA_3			195
    112 #define RESET_I2C_M0			196
    113 #define RESET_TS_PLL			197
    114 #define RESET_SPICC1			198
    115 #define RESET_STREAM			199
    116 #define RESET_TS_CPU			200
    117 #define RESET_UART0			201
    118 #define RESET_UART1_2			202
    119 #define RESET_ASYNC0			203
    120 #define RESET_ASYNC1			204
    121 #define RESET_SPIFC0			205
    122 #define RESET_I2C_M3			206
    123 /*					207-223	*/
    124 /*	RESET7					*/
    125 #define RESET_USB_DDR_0			224
    126 #define RESET_USB_DDR_1			225
    127 #define RESET_USB_DDR_2			226
    128 #define RESET_USB_DDR_3			227
    129 #define RESET_TS_GPU			228
    130 #define RESET_DEVICE_MMC_ARB		229
    131 #define RESET_DVALIN_DMC_PIPL		230
    132 #define RESET_VID_LOCK			231
    133 #define RESET_NIC_DMC_PIPL		232
    134 #define RESET_DMC_VPU_PIPL		233
    135 #define RESET_GE2D_DMC_PIPL		234
    136 #define RESET_HCODEC_DMC_PIPL		235
    137 #define RESET_WAVE420_DMC_PIPL		236
    138 #define RESET_HEVCF_DMC_PIPL		237
    139 /*					238-255	*/
    140 
    141 #endif
    142