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    Searched defs:RegSize (Results 1 - 17 of 17) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsFrameLowering.cpp 127 unsigned RegSize = TRI.getSpillSize(*TRI.getMinimalPhysRegClass(*R));
128 Size = alignTo(Size + RegSize, RegSize);
MipsCallLowering.cpp 470 unsigned RegSize = 4;
472 VaArgOffset = alignTo(CCInfo.getNextStackOffset(), RegSize);
476 (int)(RegSize * (ArgRegs.size() - Idx));
480 int FI = MFI.CreateFixedObject(RegSize, VaArgOffset, true);
483 for (unsigned I = Idx; I < ArgRegs.size(); ++I, VaArgOffset += RegSize) {
487 MIRBuilder.buildCopy(LLT::scalar(RegSize * 8), Register(ArgRegs[I]));
488 FI = MFI.CreateFixedObject(RegSize, VaArgOffset, true);
493 MPO, MachineMemOperand::MOStore, RegSize, Align(RegSize));
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86TileConfig.cpp 174 unsigned RegSize = TRI->getRegSizeInBits(*MRI.getRegClass(R));
175 if ((IsRow && RegSize == 8) || (!IsRow && RegSize == 16))
X86InstrInfo.cpp 5767 unsigned RegSize = TRI.getRegSizeInBits(*RC);
5772 RegSize > 32) {
5881 RegSize > 64) {
  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
InfoByHwMode.h 149 unsigned RegSize;
157 return std::tie(RegSize, SpillSize, SpillAlignment) ==
158 std::tie(I.RegSize, I.SpillSize, I.SpillAlignment);
RegisterInfoEmitter.cpp 1080 uint32_t RegSize = 0;
1082 RegSize = RC.RSI.getSimple().RegSize;
1087 << ", " << RegSize << ", " << RC.CopyCost << ", "
1289 OS << " { " << RI.RegSize << ", " << RI.SpillSize << ", "
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/AsmPrinter/
DwarfExpression.cpp 138 unsigned RegSize = TRI.getRegSizeInBits(*RC);
144 SmallBitVector Coverage(RegSize, false);
155 SmallBitVector CurSubReg(RegSize, false);
179 if (CurPos < RegSize)
181 -1, RegSize - CurPos, "no DWARF register encoding"));
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
TargetRegisterInfo.h 236 unsigned RegSize, SpillSize, SpillAlignment;
275 return getRegClassInfo(RC).RegSize;
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMFrameLowering.cpp 264 int RegSize;
267 RegSize = 8;
271 RegSize = 4;
284 count += RegSize;
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZInstrInfo.cpp 904 LogicOp(unsigned regSize, unsigned immLSB, unsigned immSize)
905 : RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {}
907 explicit operator bool() const { return RegSize; }
909 unsigned RegSize = 0;
954 Imm |= allOnes(And.RegSize) & ~(allOnes(And.ImmSize) << And.ImmLSB);
956 if (isRxSBGMask(Imm, And.RegSize, Start, End)) {
958 if (And.RegSize == 64) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64FastISel.cpp 1652 unsigned RegSize;
1663 RegSize = 32;
1669 RegSize = 64;
1673 if (!AArch64_AM::isLogicalImmediate(Imm, RegSize))
1678 AArch64_AM::encodeLogicalImmediate(Imm, RegSize));
4022 unsigned RegSize = Is64Bit ? 64 : 32;
4069 unsigned ImmR = RegSize - Shift;
4125 unsigned RegSize = Is64Bit ? 64 : 32;
4173 return materializeInt(ConstantInt::get(*Context, APInt(RegSize, 0)), RetVT);
4241 unsigned RegSize = Is64Bit ? 64 : 32
    [all...]
AArch64FrameLowering.cpp 2802 auto RegSize = TRI->getRegSizeInBits(Reg, MRI) / 8;
2805 SVECSStackSize += RegSize;
2807 CSStackSize += RegSize;
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonISelLowering.cpp 860 unsigned RegSize = RegVT.getSizeInBits();
861 assert(RegSize == 32 || RegSize == 64 ||
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIInstrInfo.cpp 5152 unsigned RegSize = TRI->getRegSizeInBits(Rsrc.getReg(), MRI);
5153 unsigned NumSubRegs = RegSize / 32;
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
LegalizerHelper.cpp 160 unsigned RegSize = RegTy.getSizeInBits();
162 unsigned NumParts = RegSize / MainSize;
163 unsigned LeftoverSize = RegSize - NumParts * MainSize;
189 for (unsigned Offset = MainSize * NumParts; Offset < RegSize;
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
SelectionDAGBuilder.cpp 852 unsigned RegSize = RegisterVT.getScalarSizeInBits();
856 if (NumZeroBits == RegSize) {
869 FromVT = EVT::getIntegerVT(*DAG.getContext(), RegSize - NumZeroBits);
873 EVT::getIntegerVT(*DAG.getContext(), RegSize - NumSignBits + 1);
  /src/sys/external/bsd/acpica/dist/include/
actbl2.h 663 UINT32 RegSize;
710 UINT32 RegSize;
728 UINT32 RegSize;
762 UINT32 RegSize;

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