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      1 /*      $NetBSD: sa11x0_comreg.h,v 1.3 2008/04/28 20:23:14 martin Exp $        */
      2 
      3 /*-
      4  * Copyright (c) 2001, The NetBSD Foundation, Inc.  All rights reserved.
      5  *
      6  * This code is derived from software contributed to The NetBSD Foundation
      7  * by IWAMOTO Toshihiro and Ichiro FUKUHARA.
      8  *
      9  * Redistribution and use in source and binary forms, with or without
     10  * modification, are permitted provided that the following conditions
     11  * are met:
     12  * 1. Redistributions of source code must retain the above copyright
     13  *    notice, this list of conditions and the following disclaimer.
     14  * 2. Redistributions in binary form must reproduce the above copyright
     15  *    notice, this list of conditions and the following disclaimer in the
     16  *    documentation and/or other materials provided with the distribution.
     17  *
     18  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     19  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     20  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     21  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     22  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     28  * POSSIBILITY OF SUCH DAMAGE.
     29  */
     30 
     31 /* SA11[01]0 integrated UART interface */
     32 
     33 /* #define SACOM_BASE	0x80050000 */
     34 
     35 #define SACOM_FREQ	(3686400 / 16)
     36 #define SACOMSPEED(b)	(SACOM_FREQ / (b) - 1)
     37 
     38 /* size of I/O space */
     39 #define SACOM_NPORTS	9
     40 
     41 #define SACOM_TXFIFOLEN		8
     42 #define SACOM_RXFIFOLEN		12
     43 
     44 /* UART control register 0 */
     45 #define SACOM_CR0	0x00
     46 #define CR0_PE		0x01	/* Parity enable */
     47 #define CR0_OES		0x02	/* Odd/even parity select */
     48 #define CR0_SBS		0x04	/* Stop bit select */
     49 #define CR0_DSS		0x08	/* Data size select */
     50 #define CR0_SCE		0x10	/* Sample clock enable */
     51 #define CR0_RCE		0x20	/* Receive clock edge enable */
     52 #define CR0_TCE		0x40	/* Transmit clock edge enable */
     53 
     54 /* UART control register 1 and 2 - baud rate divisor */
     55 #define SACOM_CR1	0x04
     56 #define SACOM_CR2	0x08
     57 
     58 /* UART control register 3 */
     59 #define SACOM_CR3	0x0C
     60 #define CR3_RXE		0x01	/* Receiver enable */
     61 #define CR3_TXE		0x02	/* Transmitter enable */
     62 #define CR3_BRK		0x04	/* Break */
     63 #define CR3_RIE		0x08	/* Receive FIFO interrupt enable */
     64 #define CR3_TIE		0x10	/* Transmit FIFO interrupt enable */
     65 #define CR3_LBM		0x20	/* Loopback mode */
     66 
     67 /* UART data register */
     68 #define SACOM_DR	0x14
     69 #define DR_PRE		0x100	/* Parity error */
     70 #define DR_FRE		0x200	/* Framing error */
     71 #define DR_ROR		0x400	/* Receiver overrun */
     72 
     73 /* UART status register 0 */
     74 #define SACOM_SR0	0x1C
     75 #define SR0_TFS		0x01	/* Transmit FIFO service request */
     76 #define SR0_RFS		0x02	/* Receive FIFO service request */
     77 #define SR0_RID		0x04	/* Receiver idle */
     78 #define SR0_RBB		0x08	/* Receiver begin of break */
     79 #define SR0_REB		0x10	/* Receiver end of break */
     80 #define SR0_EIF		0x20	/* Error in FIFO */
     81 
     82 /* UART status register 1 */
     83 #define SACOM_SR1	0x20
     84 #define SR1_TBY		0x01	/* Transmitter busy */
     85 #define SR1_RNE		0x02	/* Receive FIFO not empty */
     86 #define SR1_TNF		0x04	/* Transmit FIFO not full */
     87 #define SR1_PRE		0x08	/* Parity error */
     88 #define SR1_FRE		0x10	/* Framing error */
     89 #define SR1_ROR		0x20	/* Receive FIFO overrun */
     90