1 /* $NetBSD: sdhcreg.h,v 1.21 2020/07/15 15:57:52 msaitoh Exp $ */ 2 /* $OpenBSD: sdhcreg.h,v 1.4 2006/07/30 17:20:40 fgsch Exp $ */ 3 4 /* 5 * Copyright (c) 2006 Uwe Stuehler <uwe (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _SDHCREG_H_ 21 #define _SDHCREG_H_ 22 23 /* Host standard register set */ 24 #define SDHC_DMA_ADDR 0x00 25 #define SDHC_BLOCK_SIZE 0x04 26 #define SDHC_DMA_BOUNDARY_SHIFT 12 27 #define SDHC_DMA_BOUNDARY_MASK 0x7 28 #define SDHC_BLOCK_COUNT 0x06 29 #define SDHC_BLOCK_COUNT_MAX 512 30 #define SDHC_ARGUMENT 0x08 31 #define SDHC_TRANSFER_MODE 0x0c 32 #define SDHC_TRANSFER_MODE_MASK 0xb7 33 #define SDHC_MULTI_BLOCK_MODE (1<<5) 34 #define SDHC_READ_MODE (1<<4) 35 #define SDHC_AUTO_CMD12_ENABLE (1<<2) 36 #define SDHC_BLOCK_COUNT_ENABLE (1<<1) 37 #define SDHC_DMA_ENABLE (1<<0) 38 #define SDHC_COMMAND 0x0e 39 /* 14-15 reserved */ 40 #define SDHC_COMMAND_INDEX_SHIFT 8 41 #define SDHC_COMMAND_INDEX_MASK 0x3f 42 #define SDHC_COMMAND_TYPE_ABORT (3<<6) 43 #define SDHC_COMMAND_TYPE_RESUME (2<<6) 44 #define SDHC_COMMAND_TYPE_SUSPEND (1<<6) 45 #define SDHC_COMMAND_TYPE_NORMAL (0<<6) 46 #define SDHC_DATA_PRESENT_SELECT (1<<5) 47 #define SDHC_INDEX_CHECK_ENABLE (1<<4) 48 #define SDHC_CRC_CHECK_ENABLE (1<<3) 49 /* 2 reserved */ 50 #define SDHC_RESP_LEN_48_CHK_BUSY (3<<0) 51 #define SDHC_RESP_LEN_48 (2<<0) 52 #define SDHC_RESP_LEN_136 (1<<0) 53 #define SDHC_NO_RESPONSE (0<<0) 54 #define SDHC_RESPONSE 0x10 /* - 0x1f */ 55 #define SDHC_DATA 0x20 56 #define SDHC_PRESENT_STATE 0x24 57 /* 25-31 reserved */ 58 #define SDHC_CMD_LINE_SIGNAL_LEVEL (1<<24) 59 #define SDHC_DAT3_LINE_LEVEL (1<<23) 60 #define SDHC_DAT2_LINE_LEVEL (1<<22) 61 #define SDHC_DAT1_LINE_LEVEL (1<<21) 62 #define SDHC_DAT0_LINE_LEVEL (1<<20) 63 #define SDHC_WRITE_PROTECT_SWITCH (1<<19) 64 #define SDHC_CARD_DETECT_PIN_LEVEL (1<<18) 65 #define SDHC_CARD_STATE_STABLE (1<<17) 66 #define SDHC_CARD_INSERTED (1<<16) 67 /* 12-15 reserved */ 68 #define SDHC_BUFFER_READ_ENABLE (1<<11) 69 #define SDHC_BUFFER_WRITE_ENABLE (1<<10) 70 #define SDHC_READ_TRANSFER_ACTIVE (1<<9) 71 #define SDHC_WRITE_TRANSFER_ACTIVE (1<<8) 72 /* 4-7 reserved */ 73 #define SDHC_SDSTB (1<<3) /* uSDHC */ 74 #define SDHC_DAT_ACTIVE (1<<2) 75 #define SDHC_CMD_INHIBIT_DAT (1<<1) 76 #define SDHC_CMD_INHIBIT_CMD (1<<0) 77 #define SDHC_CMD_INHIBIT_MASK 0x0003 78 #define SDHC_HOST_CTL 0x28 79 #define SDHC_USDHC_BURST_LEN_EN (1<<27) /* uSDHC */ 80 #define SDHC_USDHC_HOST_CTL_RESV23 (1<<23) /* uSDHC */ 81 #define SDHC_USDHC_DMA_SELECT (3<<8) /* uSDHC */ 82 #define SDHC_USDHC_DMA_SELECT_ADMA1 (1<<8) /* uSDHC */ 83 #define SDHC_USDHC_DMA_SELECT_ADMA2 (2<<8) /* uSDHC */ 84 #define SDHC_USDHC_EMODE (3<<4) /* uSDHC */ 85 #define SDHC_USDHC_EMODE_LE (2<<4) /* uSDHC */ 86 #define SDHC_8BIT_MODE (1<<5) 87 #define SDHC_DMA_SELECT (3<<3) 88 #define SDHC_DMA_SELECT_SDMA (0<<3) 89 #define SDHC_DMA_SELECT_ADMA2 (2<<3) 90 #define SDHC_HIGH_SPEED (1<<2) 91 #define SDHC_ESDHC_8BIT_MODE (1<<2) /* eSDHC */ 92 #define SDHC_4BIT_MODE (1<<1) 93 #define SDHC_LED_ON (1<<0) 94 #define SDHC_POWER_CTL 0x29 95 #define SDHC_VOLTAGE_SHIFT 1 96 #define SDHC_VOLTAGE_MASK 0x07 97 #define SDHC_VOLTAGE_3_3V 0x07 98 #define SDHC_VOLTAGE_3_0V 0x06 99 #define SDHC_VOLTAGE_1_8V 0x05 100 #define SDHC_BUS_POWER (1<<0) 101 #define SDHC_BLOCK_GAP_CTL 0x2a 102 #define SDHC_WAKEUP_CTL 0x2b 103 #define SDHC_CLOCK_CTL 0x2c 104 #define SDHC_SDCLK_DIV_SHIFT 8 105 #define SDHC_SDCLK_DIV_MASK 0xff 106 #define SDHC_SDCLK_XDIV_SHIFT 6 107 #define SDHC_SDCLK_XDIV_MASK 0x3 108 #define SDHC_SDCLK_CGM (1<<5) 109 #define SDHC_SDCLK_DVS_SHIFT 4 110 #define SDHC_SDCLK_DVS_MASK 0xf 111 #define SDHC_SDCLK_ENABLE (1<<2) 112 #define SDHC_INTCLK_STABLE (1<<1) 113 #define SDHC_INTCLK_ENABLE (1<<0) 114 #define SDHC_TIMEOUT_CTL 0x2e 115 #define SDHC_TIMEOUT_MAX 0x0e 116 #define SDHC_SOFTWARE_RESET 0x2f 117 #define SDHC_INIT_ACTIVE (1<<3) /* ESDHC */ 118 #define SDHC_RESET_MASK 0x5 119 #define SDHC_RESET_DAT (1<<2) 120 #define SDHC_RESET_CMD (1<<1) 121 #define SDHC_RESET_ALL (1<<0) 122 #define SDHC_NINTR_STATUS 0x30 123 #define SDHC_ERROR_INTERRUPT (1<<15) 124 #define SDHC_RETUNING_EVENT (1<<12) 125 #define SDHC_CARD_INTERRUPT (1<<8) 126 #define SDHC_CARD_REMOVAL (1<<7) 127 #define SDHC_CARD_INSERTION (1<<6) 128 #define SDHC_BUFFER_READ_READY (1<<5) 129 #define SDHC_BUFFER_WRITE_READY (1<<4) 130 #define SDHC_DMA_INTERRUPT (1<<3) 131 #define SDHC_BLOCK_GAP_EVENT (1<<2) 132 #define SDHC_TRANSFER_COMPLETE (1<<1) 133 #define SDHC_COMMAND_COMPLETE (1<<0) 134 #define SDHC_NINTR_STATUS_MASK 0x91ff 135 #define SDHC_EINTR_STATUS 0x32 136 #define SDHC_DMA_ERROR (1<<12) 137 #define SDHC_ADMA_ERROR (1<<9) 138 #define SDHC_AUTO_CMD12_ERROR (1<<8) 139 #define SDHC_CURRENT_LIMIT_ERROR (1<<7) 140 #define SDHC_DATA_END_BIT_ERROR (1<<6) 141 #define SDHC_DATA_CRC_ERROR (1<<5) 142 #define SDHC_DATA_TIMEOUT_ERROR (1<<4) 143 #define SDHC_CMD_INDEX_ERROR (1<<3) 144 #define SDHC_CMD_END_BIT_ERROR (1<<2) 145 #define SDHC_CMD_CRC_ERROR (1<<1) 146 #define SDHC_CMD_TIMEOUT_ERROR (1<<0) 147 #define SDHC_EINTR_STATUS_MASK 0x03ff /* excluding vendor signals */ 148 #define SDHC_NINTR_STATUS_EN 0x34 149 #define SDHC_EINTR_STATUS_EN 0x36 150 #define SDHC_NINTR_SIGNAL_EN 0x38 151 #define SDHC_NINTR_SIGNAL_MASK 0x01ff 152 #define SDHC_EINTR_SIGNAL_EN 0x3a 153 #define SDHC_EINTR_SIGNAL_MASK 0x03ff /* excluding vendor signals */ 154 #define SDHC_CMD12_ERROR_STATUS 0x3c 155 #define SDHC_HOST_CTL2 0x3e 156 #define SDHC_SAMPLING_CLOCK_SEL (1<<7) 157 #define SDHC_EXECUTE_TUNING (1<<6) 158 #define SDHC_1_8V_SIGNAL_EN (1<<3) 159 #define SDHC_UHS_MODE_SELECT_SHIFT 0 160 #define SDHC_UHS_MODE_SELECT_MASK 0x7 161 #define SDHC_UHS_MODE_SELECT_SDR12 0 162 #define SDHC_UHS_MODE_SELECT_SDR25 1 163 #define SDHC_UHS_MODE_SELECT_SDR50 2 164 #define SDHC_UHS_MODE_SELECT_SDR104 3 165 #define SDHC_UHS_MODE_SELECT_DDR50 4 166 #define SDHC_CAPABILITIES 0x40 167 #define SDHC_SHARED_BUS_SLOT (1<<31) 168 #define SDHC_EMBEDDED_SLOT (1<<30) 169 #define SDHC_ASYNC_INTR (1<<29) 170 #define SDHC_64BIT_SYS_BUS (1<<28) 171 #define SDHC_VOLTAGE_SUPP_1_8V (1<<26) 172 #define SDHC_VOLTAGE_SUPP_3_0V (1<<25) 173 #define SDHC_VOLTAGE_SUPP_3_3V (1<<24) 174 #define SDHC_DMA_SUPPORT (1<<22) 175 #define SDHC_HIGH_SPEED_SUPP (1<<21) 176 #define SDHC_ADMA1_SUPP (1<<20) 177 #define SDHC_ADMA2_SUPP (1<<19) 178 #define SDHC_8BIT_SUPP (1<<18) 179 #define SDHC_MAX_BLK_LEN_512 0 180 #define SDHC_MAX_BLK_LEN_1024 1 181 #define SDHC_MAX_BLK_LEN_2048 2 182 #define SDHC_MAX_BLK_LEN_4096 3 183 #define SDHC_MAX_BLK_LEN_SHIFT 16 184 #define SDHC_MAX_BLK_LEN_MASK 0x3 185 #define SDHC_BASE_FREQ_SHIFT 8 186 #define SDHC_BASE_FREQ_MASK 0x3f 187 #define SDHC_BASE_V3_FREQ_MASK 0xff 188 #define SDHC_TIMEOUT_FREQ_UNIT (1<<7) /* 0=KHz, 1=MHz */ 189 #define SDHC_TIMEOUT_FREQ_SHIFT 0 190 #define SDHC_TIMEOUT_FREQ_MASK 0x1f 191 #define SDHC_CAPABILITIES2 0x44 192 #define SDHC_SDR50_SUPP (1<<0) 193 #define SDHC_SDR104_SUPP (1<<1) 194 #define SDHC_DDR50_SUPP (1<<2) 195 #define SDHC_DRIVER_TYPE_A (1<<4) 196 #define SDHC_DRIVER_TYPE_C (1<<5) 197 #define SDHC_DRIVER_TYPE_D (1<<6) 198 #define SDHC_TIMER_COUNT_SHIFT 8 199 #define SDHC_TIMER_COUNT_MASK 0xf 200 #define SDHC_TUNING_SDR50 (1<<13) 201 #define SDHC_RETUNING_MODES_SHIFT 14 202 #define SDHC_RETUNING_MODES_MASK 0x3 203 #define SDHC_RETUNING_MODE_1 (0 << SDHC_RETUNING_MODES_SHIFT) 204 #define SDHC_RETUNING_MODE_2 (1 << SDHC_RETUNING_MODES_SHIFT) 205 #define SDHC_RETUNING_MODE_3 (2 << SDHC_RETUNING_MODES_SHIFT) 206 #define SDHC_CLOCK_MULTIPLIER_SHIFT 16 207 #define SDHC_CLOCK_MULTIPLIER_MASK 0xff 208 #define SDHC_ADMA_ERROR_STATUS 0x54 209 #define SDHC_ADMA_LENGTH_MISMATCH (1<<2) 210 #define SDHC_ADMA_ERROR_STATE (3<<0) 211 #define SDHC_ADMA_SYSTEM_ADDR 0x58 212 #define SDHC_WATERMARK_LEVEL 0x44 /* ESDHC/uSDHC */ 213 #define SDHC_WATERMARK_WR_BRST_SHIFT 24 /* uSDHC */ 214 #define SDHC_WATERMARK_WR_BRST_MASK 0x1f /* uSDHC */ 215 #define SDHC_WATERMARK_WRITE_SHIFT 16 216 #define SDHC_WATERMARK_WRITE_MASK 0xff 217 #define SDHC_WATERMARK_RD_BRST_SHIFT 8 /* uSDHC */ 218 #define SDHC_WATERMARK_RD_BRST_MASK 0x1f /* uSDHC */ 219 #define SDHC_WATERMARK_READ_SHIFT 0 220 #define SDHC_WATERMARK_READ_MASK 0xff 221 #define SDHC_MAX_CAPABILITIES 0x48 222 #define SDHC_SLOT_INTR_STATUS 0xfc 223 #define SDHC_ESDHC_HOST_CTL_VERSION 0xfc /* eSDHC */ 224 #define SDHC_HOST_CTL_VERSION 0xfe 225 #define SDHC_SPEC_VERS_SHIFT 0 226 #define SDHC_SPEC_VERS_MASK 0xff 227 #define SDHC_VENDOR_VERS_SHIFT 8 228 #define SDHC_VENDOR_VERS_MASK 0xff 229 #define SDHC_DMA_CTL 0x40c /* eSDHC */ 230 #define SDHC_DMA_SNOOP 0x40 231 #define SDHC_MIX_CTRL 0x48 /* uSDHC */ 232 #define SDHC_USDHC_NIBBLE_POS (1<<6) 233 #define SDHC_USDHC_DDR_EN (1<<3) 234 #define SDHC_VEND_SPEC 0xc0 /* uSDHC */ 235 #define SDHC_VEND_SPEC_MBO (1<<29) 236 #define SDHC_VEND_SPEC_CARD_CLK_SOFT_EN (1<<14) 237 #define SDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN (1<<13) 238 #define SDHC_VEND_SPEC_HCLK_SOFT_EN (1<<12) 239 #define SDHC_VEND_SPEC_IPG_CLK_SOFT_EN (1<<11) 240 #define SDHC_VEND_SPEC_FRC_SDCLK_ON (1<<8) 241 #define SDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN (1<<3) 242 #define SDHC_VEND_SPEC_VSELECT (1<<1) 243 #define SDHC_MMC_BOOT 0xc4 /* uSDHC */ 244 #define SDHC_VEND_SPEC2 0xc8 /* uSDHC */ 245 246 /* SDHC_SPEC_VERS */ 247 #define SDHC_SPEC_VERS_100 0x00 248 #define SDHC_SPEC_VERS_200 0x01 249 #define SDHC_SPEC_VERS_300 0x02 250 #define SDHC_SPEC_VERS_400 0x03 251 #define SDHC_SPEC_VERS_410 0x04 252 #define SDHC_SPEC_VERS_420 0x05 253 #define SDHC_SPEC_NOVERS 0xff /* dummy */ 254 255 /* SDHC_CAPABILITIES decoding */ 256 #define SDHC_BASE_V3_FREQ_KHZ(cap) \ 257 ((((cap) >> SDHC_BASE_FREQ_SHIFT) & SDHC_BASE_V3_FREQ_MASK) * 1000) 258 #define SDHC_BASE_FREQ_KHZ(cap) \ 259 ((((cap) >> SDHC_BASE_FREQ_SHIFT) & SDHC_BASE_FREQ_MASK) * 1000) 260 #define SDHC_TIMEOUT_FREQ(cap) \ 261 (((cap) >> SDHC_TIMEOUT_FREQ_SHIFT) & SDHC_TIMEOUT_FREQ_MASK) 262 #define SDHC_TIMEOUT_FREQ_KHZ(cap) \ 263 (((cap) & SDHC_TIMEOUT_FREQ_UNIT) ? \ 264 SDHC_TIMEOUT_FREQ(cap) * 1000: \ 265 SDHC_TIMEOUT_FREQ(cap)) 266 267 /* SDHC_HOST_CTL_VERSION decoding */ 268 #define SDHC_SPEC_VERSION(hcv) \ 269 (((hcv) >> SDHC_SPEC_VERS_SHIFT) & SDHC_SPEC_VERS_MASK) 270 #define SDHC_VENDOR_VERSION(hcv) \ 271 (((hcv) >> SDHC_VENDOR_VERS_SHIFT) & SDHC_VENDOR_VERS_MASK) 272 273 #define SDHC_PRESENT_STATE_BITS \ 274 "\20\31CL\30D3L\27D2L\26D1L\25D0L\24WPS\23CD\22CSS\21CI" \ 275 "\14BRE\13BWE\12RTA\11WTA\3DLA\2CID\1CIC" 276 #define SDHC_NINTR_STATUS_BITS \ 277 "\20\20ERROR\11CARD\10REMOVAL\7INSERTION\6READ\5WRITE" \ 278 "\4DMA\3GAP\2XFER\1CMD" 279 #define SDHC_EINTR_STATUS_BITS \ 280 "\20\11ACMD12\10CL\7DEB\6DCRC\5DT\4CI\3CEB\2CCRC\1CT" 281 #define SDHC_CAPABILITIES_BITS \ 282 "\20\33Vdd1.8V\32Vdd3.0V\31Vdd3.3V\30SUSPEND\27DMA\26HIGHSPEED" 283 284 #define SDHC_ADMA2_VALID (1<<0) 285 #define SDHC_ADMA2_END (1<<1) 286 #define SDHC_ADMA2_INT (1<<2) 287 #define SDHC_ADMA2_ACT (3<<4) 288 #define SDHC_ADMA2_ACT_NOP (0<<4) 289 #define SDHC_ADMA2_ACT_TRANS (2<<4) 290 #define SDHC_ADMA2_ACT_LINK (3<<4) 291 292 struct sdhc_adma2_descriptor32 { 293 uint16_t attribute; 294 uint16_t length; 295 uint32_t address; 296 } __packed; 297 298 struct sdhc_adma2_descriptor64 { 299 uint16_t attribute; 300 uint16_t length; 301 uint32_t address; 302 uint32_t address_hi; 303 } __packed; 304 305 #endif /* _SDHCREG_H_ */ 306
Indexes created Sun Sep 21 16:09:51 GMT 2025