1 /* $NetBSD: ausmbus_pscreg.h,v 1.2 2024/06/02 19:51:22 andvar Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Shigeyuki Fukushima. 5 * All rights reserved. 6 * 7 * Written by Shigeyuki Fukushima. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer in the documentation and/or other materials provided 17 * with the distribution. 18 * 3. The name of the author may not be used to endorse or promote 19 * products derived from this software without specific prior 20 * written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS 23 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 26 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 28 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 31 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #ifndef _MIPS_ALCHEMY_AUSMBUS_PSCREG_H_ 36 #define _MIPS_ALCHEMY_AUSMBUS_PSCREG_H_ 37 38 /* 39 * psc_smbcfg: SMBus Configuration Register 40 * RT: Rx FIFO Threshold 41 * TT: Tx FIFO Threshold 42 * DD: Disable DMA Transfers 43 * DE: Device Enable 44 * DIV: PSC Clock Divider (see psc_smbtmr) 45 * GCE: General Call Enable 46 * SFM: Standard/Fast Mode 47 * SLV: Slave Address 48 */ 49 #define SMBUS_CFG_RT (3u << 30) /* R/W */ 50 #define SMBUS_CFG_RT_SET(x) ((x & 0x3) << 30) 51 #define SMBUS_CFG_RT_FIFO1 0 52 #define SMBUS_CFG_RT_FIFO2 1 53 #define SMBUS_CFG_RT_FIFO4 2 54 #define SMBUS_CFG_RT_FIFO8 3 55 #define SMBUS_CFG_TT (3u << 28) /* R/W */ 56 #define SMBUS_CFG_TT_SET(x) ((x & 0x3) << 28) 57 #define SMBUS_CFG_TT_FIFO1 0 58 #define SMBUS_CFG_TT_FIFO2 1 59 #define SMBUS_CFG_TT_FIFO4 2 60 #define SMBUS_CFG_TT_FIFO8 3 61 #define SMBUS_CFG_DD (1u << 27) /* R/W */ 62 #define SMBUS_CFG_DE (1u << 26) /* R/W */ 63 #define SMBUS_CFG_DIV (3u << 13) /* R/W */ 64 #define SMBUS_CFG_DIV_SET(x) ((x & 0x3) << 13) 65 #define SMBUS_CFG_DIV2 0 /* PSC_CLK = pscn_mainclk / 2 */ 66 #define SMBUS_CFG_DIV4 1 /* PSC_CLK = pscn_mainclk / 4 */ 67 #define SMBUS_CFG_DIV8 2 /* PSC_CLK = pscn_mainclk / 8 */ 68 #define SMBUS_CFG_DIV16 3 /* PSC_CLK = pscn_mainclk / 16 */ 69 #define SMBUS_CFG_GCE (1u << 3) /* R/W */ 70 #define SMBUS_CFG_SFM (1u << 8) /* R/W */ 71 #define SMBUS_CFG_SLV (127u << 1) /* R/W */ 72 73 /* 74 * psc_smbmsk: SMBus Mask Register 75 * DN: Data Not-acknowledged 76 * AN: Address Not-acknowledged 77 * AL: Arbitration Lost 78 * RR: Mask Rx FIFO request interrupt 79 * RO: Mask Rx FIFO overflow interrupt 80 * RU: Mask Rx FIFO uderflow interrupt 81 * TR: Mask Tx FIFO request interrupt 82 * TO: Mask Tx FIFO overflow interrupt 83 * TU: Mask Tx FIFO uderflow interrupt 84 * SD: Mask Slave Done interrupt 85 * MD: Mask Master Done interrupt 86 */ 87 #define SMBUS_MSK_DN (1u << 30) /* R/W */ 88 #define SMBUS_MSK_AN (1u << 29) /* R/W */ 89 #define SMBUS_MSK_AL (1u << 28) /* R/W */ 90 #define SMBUS_MSK_RR (1u << 13) /* R/W */ 91 #define SMBUS_MSK_RO (1u << 12) /* R/W */ 92 #define SMBUS_MSK_RU (1u << 11) /* R/W */ 93 #define SMBUS_MSK_TR (1u << 10) /* R/W */ 94 #define SMBUS_MSK_TO (1u << 9) /* R/W */ 95 #define SMBUS_MSK_TU (1u << 8) /* R/W */ 96 #define SMBUS_MSK_SD (1u << 5) /* R/W */ 97 #define SMBUS_MSK_MD (1u << 4) /* R/W */ 98 #define SMBUS_MSK_ALLMASK (SMBUS_MSK_DN | SMBUS_MSK_AN | SMBUS_MSK_AL \ 99 | SMBUS_MSK_RR | SMBUS_MSK_RO | SMBUS_MSK_RU \ 100 | SMBUS_MSK_TR | SMBUS_MSK_TO | SMBUS_MSK_TU \ 101 | SMBUS_MSK_SD | SMBUS_MSK_MD) 102 103 /* 104 * psc_smbpcr: SMBus Protocol Control Register 105 * DC: Data Clear 106 * MS: Master Start 107 */ 108 #define SMBUS_PCR_DC (1u << 2) /* R/W */ 109 #define SMBUS_PCR_MS (1u << 0) /* R/W */ 110 111 /* 112 * psc_smbstat: SMBus Status Register 113 * BB: SMBus bus busy 114 * RF: Receive FIFO full 115 * RE: Receive FIFO empty 116 * RR: Receive request 117 * TF: Transfer FIFO full 118 * TE: Transfer FIFO empty 119 * TR: Transfer request 120 * SB: Slave busy 121 * MB: Master busy 122 * DI: Device interrupt 123 * DR: Device ready 124 * SR: PSC ready 125 */ 126 #define SMBUS_STAT_BB (1u << 28) /* Read only */ 127 #define SMBUS_STAT_RF (1u << 13) /* Read only */ 128 #define SMBUS_STAT_RE (1u << 12) /* Read only */ 129 #define SMBUS_STAT_RR (1u << 11) /* Read only */ 130 #define SMBUS_STAT_TF (1u << 10) /* Read only */ 131 #define SMBUS_STAT_TE (1u << 9) /* Read only */ 132 #define SMBUS_STAT_TR (1u << 8) /* Read only */ 133 #define SMBUS_STAT_SB (1u << 5) /* Read only */ 134 #define SMBUS_STAT_MB (1u << 4) /* Read only */ 135 #define SMBUS_STAT_DI (1u << 2) /* Read only */ 136 #define SMBUS_STAT_DR (1u << 1) /* Read only */ 137 #define SMBUS_STAT_SR (1u << 0) /* Read only */ 138 139 /* 140 * psc_smbevnt: SMBus Event Register 141 * DN: Data Not-acknowledged 142 * AN: Address Not-acknowledged 143 * AL: Arbitration Lost 144 * RR: Mask Rx FIFO request interrupt 145 * RO: Mask Rx FIFO overflow interrupt 146 * RU: Mask Rx FIFO uderflow interrupt 147 * TR: Mask Tx FIFO request interrupt 148 * TO: Mask Tx FIFO overflow interrupt 149 * TU: Mask Tx FIFO uderflow interrupt 150 * SD: Mask Slave Done interrupt 151 * MD: Mask Master Done interrupt 152 */ 153 #define SMBUS_EVNT_DN (1u << 30) /* R/W */ 154 #define SMBUS_EVNT_AN (1u << 29) /* R/W */ 155 #define SMBUS_EVNT_AL (1u << 28) /* R/W */ 156 #define SMBUS_EVNT_RR (1u << 13) /* R/W */ 157 #define SMBUS_EVNT_RO (1u << 12) /* R/W */ 158 #define SMBUS_EVNT_RU (1u << 11) /* R/W */ 159 #define SMBUS_EVNT_TR (1u << 10) /* R/W */ 160 #define SMBUS_EVNT_TO (1u << 9) /* R/W */ 161 #define SMBUS_EVNT_TU (1u << 8) /* R/W */ 162 #define SMBUS_EVNT_SD (1u << 5) /* R/W */ 163 #define SMBUS_EVNT_MD (1u << 4) /* R/W */ 164 165 /* 166 * psc_smbtxrx: SMBus Tx/Rx Data Register 167 * STP: Stop 168 * RSR: Restart 169 * ADDRDATA: Address/Data 170 */ 171 #define SMBUS_TXRX_STP (1u << 29) /* Write only */ 172 #define SMBUS_TXRX_RSR (1u << 28) /* Write only */ 173 #define SMBUS_TXRX_ADDRDATA (255u << 0) /* R/W */ 174 175 176 /* 177 * psc_smbtmr: SMBus Protocol Timers Register 178 * TH: Tx Data Hold Timer 179 * PS: Stop->Start Buffer Timer 180 * PU: Stop Setup Timer 181 * SH: Start Hold Timer 182 * SU: Start Setup Timer 183 * CL: Clock Low 184 * CH: Clock High 185 * 186 * [SMBus Timing Parameter Values] 187 * 188 * Standard Mode Fast Mode 189 * Timer Name (pscn_mainclk/8) = 6.25MHz (pscn_mainclk/2) = 25MHz 190 * Time unit = 160ns Time unit = 40ns 191 * psc_smbtmr Bus Timings psc_smbtmr Bus Timings 192 * Tx Hold TX = 0x00 480ns TH = 0x02 320ns 193 * Stop->Start PS = 0x0F 4800ns PS = 0x0F 1320ns 194 * Stop Setup PU = 0x0F 4000ns PU = 0x0B 600ns 195 * Start Hold SH = 0x0F 4000ns SH = 0x0B 600ns 196 * Start Setup SU = 0x0F 4800ns SU = 0x0B 600ns 197 * Clock Low CL = 0x0F 4800ns CL = 0x0F 1320ns 198 * Clock High CH = 0x0F 4000ns CH = 0x0B 600ns 199 */ 200 #define SMBUS_TMR_TH (3u << 30) /* R/W */ 201 #define SMBUS_TMR_TH_SET(x) ((x & 0x3) << 30) 202 #define SMBUS_TMR_PS (31u << 25) /* R/W */ 203 #define SMBUS_TMR_PS_SET(x) ((x & 0x1f) << 25) 204 #define SMBUS_TMR_PU (31u << 20) /* R/W */ 205 #define SMBUS_TMR_PU_SET(x) ((x & 0x1f) << 20) 206 #define SMBUS_TMR_SH (31u << 15) /* R/W */ 207 #define SMBUS_TMR_SH_SET(x) ((x & 0x1f) << 15) 208 #define SMBUS_TMR_SU (31u << 10) /* R/W */ 209 #define SMBUS_TMR_SU_SET(x) ((x & 0x1f) << 10) 210 #define SMBUS_TMR_CL (31u << 5) /* R/W */ 211 #define SMBUS_TMR_CL_SET(x) ((x & 0x1f) << 5) 212 #define SMBUS_TMR_CH (31u << 0) /* R/W */ 213 #define SMBUS_TMR_CH_SET(x) ((x & 0x1f) << 0) 214 215 /* Standard Mode */ 216 #define SMBUS_TMR_STD_TH 0x0 217 #define SMBUS_TMR_STD_PS 0xf 218 #define SMBUS_TMR_STD_PU 0xf 219 #define SMBUS_TMR_STD_SH 0xf 220 #define SMBUS_TMR_STD_SU 0xf 221 #define SMBUS_TMR_STD_CL 0xf 222 #define SMBUS_TMR_STD_CH 0xf 223 224 /* Fast Mode */ 225 #define SMBUS_TMR_FAST_TH 0x2 226 #define SMBUS_TMR_FAST_PS 0xf 227 #define SMBUS_TMR_FAST_PU 0xb 228 #define SMBUS_TMR_FAST_SH 0xb 229 #define SMBUS_TMR_FAST_SU 0xb 230 #define SMBUS_TMR_FAST_CL 0xf 231 #define SMBUS_TMR_FAST_CH 0xb 232 233 #endif /* _MIPS_ALCHEMY_AUSMBUS_PSCREG_H_ */ 234
Indexes created Sat Oct 04 05:10:05 GMT 2025