NetBSD Cross-Reference & Source Code Search Engine

Home	Sort by: relevance \| last modified time \| path

Full Search

in project(s):

Definition

Symbol

File Path

History

| | Help

Searched defs:SMU__NUM_PCIE_DPM_LEVELS (Results 1 - 9 of 9) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
ci_smumgr.h	`31 #define SMU__NUM_PCIE_DPM_LEVELS 8`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
kv_dpm.h	`31 #define SMU__NUM_PCIE_DPM_LEVELS 0 /* ??? */`
/src/sys/external/bsd/drm2/dist/drm/radeon/
kv_dpm.h	`31 #define SMU__NUM_PCIE_DPM_LEVELS 0 /* ??? */`
ci_dpm.h	`34 #define SMU__NUM_PCIE_DPM_LEVELS 8`
/src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
smu71.h	`32 #define SMU__NUM_PCIE_DPM_LEVELS 8 66 #define SMU71_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS`
smu72.h	`36 #define SMU__NUM_PCIE_DPM_LEVELS 8 114 #define SMU72_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS /* PCIe speed and number of lanes. */`
smu73.h	`98 #define SMU__NUM_PCIE_DPM_LEVELS 8 113 #define SMU73_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS // PCIe speed and number of lanes.`
smu74.h	`37 #define SMU__NUM_PCIE_DPM_LEVELS 8 139 #define SMU74_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS /* PCIe speed and number of lanes */`
smu75.h	`45 #define SMU__NUM_PCIE_DPM_LEVELS 8 60 #define SMU75_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS`

Completed in 55 milliseconds